
Warning-[DBGACC_DBG] Multiple debug options being used
  The debug switches '-debug_access' and '-debug*' are being used together.  
  For better performance, consider using only '-debug_access'.

                         Chronologic VCS (TM)
        Version O-2018.09-1_Full64 -- Tue Aug  5 21:54:17 2025
               Copyright (c) 1991-2018 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '../rtl/sync_fifo_128_to_64.v'
Parsing design file '../rtl/sync_fifo.v'
Parsing design file '../rtl/rchannel.v'
Parsing design file '../tb/tb_rchannel.v'
Top Level Modules:
       tb_rchannel
TimeScale is 1 ns / 1 ps
Starting vcs inline pass...
1 module and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared  -Bsymbolic  -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o 
rm -f _csrc0.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib     _12247_archive_1.so _prev_archive_1.so _csrc0.so  SIM_l.o  _csrc0.so     rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive        _vcs_pli_stub_.o   /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl 
../simv up to date
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64;  Aug  5 21:54 2025
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi* : Create FSDB file 'tb.fsdb'
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
*Verdi* : Enable +all dumping.
*Verdi* : End of traversing.
$finish called from file "../tb/tb_rchannel.v", line 64.
$finish at simulation time               365000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 365000 ps
CPU Time:      0.570 seconds;       Data structure size:   0.0Mb
Tue Aug  5 21:54:18 2025
CPU time: .334 seconds to compile + .316 seconds to elab + .256 seconds to link + .607 seconds in simulation
