module tb_rchannel;
reg clk;
reg rst_n;
reg axi_s_arvalid;
reg [25:0] axi_s_araddr;
reg [7:0]  axi_s_arlen;
wire        axi_s_arready;
wire [63:0] axi_s_rdata;
wire        axi_s_rvalid;
wire        axi_s_rlast;
wire [159:0] rframe_data;
wire        rframe_valid;
reg        rframe_ready;
reg [127:0] array2axi_rdata;
reg         array2axi_rdata_valid;

rchannel u_rchannel(
    .clk        (clk),
    .rst_n      (rst_n),
    .axi_s_arvalid(axi_s_arvalid),
    .axi_s_araddr(axi_s_araddr),
    .axi_s_arlen(axi_s_arlen),
    .axi_s_arready(axi_s_arready),
    .axi_s_rdata(axi_s_rdata),
    .axi_s_rvalid(axi_s_rvalid),
    .axi_s_rlast(axi_s_rlast),
    .rframe_data(rframe_data),
    .rframe_valid(rframe_valid),
    .rframe_ready(rframe_ready),
    .array2axi_rdata(array2axi_rdata),
    .array2axi_rdata_valid(array2axi_rdata_valid)
);

initial begin
    clk = 1'd0;
    forever begin
        #10; clk = ~clk;
    end
end

initial begin
    rst_n = 1'b0;
    axi_s_arvalid = 'd0;
    axi_s_araddr = 'd0;
    axi_s_arlen = 'd0;
    rframe_ready = 1'b1;
    array2axi_rdata = 'd0;
    array2axi_rdata_valid = 'd0;
    @(posedge clk) begin
        rst_n <= 1'b1;
    end
    ar({16'h1,6'h3f,4'h0},8'd9);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    arrayrdata({64'h2,64'h1});
    arrayrdata({64'h4,64'h3});
    arrayrdata({64'h6,64'h5});
    arrayrdata({64'h8,64'h7});
    arrayrdata({64'ha,64'h9});
    #15;
    $finish;
end

task ar;
input [25:0] araddr;
input [7:0] arlen;
begin
@(posedge clk) begin
    axi_s_arvalid <= 1'b1;
    axi_s_araddr <= araddr;
    axi_s_arlen <= arlen;
    #1;
    wait(axi_s_arready);
    @(posedge clk) begin
        axi_s_arvalid <= 1'b0;
    end
end
end
endtask

task arrayrdata;
input [127:0] rdata;
begin
@(posedge clk) begin
    array2axi_rdata <= rdata;
    array2axi_rdata_valid <= 1'b1;
end
@(posedge clk) begin
    array2axi_rdata_valid <= 1'b0;
end
end
endtask

initial begin
    $fsdbDumpfile("tb.fsdb");
    $fsdbDumpvars(0,tb_rchannel,"+all");
end

endmodule



