`timescale 1ns/1ps
module tb_sync_fifo;
parameter DATA_WIDTH = 30;
parameter FIFO_DEPTH = 4;
reg clk;
reg rst_n;
reg wr_en;
reg [DATA_WIDTH -1:0] wr_data;
wire full;
reg rd_en;
wire [DATA_WIDTH -1:0] rd_data;
wire empty;

sync_fifo #(
    .DATA_WIDTH(DATA_WIDTH),
    .FIFO_DEPTH(FIFO_DEPTH)
) u_sync_fifo(
    .clk(clk),
    .rst_n(rst_n),
    .wr_en(wr_en),
    .wr_data(wr_data),
    .full(full),
    .rd_en(rd_en),
    .rd_data(rd_data),
    .empty(empty)
);

initial begin
    clk = 0;
    forever begin
        #10;
        clk = ~clk;
    end
end

initial begin
init;
push;
pop;
$fsdbDumpfile("tb.fsdb");
$fsdbDumpvars(0,tb_sync_fifo);
#100;
$finish;
end

task init;
begin
    rst_n = 0;
    #30;
    rst_n = 1'b1;
    wr_en = 'b0;
    wr_data = 'd0;
    rd_en = 'b0;
end
endtask

integer i;
task push;
begin
for(i=0;i<=20;i=i+1) begin
@(posedge clk) begin
    wr_data <= {$random}%DATA_WIDTH + 5'd20;
    wr_en <= 1;
    if(!full) begin
    $display("write data is %0d",wr_data);
    end else begin
    $display("fifo is full!");
    end
end
end
wr_en <= 0;
end
endtask

task pop;
begin
for(i=0;i<=20;i=i+1) begin
    @(negedge clk) begin
        rd_en <= 1;
        if(!empty) begin
        $display("read data is %0d",rd_data);
        end else begin
        $display("fifo is empty!");
        end
    end
end
rd_en = 0;
end
endtask




endmodule



