SpyGlass run started at 11:06:16  on 8 05 2025 

SpyGlass Predictive Analyzer(R) - Version SpyGlass_vL-2016.06
Last compiled on May 20 2016

All Rights Reserved. Use, disclosure or duplication
without prior written permission of Synopsys Inc. is prohibited.
Technical support: email spyglass_support@synopsys.com.


Running SpyGlass 64-bit Executable: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/obj/check.Linux4

RULE-CHECKING IN MIXED MODE
Loading Policy: spyglass (Version: SpyGlass_vL-2016.06) from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/spyglass
Loading Shared library libspyglassrules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libspyglassrules-Linux4.spyso 
Loading Shared library libsdcInitRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libsdcInitRules-Linux4.spyso 
Loading Shared library librmerules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/librmerules-Linux4.spyso 
Loading perl file for 'openmore' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/openmore/openmore-policy.pl
Version of Policy 'openmore': SpyGlass_vL-2016.06
Loading Shared library libCoreRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libCoreRules-Linux4.spyso 
Loading Shared library libLexRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libLexRules-Linux4.spyso 
Loading Shared library libVeLint-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libVeLint-Linux4.spyso 
Loading Shared library libVhLint-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libVhLint-Linux4.spyso 
Loading perl file for 'starc' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc/starc-policy.pl
Version of Policy 'starc': SpyGlass_vL-2016.06
Loading Shared library libVeStarc-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc/libVeStarc-Linux4.spyso 
Loading Shared library libVhStarc-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc/libVhStarc-Linux4.spyso 
Loading perl file for 'starc2005' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2005/starc2005-policy.pl
Version of Policy 'starc2005': SpyGlass_vL-2016.06
Loading Shared library libVeStarc2002-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2002/libVeStarc2002-Linux4.spyso 
Loading Shared library libVhStarc2002-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2002/libVhStarc2002-Linux4.spyso 
Loading Shared library libVmixedStarc2002-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2002/libVmixedStarc2002-Linux4.spyso 
Loading Shared library libVeStarc2005-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2005/libVeStarc2005-Linux4.spyso 
Loading Shared library libVmixedStarc2005-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2005/libVmixedStarc2005-Linux4.spyso 
Loading Shared library libVhStarc2005-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2005/libVhStarc2005-Linux4.spyso 
Loading perl file for 'erc' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/erc/erc-policy.pl
Version of Policy 'erc': SpyGlass_vL-2016.06
Loading Shared library liberc-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/erc/liberc-Linux4.spyso 
Loading perl file for 'simulation' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/simulation/simulation-policy.pl
Version of Policy 'simulation': SpyGlass_vL-2016.06
Loading Shared library libvcs-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/simulation/libvcs-Linux4.spyso 
Loading perl file for 'lint' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/lint/lint-policy.pl
Version of Policy 'lint': SpyGlass_vL-2016.06
Loading perl file for 'latch' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/latch/latch-policy.pl
Version of Policy 'latch': SpyGlass_vL-2016.06
Loading Shared library liblatch-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/latch/liblatch-Linux4.spyso 
Loading perl file for 'spyglass' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/spyglass/spyglass-policy.pl
Loading perl file for 'morelint' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/morelint/morelint-policy.pl
Version of Policy 'morelint': SpyGlass_vL-2016.06
Loading Shared library libVeMoreLint-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/morelint/libVeMoreLint-Linux4.spyso 
Loading Shared library libVhMoreLint-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/morelint/libVhMoreLint-Linux4.spyso 
Loading perl file for 'timing' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/timing/timing-policy.pl
Version of Policy 'timing': SpyGlass_vL-2016.06
Loading Shared library libtiming-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/timing/libtiming-Linux4.spyso 
Version of Policy 'starc2002': SpyGlass_vL-2016.06

------------------------------------------------------
      Table of Successfully Overloaded Rules
  RuleName            Language          PolicyName
   FieldName    Original Value/Overloaded Value
------------------------------------------------------
  STARC05-1.1.1.1     Verilog           starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-1.1.1.1     VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-1.1.1.2     Verilog           starc2005
   SEVERITY:    Recommended/Mandatory

  STARC05-1.1.1.2     VHDL              starc2005
   SEVERITY:    Recommended/Mandatory

  STARC05-1.1.1.5     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-1.1.1.5     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-1.1.1.10    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory
   ORDER:       1/1

  STARC05-1.1.1.10    VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory
   ORDER:       1/1

  STARC05-1.1.2.2     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.2     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.3     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.4     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.4     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.2.5     Verilog           starc2005
   SEVERITY:    Recommended/Reference

  STARC05-1.1.2.5     VHDL              starc2005
   SEVERITY:    Recommended/Reference

  STARC05-1.1.2.6a    Verilog           starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-1.1.2.6a    VHDL              starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-1.1.2.6b    Verilog           starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-1.1.2.6b    VHDL              starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-1.1.3.1     Verilog           starc2005
   SEVERITY:    Recommended/Reference

  STARC05-1.1.3.1     VHDL              starc2005
   SEVERITY:    Recommended/Reference

  STARC05-1.1.4.7     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.4.7     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.5.2a    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.5.2a    VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.5.2c    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.5.2c    VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-1.1.5.3     Verilog           starc2005
   SEVERITY:    Reference/Reference

  STARC05-1.1.5.3     VHDL              starc2005
   SEVERITY:    Reference/Reference

  STARC05-1.2.1.1a    Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-1.2.1.1b    Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-1.2.1.2     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Error

  STARC05-1.2.1.3     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Mandatory

  STARC05-1.3.1.2     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended3
   ORDER:       1/0

  STARC05-1.3.1.2     VHDL              starc2005
   SEVERITY:    Mandatory/Recommended3
   ORDER:       1/0

  STARC05-1.3.1.3     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Warning

  STARC05-1.3.1.5a    Verilog           starc2005
   SEVERITY:    Prohibited/Recommended3
   ORDER:       1/0

  STARC05-1.3.1.5a    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended3
   ORDER:       1/1

  STARC05-1.3.1.5b    Verilog           starc2005
   SEVERITY:    Prohibited/Recommended3
   ORDER:       1/0

  STARC05-1.3.1.5b    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended3
   ORDER:       1/1

  STARC05-1.3.1.6     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-1.3.2.1a    Verilog+VHDL      starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-1.3.2.2     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Recommended1

  STARC05-1.4.1.1     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-1.4.3.1c    Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-1.4.3.2     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-1.4.3.4     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Warning

  STARC05-1.4.3.6     Verilog           starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-1.4.3.6     VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-1.5.1.1     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-1.5.1.2     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-1.6.1.4     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory
   ORDER:       0/1

  STARC05-1.6.1.4     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory
   ORDER:       0/1

  Prereqs_STARC05-1.6.2.1  Verilog+VHDL      starc2005
   SEVERITY:    Data/Data

  STARC05-1.6.2.1     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-1.6.2.2     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Recommended1
   ORDER:       1/0

  STARC05-2.1.6.2     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.1.6.2     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.1.6.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.1.6.3     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.2.2.1     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.2.2.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.2.2.2a    Verilog           starc2005
   SEVERITY:    Recommended2/Recommended2

  STARC05-2.2.2.2a    VHDL              starc2005
   SEVERITY:    NULL/Recommended2

  STARC05-2.3.1.1     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.3.1.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.3.1.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.3.1.3     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.3.1.4     Verilog           starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.3.1.4     VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.3.1.5a    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.3.1.5a    VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.3.3.1     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.3.3.1     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.3.3.2a    Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.3.3.2a    VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.3.3.2b    Verilog           starc2005
   SEVERITY:    Reference/Reference

  STARC05-2.3.3.2b    VHDL              starc2005
   SEVERITY:    Reference/Reference

  STARC05-2.3.5.1     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Recommended1

  STARC05-2.3.6.1     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Recommended1

  STARC05-2.4.1.2     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.4.1.3     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.4.1.3     VHDL              starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.4.1.4     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Mandatory

  STARC05-2.4.1.5     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Error

  STARC05-2.5.1.2     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Recommended2
   ORDER:       1/0

  STARC05-2.5.1.4     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.5.1.6     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.5.1.7     Verilog           starc2005
   SEVERITY:    Recommended2/Warning
   ORDER:       1/0

  STARC05-2.5.1.7     VHDL              starc2005
   SEVERITY:    Recommended2/Warning
   ORDER:       1/0

  STARC05-2.5.1.8     Verilog           starc2005
   SEVERITY:    Recommended2/Recommended2
   ORDER:       1/0

  STARC05-2.5.1.8     VHDL              starc2005
   SEVERITY:    Recommended2/Recommended2
   ORDER:       1/0

  STARC05-2.5.2.1     Verilog+VHDL      starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.6.1.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.6.1.3     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.6.2.1     Verilog           starc2005
   SEVERITY:    Caution/Mandatory

  STARC05-2.6.2.1     VHDL              starc2005
   SEVERITY:    Caution/Mandatory

  STARC05-2.7.1.3a    Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.7.1.3a    VHDL              starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.7.1.3b    Verilog           starc2005
   SEVERITY:    NULL/Recommended3
   ORDER:       1/0

  STARC05-2.7.1.3b    VHDL              starc2005
   SEVERITY:    Reference/Recommended3
   ORDER:       1/1

  STARC05-2.7.2.1     Verilog           starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-2.7.2.1     VHDL              starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-2.7.3.4     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.7.3.4     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.8.1.4     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.8.1.4     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.8.3.1     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.8.3.1     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/1

  STARC05-2.9.1.1     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-2.9.1.1     VHDL              starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-2.9.2.1     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.2.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.2.2     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       0/0

  STARC05-2.9.2.2     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.9.2.4     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.2.4     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.10.6.6    Verilog           starc2005
   SEVERITY:    Recommended3/Recommended3
   ORDER:       1/0

  STARC05-2.10.6.6    VHDL              starc2005
   SEVERITY:    Recommended3/Recommended3
   ORDER:       1/1

  STARC05-2.10.7.1    Verilog           starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.10.7.1    VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.11.2.1    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.11.2.1    VHDL              starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.11.3.1    Verilog           starc2005
   SEVERITY:    Recommended/Warning
   ORDER:       1/0

  STARC05-2.11.3.1    VHDL              starc2005
   SEVERITY:    Recommended/Warning
   ORDER:       1/1

  STARC05-2.11.4.1    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-2.11.4.1    VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.2.7     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory
   ORDER:       0/1

  STARC05-3.1.2.7     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory
   ORDER:       0/1

  STARC05-3.1.4.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.4.3     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.4.4     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.4.4     VHDL              starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.4.5     Verilog           starc2005
   SEVERITY:    Reference/Recommended3

  STARC05-3.1.4.5     VHDL              starc2005
   SEVERITY:    Reference/Recommended3

  STARC05-3.3.1.1     Verilog+VHDL      starc2005
   SEVERITY:    NULL/Mandatory

  STARC05-3.3.1.4a    Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.3.2.2     Verilog+VHDL      starc2005
   SEVERITY:    Recommended3/Recommended3
   ORDER:       1/0

  STARC05-3.3.2.3     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.3.3.1     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.3.6.2     Verilog+VHDL      starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.5.3.1     Verilog           starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-3.5.3.1     VHDL              starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-3.5.6.4     Verilog           starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-3.5.6.4     VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-1.1.4.5     Verilog           starc2005
   SEVERITY:    Reference/Reference

  STARC05-1.4.4.2     Verilog           starc2005
   SEVERITY:    Reference/Reference

  STARC05-2.1.3.2     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.3.5     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.4.1     Verilog           starc2005
   SEVERITY:    Recommended/Reference

  STARC05-2.1.4.5     Verilog           starc2005
   SEVERITY:    Mandatory/Warning

  STARC05-2.1.4.6a    Verilog           starc2005
   SEVERITY:    NULL/Recommended3

  STARC05-2.1.4.6b    Verilog           starc2005
   SEVERITY:    Caution/Recommended3

  STARC05-2.1.5.3     Verilog           starc2005
   SEVERITY:    Recommended/Warning
   ORDER:       1/0

  STARC05-2.1.6.4     Verilog           starc2005
   SEVERITY:    Caution/Recommended2
   ORDER:       1/0

  STARC05-2.1.6.5     Verilog           starc2005
   SEVERITY:    Mandatory/Warning

  STARC05-2.2.2.2b    Verilog           starc2005
   SEVERITY:    Recommended2/Recommended2

  STARC05-2.2.3.1     Verilog           starc2005
   SEVERITY:    Recommended/Mandatory

  STARC05-2.2.3.2     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.2.3.3     Verilog           starc2005
   SEVERITY:    Prohibited/Warning

  STARC05-2.3.1.5b    Verilog           starc2005
   SEVERITY:    Mandatory/Error

  STARC05-2.3.1.6     Verilog           starc2005
   SEVERITY:    Mandatory/Warning

  STARC05-2.3.2.1     Verilog           starc2005
   SEVERITY:    Caution/Reference

  STARC05-2.3.4.2     Verilog           starc2005
   SEVERITY:    Caution/Mandatory

  STARC05-2.5.1.9     Verilog           starc2005
   SEVERITY:    Recommended2/Warning
   ORDER:       1/0

  STARC05-2.7.4.3     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.8.1.5     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.8.1.6     Verilog           starc2005
   SEVERITY:    Caution/Recommended2
   ORDER:       1/0

  STARC05-2.8.3.5     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.8.3.7     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.8.4.1a    Verilog           starc2005
   SEVERITY:    Caution/Reference
   ORDER:       1/0

  STARC05-2.8.4.1b    Verilog           starc2005
   SEVERITY:    Caution/Reference
   ORDER:       1/0

  STARC05-2.8.4.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3
   ORDER:       1/0

  STARC05-2.8.4.4     Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.8.5.1     Verilog           starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.8.5.2     Verilog           starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.8.5.3     Verilog           starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.8.5.4     Verilog           starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.9.1.2a    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.1.2b    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.1.2c    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.1.2d    Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.10.1.7    Verilog           starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.10.2.3    Verilog           starc2005
   SEVERITY:    Prohibited/Warning

  STARC05-2.10.3.2a   Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.10.3.2b   Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.10.3.2c   Verilog           starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.10.3.5    Verilog           starc2005
   SEVERITY:    NULL/Recommended2
   ORDER:       1/0

  STARC05-2.10.3.6    Verilog           starc2005
   SEVERITY:    Recommended/Mandatory
   ORDER:       0/1

  STARC05-2.10.5.5    Verilog           starc2005
   SEVERITY:    Recommended2/Recommended2
   ORDER:       1/0

  STARC05-2.10.6.1    Verilog           starc2005
   SEVERITY:    NULL/Recommended3
   ORDER:       1/0

  STARC05-2.11.4.2    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.3.1     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.3.4a    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.1.3.4b    Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.2.2.3     Verilog           starc2005
   SEVERITY:    Recommended/Recommended3

  STARC05-3.2.2.5     Verilog           starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-3.2.2.7     Verilog           starc2005
   SEVERITY:    NULL/Recommended3

  STARC05-3.2.3.2     Verilog           starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.2.4.3     Verilog           starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-3.5.6.7     Verilog           starc2005
   SEVERITY:    Recommended3/Recommended3

  STARC05-2.10.3.7    Verilog           starc2005
   SEVERITY:    NULL/Recommended2

  STARC05-1.1.1.3vb   VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-1.1.4.1vb   VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-1.1.6.4     VHDL              starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.1.1.3     VHDL              starc2005
   SEVERITY:    Recommended2/Recommended2

  STARC05-2.1.2.6     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.3.3     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.7.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory
   ORDER:       0/1

  STARC05-2.1.7.3     VHDL              starc2005
   SEVERITY:    Recommended/Reference

  STARC05-2.1.8.1     VHDL              starc2005
   SEVERITY:    Recommended/Reference

  STARC05-2.1.8.2     VHDL              starc2005
   SEVERITY:    Mandatory/Reference
   ORDER:       1/0

  STARC05-2.1.8.4     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.8.5a    VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.1.8.5b    VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.1.8.6     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.8.9     VHDL              starc2005
   SEVERITY:    Mandatory/Recommended1

  STARC05-2.1.8.10    VHDL              starc2005
   SEVERITY:    Mandatory/Recommended2

  STARC05-2.1.9.4     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.1.9.5     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory
   ORDER:       0/1

  STARC05-2.1.10.1    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.2    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.3    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.4    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.5    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.6    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended1

  STARC05-2.1.10.8    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended2
   ORDER:       1/0

  STARC05-2.1.10.9    VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.10.10   VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.1.10.11   VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.1.10.12   VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.1.10.13   VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.3.1.8     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-2.3.1.9     VHDL              starc2005
   SEVERITY:    Reference/Reference

  STARC05-2.3.2.4     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.9.3.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-2.10.1.2    VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.10.1.3    VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.10.4.3    VHDL              starc2005
   SEVERITY:    Recommended/Recommended1

  STARC05-2.10.4.7    VHDL              starc2005
   SEVERITY:    Recommended2/Recommended2

  STARC05-2.10.4.8    VHDL              starc2005
   SEVERITY:    Recommended1/Recommended1

  STARC05-2.10.7.2    VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.11.5.2    VHDL              starc2005
   SEVERITY:    Prohibited/Recommended2

  STARC05-3.1.3.5     VHDL              starc2005
   SEVERITY:    Recommended3/Recommended3
   ORDER:       1/0

  STARC05-3.1.6.1     VHDL              starc2005
   SEVERITY:    Recommended/Reference

  STARC05-3.1.6.2     VHDL              starc2005
   SEVERITY:    Caution/Reference

  STARC05-3.2.3.3     VHDL              starc2005
   SEVERITY:    Prohibited/Mandatory

  STARC05-3.2.4.1     VHDL              starc2005
   SEVERITY:    Mandatory/Mandatory

  STARC05-3.5.6.3a    VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-3.5.6.3b    VHDL              starc2005
   SEVERITY:    Recommended/Recommended2

  STARC05-2.3.1.2c    Verilog           starc2005
   SEVERITY:    Mandatory/Error

  W421                Verilog           lint
   SEVERITY:    Warning/Error

  W421                VHDL              lint
   SEVERITY:    Warning/Error

  sim_race02          Verilog           simulation
   SEVERITY:    Race/Warning

  W416                VHDL              lint
   SEVERITY:    Warning/Error

  PragmaComments-ML   Verilog           morelint
   SEVERITY:    Info/Data

  PragmaComments-ML   VHDL              morelint
   SEVERITY:    Info/Data

  W289                Verilog           lint
   SEVERITY:    Warning/Error

  W293                Verilog           lint
   SEVERITY:    Warning/Error

  W293                VHDL              lint
   SEVERITY:    Warning/Error

  W352                Verilog           lint
   SEVERITY:    Warning/Error

  W398                Verilog           lint
   SEVERITY:    Warning/Error

  W398                VHDL              lint
   SEVERITY:    Warning/Error

  W422                Verilog           lint
   SEVERITY:    Warning/Error

  W422                VHDL              lint
   SEVERITY:    Warning/Error

  W71                 Verilog           lint
   SEVERITY:    Warning/Error

  W71                 VHDL              lint
   SEVERITY:    Warning/Error

  ParamWidthMismatch-ML  Verilog           morelint
   SEVERITY:    NULL/Warning

  ReportPortInfo-ML   Verilog+VHDL      morelint
   SEVERITY:    Info/Data

  STARC05-2.1.3.1     Verilog           starc2005
   SEVERITY:    NULL/Warning

  W110                Verilog           lint
   SEVERITY:    Warning/Error

  W122                Verilog           lint
   SEVERITY:    Warning/Error

  W122                VHDL              lint
   SEVERITY:    Warning/Error

  W123                Verilog           lint
   SEVERITY:    NULL/Error

  W123                VHDL              lint
   SEVERITY:    NULL/Error

  W19                 Verilog           lint
   SEVERITY:    Warning/Error

  W218                Verilog           lint
   SEVERITY:    Warning/Error

  W505                Verilog           lint
   SEVERITY:    Warning/Error

  W505                VHDL              lint
   SEVERITY:    Warning/Error

  W66                 Verilog           lint
   SEVERITY:    Warning/Error

  InferLatch          Verilog+VHDL      openmore
   SEVERITY:    NULL/Error

  RegInputOutput-ML   Verilog+VHDL      morelint
   SEVERITY:    NULL/Data

  STARC05-2.3.4.1v    VHDL              starc2005
   SEVERITY:    NULL/Warning

  W336                Verilog           lint
   SEVERITY:    NULL/Error

  W414                Verilog           lint
   SEVERITY:    Warning/Error

  W450L               Verilog           latch
   SEVERITY:    Info/Warning

  UndrivenInTerm-ML   Verilog+VHDL      morelint
   SEVERITY:    NULL/Error

  BufClock            Verilog+VHDL      openmore
   SEVERITY:    Guideline/Warning

  checkPinConnectedToSupply  Verilog+VHDL      erc
   SEVERITY:    NULL/Error

  CombLoop            Verilog+VHDL      openmore
   SEVERITY:    (MsgLabel: CombLoop) Guideline/Error

  FlopClockConstant   Verilog+VHDL      erc
   SEVERITY:    (MsgLabel: FlopClockConstant) Warning/Error

  LatchFeedback       Verilog+VHDL      latch
   SEVERITY:    NULL/Error

  W415                Verilog+VHDL      lint
   SEVERITY:    (MsgLabel: W415) Warning/Error

  STARC02-1.1.5.1     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.5.1     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.5.3     Verilog           ---
   SEVERITY:    Reference/Reference

  STARC02-1.1.5.3     VHDL              ---
   SEVERITY:    Reference/Reference

  STARC02-1.1.5.4     Verilog           ---
   SEVERITY:    Reference/Reference

  STARC02-1.1.5.4     VHDL              ---
   SEVERITY:    Reference/Reference

  Prereqs_STARC02-1.6.2.1  Verilog+VHDL      ---
   SEVERITY:    Data/Data

  STARC02-1.6.2.1     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.2.1.2     Verilog+VHDL      ---
   SEVERITY:    Recommended/Reference

  STARC02-2.4.1.2     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.5.1.1     Verilog+VHDL      ---
   SEVERITY:    Mandatory/Recommended3

  STARC02-2.5.1.2     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended2

  STARC02-1.2.1.1a    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended1

  STARC02-1.2.1.1b    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended1

  STARC02-1.2.1.3     Verilog+VHDL      ---
   SEVERITY:    NULL/Mandatory

  STARC02-1.3.1.3     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-1.3.1.6     Verilog+VHDL      ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.3.2.1a    Verilog+VHDL      ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-1.3.2.1b    Verilog+VHDL      ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.3.2.2     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-1.4.1.1     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended1

  STARC02-1.4.3.1a    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.4.3.1b    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.4.3.2     Verilog+VHDL      ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.4.3.4     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-1.5.1.1     Verilog+VHDL      ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.5.1.2     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended1

  STARC02-1.5.1.5     Verilog+VHDL      ---
   SEVERITY:    Recommended/Reference

  STARC02-1.6.1.1     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.6.1.2     Verilog+VHDL      ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.6.2.2     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-1.6.2.2a    Verilog+VHDL      ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.6.3.1     Verilog+VHDL      ---
   SEVERITY:    Reference/Reference

  STARC02-1.6.3.2     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.5.1     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-2.3.6.1     Verilog+VHDL      ---
   SEVERITY:    NULL/Recommended1

  STARC02-2.5.1.4     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.5.2.1     Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.1.4.5     Verilog           ---
   SEVERITY:    Reference/Recommended3

  STARC02-3.1.4.5     VHDL              ---
   SEVERITY:    Reference/Recommended3

  STARC02-3.3.1.1     Verilog+VHDL      ---
   SEVERITY:    NULL/Mandatory

  STARC02-3.3.1.4a    Verilog+VHDL      ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.1.1.2     Verilog           ---
   SEVERITY:    Recommended/Mandatory

  STARC02-1.1.1.2     VHDL              ---
   SEVERITY:    Recommended/Mandatory

  STARC02-1.1.1.3a    Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-1.1.1.3a    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-1.1.1.8     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.1.8     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.1.10    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.1.1.10    VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.1.2.2     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.2     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.4     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.4     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.2.6a    Verilog           ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-1.1.2.6a    VHDL              ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-1.1.2.6b    Verilog           ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-1.1.2.6b    VHDL              ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-1.1.4.2     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.4.2     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.4.6     Verilog           ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-1.1.4.6     VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-1.1.4.7     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.4.7     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.4.8     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.1.4.8     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.4.9     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.1.4.9     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.3.1.2     Verilog           ---
   SEVERITY:    Mandatory/Recommended3

  STARC02-1.3.1.2     VHDL              ---
   SEVERITY:    Mandatory/Recommended3

  STARC02-1.6.1.4     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-1.6.1.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.1.1     Verilog           ---
   SEVERITY:    Recommended/Reference

  STARC02-2.1.1.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.1.2     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.1.2     VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.1.3.1     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.3.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.3.4     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.1.3.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.6.1     Verilog           ---
   SEVERITY:    NULL/Recommended2

  STARC02-2.1.6.1     VHDL              ---
   SEVERITY:    NULL/Recommended3

  STARC02-2.1.6.2     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.1.6.2     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.1.6.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.1.6.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.2.2.1     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.2.2.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.3.1.1     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.3.1.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.3.1.2a    Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.2a    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.2b    Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.2b    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.2c    Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.2c    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.1.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.2.2     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.2.2     VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.3.3.1     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.3.1     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.3.2     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.3.2     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.6.2a    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.6.2a    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.6.2b    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.3.6.2b    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.5.1.5a    Verilog           ---
   SEVERITY:    NULL/Mandatory

  STARC02-2.5.1.5a    VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.6.1.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.6.1.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.6.2.1     Verilog           ---
   SEVERITY:    Caution/Mandatory

  STARC02-2.6.2.1     VHDL              ---
   SEVERITY:    Caution/Mandatory

  STARC02-2.6.2.2     Verilog           ---
   SEVERITY:    Caution/Mandatory

  STARC02-2.6.2.2     VHDL              ---
   SEVERITY:    Caution/Mandatory

  STARC02-2.7.1.3a    Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.1.3a    VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.1.3b    Verilog           ---
   SEVERITY:    NULL/Recommended1

  STARC02-2.7.1.3b    VHDL              ---
   SEVERITY:    Reference/Recommended1

  STARC02-2.7.2.1     Verilog           ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.7.2.1     VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.7.3.1a    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.7.3.1a    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.7.3.1b    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.7.3.1b    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.7.3.3a    Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.3.3a    VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.3.3b    Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.3.3b    VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.3.3c    Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.7.3.3c    VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.8.1.4     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.8.1.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.8.3.1     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.8.3.1     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.9.1.1     Verilog           ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-2.9.1.1     VHDL              ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-2.9.2.1     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.2.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.2.2     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.9.2.2     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.9.2.3     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.9.2.3     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.9.2.4     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.2.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.10.3.1    Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.10.3.1    VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.10.6.5    Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.6.5    VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.11.1.4    Verilog           ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-2.11.1.4    VHDL              ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-2.11.2.1    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.2.1    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.3.1    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.3.1    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.4.1    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.4.1    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.4.4     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.4.4     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.5.2     Verilog           ---
   SEVERITY:    Recommended/Reference

  STARC02-3.1.5.2     VHDL              ---
   SEVERITY:    Reference/Reference

  STARC02-3.2.2.1     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.2.1     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.3.1     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-3.2.3.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-3.5.6.2a    Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.6.2a    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.6.4     Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.6.4     VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.3.4.1     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.4.1     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.4.1.3     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.4.1.3     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.1.5.2a    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.5.2a    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.5.2c    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.5.2c    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.3.2a    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.1.3.2b    Verilog+VHDL      ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.1.3.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.3.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-1.1.1.1     Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.1.1.1     VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.1.1.5     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-1.1.1.5     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-1.3.1.5a    Verilog           ---
   SEVERITY:    Prohibited/Recommended3

  STARC02-1.3.1.5a    VHDL              ---
   SEVERITY:    Prohibited/Recommended3

  STARC02-1.3.1.5b    Verilog           ---
   SEVERITY:    Prohibited/Recommended3

  STARC02-1.3.1.5b    VHDL              ---
   SEVERITY:    Prohibited/Recommended3

  STARC02-2.6.1.4     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.6.1.4     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.2.7     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-3.1.2.7     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-3.1.4.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.4.3     VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.5.3.1     Verilog           ---
   SEVERITY:    Recommended/Recommended1

  STARC02-3.5.3.1     VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-3.2.3.2     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-3.2.4.3     Verilog           ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-1.1.1.6     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.1.4.5     Verilog           ---
   SEVERITY:    Reference/Reference

  STARC02-2.1.3.2     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.3.5     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.4.5     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.1.4.6a    Verilog           ---
   SEVERITY:    NULL/Recommended3

  STARC02-2.1.4.6b    Verilog           ---
   SEVERITY:    Caution/Recommended3

  STARC02-2.1.5.3     Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.1.6.4     Verilog           ---
   SEVERITY:    Caution/Recommended2

  STARC02-2.2.3.2     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.2.3.3     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.1.5b    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.3.1.6     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.3.4.2     Verilog           ---
   SEVERITY:    Caution/Mandatory

  STARC02-2.7.4.3     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.8.1.3     Verilog           ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.8.1.5     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.8.1.6     Verilog           ---
   SEVERITY:    Caution/Recommended2

  STARC02-2.8.3.4a    Verilog           ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.8.3.4b    Verilog           ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.8.3.5     Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.8.4.1a    Verilog           ---
   SEVERITY:    Caution/Reference

  STARC02-2.8.4.1b    Verilog           ---
   SEVERITY:    Caution/Reference

  STARC02-2.8.4.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.8.4.4     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.8.5.1     Verilog           ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.8.5.2     Verilog           ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.8.5.3     Verilog           ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.8.5.4     Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.9.1.2a    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.1.2b    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.1.2c    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.9.1.2d    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.10.1.4b   Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.1.4c   Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.2.3    Verilog           ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.10.3.2a   Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.3.2b   Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.3.2c   Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.10.3.5    Verilog           ---
   SEVERITY:    NULL/Recommended1

  STARC02-2.10.3.6    Verilog           ---
   SEVERITY:    Recommended/Mandatory

  STARC02-2.10.4.5    Verilog           ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.10.5.1    Verilog           ---
   SEVERITY:    Caution/Reference

  STARC02-2.10.6.1    Verilog           ---
   SEVERITY:    NULL/Recommended3

  STARC02-2.11.4.2    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.3.1     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.3.4a    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.2.4     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-3.2.2.5     Verilog           ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.2.1     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.2.3.1     Verilog           ---
   SEVERITY:    Recommended/Mandatory

  STARC02-2.3.2.1     Verilog           ---
   SEVERITY:    Caution/Reference

  STARC02-1.4.4.1     Verilog           ---
   SEVERITY:    Reference/Reference

  STARC02-1.1.4.4     Verilog           ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-3.1.3.4b    Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.2.2     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.2.3     Verilog           ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.2.2.7     Verilog           ---
   SEVERITY:    NULL/Recommended3

  STARC02-1.1.1.3b    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-1.1.6.1     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-1.1.6.4     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.1.3.3     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.7.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.7.3     VHDL              ---
   SEVERITY:    Recommended/Reference

  STARC02-2.1.8.1     VHDL              ---
   SEVERITY:    Recommended/Reference

  STARC02-2.1.8.2     VHDL              ---
   SEVERITY:    Mandatory/Reference

  STARC02-2.1.8.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.8.5a    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.1.8.5b    VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.1.8.6     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.1.8.9     VHDL              ---
   SEVERITY:    Mandatory/Recommended1

  STARC02-2.1.8.10    VHDL              ---
   SEVERITY:    Mandatory/Recommended2

  STARC02-2.1.9.4     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.1.9.5     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.1.10.1    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.2    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.3    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.4    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.5    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.6    VHDL              ---
   SEVERITY:    Prohibited/Recommended1

  STARC02-2.1.10.8    VHDL              ---
   SEVERITY:    Prohibited/Recommended2

  STARC02-2.3.1.8     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-2.3.2.4     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.5.1.5b    VHDL              ---
   SEVERITY:    NULL/Mandatory

  STARC02-2.8.3.3     VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.9.3.1     VHDL              ---
   SEVERITY:    Mandatory/Mandatory

  STARC02-2.10.1.2    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.10.4.3    VHDL              ---
   SEVERITY:    Recommended/Recommended1

  STARC02-2.10.7.2    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-2.11.1.1    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-2.11.5.2    VHDL              ---
   SEVERITY:    Prohibited/Recommended2

  STARC02-3.1.3.2c    VHDL              ---
   SEVERITY:    Recommended/Recommended3

  STARC02-3.1.6.1     VHDL              ---
   SEVERITY:    Recommended/Reference

  STARC02-3.1.6.2     VHDL              ---
   SEVERITY:    Caution/Reference

  STARC02-3.2.3.3     VHDL              ---
   SEVERITY:    Prohibited/Mandatory

  STARC02-3.5.6.2b    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.6.3a    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-1.1.4.1b    VHDL              ---
   SEVERITY:    Recommended/Recommended2

  STARC02-3.5.6.3b    VHDL              ---
   SEVERITY:    Recommended/Recommended2
------------------------------------------------------


INFO [326]    SpyGlass Design Database './spyglass-1/tb_wchannel/.SG_SaveRestoreDB' can not be restored because:
              Following design files/directories have been modified since design save
    ../tb/tb_wchannel.v

              Saving Database again
Loading perl file for 'Audits' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/Audits/Audits-policy.pl
Version of Policy 'Audits': SpyGlass_vL-2016.06
Loading Shared library libVhAudits-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/Audits/libVhAudits-Linux4.spyso 
Loading Shared library libVeAudits-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/Audits/libVeAudits-Linux4.spyso 
Loading perl file for 'area' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/area/area-policy.pl
Version of Policy 'area': SpyGlass_vL-2016.06
Loading Shared library libarea-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/area/libarea-Linux4.spyso 
Loading perl file for 'miscellaneous' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/miscellaneous/miscellaneous-policy.pl
Version of Policy 'miscellaneous': SpyGlass_vL-2016.06
Loading Shared library libmiscellaneous-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/miscellaneous/libmiscellaneous-Linux4.spyso 
Loading perl file for 'starc2002' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starc2002/starc2002-policy.pl
Loading perl file for 'starcad-21' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starcad-21/starcad-21-policy.pl
Version of Policy 'starcad-21': SpyGlass_vL-2016.06
Loading Shared library libVmixedMetho-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/starcad-21/libVmixedMetho-Linux4.spyso 
Loading perl file for 'txv' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/txv/txv-policy.pl
Version of Policy 'txv': SpyGlass_vL-2016.06
Loading Shared library libtxv-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/txv/libtxv-Linux4.spyso 
Loading perl file for 'power_est' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/power_est/power_est-policy.pl
Version of Policy 'power_est': SpyGlass_vL-2016.06
Loading Shared library libBasePowerEst-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/power_est/libBasePowerEst-Linux4.spyso 
Loading perl file for 'lowpower' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/lowpower/lowpower-policy.pl
Version of Policy 'lowpower': SpyGlass_vL-2016.06
Loading Shared library libPwrRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/lowpower/libPwrRules-Linux4.spyso 
Loading Shared library libVeLowpower-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/lowpower/libVeLowpower-Linux4.spyso 
Loading Shared library libVhLowpower-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/lowpower/libVhLowpower-Linux4.spyso 
Loading perl file for 'dft_dsm' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/dft_dsm/dft_dsm-policy.pl
Version of Policy 'dft_dsm': SpyGlass_vL-2016.06
Loading Shared library libDftRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/dft/libDftRules-Linux4.spyso 
Loading perl file for 'dft' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/dft/dft-policy.pl
Version of Policy 'dft': SpyGlass_vL-2016.06
Loading perl file for 'constraints' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/constraints/constraints-policy.pl
Version of Policy 'constraints': SpyGlass_vL-2016.06
Loading Shared library libconstraints-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/constraints/libconstraints-Linux4.spyso 
Loading perl file for 'const_intern1' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/constraints/const_intern1-policy.pl
Version of Policy 'const_intern1': SpyGlass_vL-2016.06
Loading perl file for 'clock-reset' policy from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/clock/clock-reset-policy.pl
Version of Policy 'clock-reset': SpyGlass_vL-2016.06
Loading Shared library libclock-reset-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/clock/libclock-reset-Linux4.spyso 
Enabling Following Rules Only For Save:
 Ac_svasetup01
AcOvlRtl
AcOvlRtl
_meta_delay01
_vhMeta01
SGDC_meta_design_hier01
Ac_multitop01
_deltaDelay
_deltaDelay
_syncResetStyleRTL
Reset_check05
syncRstReq
syncRstReq
Pragma_setupa
_cdc_save_license01
PEMVDD01
PECHECK43
PECHECK18
PECHECK09
PESVASETUP01
PECHECK04
SGDC_power_est29
SGDC_power_est15
TxvVhMeta01
Txv_SvaSetup01
Prereqs_STARC-1.6.2.1
Prereqs_STARC05-1.6.2.1
GenTopLevelBlocksForAutoSoc
Total Rules Enabled Only For Save : 28
##build_id : SpyGlass_vL-2016.06
##system   : Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
##cwd      : /home/ICer/ic_prjs/mc/sim
##lang     : Verilog+VHDL
##args     : -mSpyGlass::Compatibility::v2_7_3 \
             -mSpyGlass::Compatibility::v2_7_3 \
             -mSpyGlass::Compatibility::v2_7_3 \
             -top 'tb_wchannel' \
             -lib WORK ./spyglass-1/tb_wchannel/WORK \
             -nl \
             -policy='openmore,starc,starc2005,erc,simulation,lint,latch,spyglass,morelint,timing' \
             -mixed \
             -batch \
             -rules='badimplicitSM1,badimplicitSM2,badimplicitSM4,BlockHeader,bothedges,STARC05-2.1.6.5,STARC05-2.3.1.2c,W421,W442a,W442b,W442c,W442f,sim_race02,W110a,W416,CheckDelayTimescale-ML,PragmaComments-ML,STARC05-2.10.2.3,STARC05-2.11.3.1,STARC05-2.3.1.5b,W215,W216,W289,W292,W293,W317,W352,W398,W422,W424,W426,W467,W480,W481a,W481b,W496a,W496b,W71,NoAssignX-ML,NoXInCase-ML,ParamWidthMismatch-ML,ReportPortInfo-ML,STARC05-2.1.3.1,STARC05-2.1.5.3,STARC05-2.2.3.3,STARC05-2.3.1.6,W110,W116,W122,W123,W19,W218,W240,W263,W337,W362,W486,W499,W502,W505,W66,InferLatch,RegInputOutput-ML,STARC05-2.3.4.1v,STARC05-2.5.1.7,STARC05-2.5.1.9,STARC05-2.10.3.2a,W336,W414,W450L,UndrivenInTerm-ML,BufClock,checkPinConnectedToSupply,CombLoop,FlopClockConstant,FlopEConst,FlopSRConst,LatchFeedback,STARC05-1.2.1.2,STARC05-1.3.1.3,STARC05-1.4.3.4,STARC05-2.1.4.5,STARC05-2.4.1.5,STARC05-2.5.1.2,W392,W415,STARC05-2.10.1.4a,STARC05-2.10.1.4b,W156,STARC05-2.3.3.1,W415a,W287b,W224,W287a,W528,mixedsenselist,W339a,STARC05-2.10.3.2a' \
             -wdir './spyglass-1/tb_wchannel/lint/lint_rtl' \
             -dbdir './spyglass-1/tb_wchannel/.SG_SaveRestoreDB' \
             -templatedir '/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff' \
             --goal_info 'lint/lint_rtl@' \
             --template_info 'lint/lint_rtl' \
             -overloadrules 'STARC05-2.1.6.5+severity=Warning,STARC05-2.3.1.2c+severity=Error,W421+severity=Error,sim_race02+severity=Warning,W416+severity=Error,PragmaComments-ML+severity=Data,STARC05-2.10.2.3+severity=Warning,STARC05-2.11.3.1+severity=Warning,STARC05-2.3.1.5b+severity=Error,W289+severity=Error,W293+severity=Error,W352+severity=Error,W398+severity=Error,W422+severity=Error,W71+severity=Error,ParamWidthMismatch-ML+severity=Warning,ReportPortInfo-ML+severity=Data,STARC05-2.1.3.1+severity=Warning,STARC05-2.1.5.3+severity=Warning,STARC05-2.2.3.3+severity=Warning,STARC05-2.3.1.6+severity=Warning,W110+severity=Error,W122+severity=Error,W123+severity=Error,W19+severity=Error,W218+severity=Error,W505+severity=Error,W66+severity=Error,InferLatch+severity=Error,RegInputOutput-ML+severity=Data,STARC05-2.3.4.1v+severity=Warning,STARC05-2.5.1.7+severity=Warning,STARC05-2.5.1.9+severity=Warning,W336+severity=Error,W414+severity=Error,W450L+severity=Warning,UndrivenInTerm-ML+severity=Error,BufClock+severity=Warning,checkPinConnectedToSupply+severity=Error,CombLoop+msgLabel=CombLoop+severity=Error,FlopClockConstant+msgLabel=FlopClockConstant+severity=Error,LatchFeedback+severity=Error,STARC05-1.2.1.2+severity=Error,STARC05-1.3.1.3+severity=Warning,STARC05-1.4.3.4+severity=Warning,STARC05-2.1.4.5+severity=Warning,STARC05-2.4.1.5+severity=Error,W415+msgLabel=W415+severity=Error' \
             -projectwdir './spyglass-1' \
             -enable_save_restore \
             -enable_fast_traversal \
             -enable_save_restore_builtin 'true' \
             -assume_driver_load=yes \
             -checkInHierarchy=yes \
             -checkRTLCInst=yes \
             -checkalldimension=yes \
             -checkconstassign=yes \
             -checkfullbus=yes \
             -checkfullrecord=yes \
             -chkTopModule=yes \
             -enableE2Q=yes \
             -ignoreModuleInstance=yes \
             -new_flow_width=yes \
             -nocheckoverflow=yes \
             -report_inferred_cell=yes \
             -reportundrivenout=no \
             -strict=W342,W343 \
             -treat_latch_as_combinational=yes \
             -64bit  \
             ../rtl/sync_fifo_64_to_128.v \
             ../rtl/sync_fifo.v \
             ../rtl/wchannel.v \
             ../tb/tb_wchannel.v

##verbosity level   : 2
##exact cmdline arg : -batch -project spyglass-1.prj -goal lint/lint_rtl -64bit
##spyglass_run.csh begins :
;	cd /home/ICer/ic_prjs/mc/sim
;	setenv SPYGLASS_LD_PRELOAD /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libsgjemalloc-Linux4.so
;	setenv SPYGLASS_DW_PATH /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/dw_support
;	/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/bin/spyglass  -batch -project spyglass-1.prj -goal lint/lint_rtl -64bit
##spyglass_run.csh ends
##files    : ../rtl/sync_fifo_64_to_128.v \
             ../rtl/sync_fifo.v \
             ../rtl/wchannel.v \
             ../tb/tb_wchannel.v

##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/openmore/CombLoopReport.rpt' in "w+" mode ...
##FILEDEBUG[spyOpenFile]: Opening file './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/lint/SignalUsageReport.rpt' in "a" mode...
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/lint/SignalUsageReport.rpt' in "a" mode ...
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/RegInputOutput' in "a" mode ...
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/morelint/ReportPortInfo' in "a" mode ...
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/morelint/ReportPortInfo.csv' in "a" mode ...
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/ReportPorts' in "a" mode ...

INFO [76]    Using `./spyglass-1/tb_wchannel/WORK/64' as the Work Directory for 64bit precompiled dump.
Checking Rule SGDC_power_est29 (Rule 1 of total 277) .... done (Time = 0.00s, Memory = -0.0K)
Checking Rule PECHECK04 (Rule 2 of total 277) .... done (Time = 0.03s, Memory = 23.4K)
Checking Rule PECHECK18 (Rule 3 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PEMVDD01 (Rule 4 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PrecompileLibCheck01 (Rule 5 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PrecompileLibCheck02 (Rule 6 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PrecompileLibCheck03 (Rule 7 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PrecompileLibCheck04 (Rule 8 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_assume_path01 (Rule 9 of total 277) .... done (Time = 0.00s, Memory = 0.1K)
Checking Rule SGDC_sdcschema02 (Rule 10 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_clock05 (Rule 11 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_clock09 (Rule 12 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_force_ta05 (Rule 13 of total 277) .... done (Time = 0.00s, Memory = 0.5K)
Checking Rule SGDC_require_path03 (Rule 14 of total 277) .... done (Time = 0.00s, Memory = 6.0K)
Checking Rule SGDC_require_value03 (Rule 15 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule SGDC_voltagedomain05 (Rule 16 of total 277) .... done (Time = 0.00s, Memory = 3.4K)
Checking Rule SGDC_voltagedomain06 (Rule 17 of total 277) .... done (Time = 0.00s, Memory = 4.0K)
Checking Rule SGDC_voltagedomain07 (Rule 18 of total 277) .... done (Time = 0.00s, Memory = 34.8K)
Checking Rule SGDC_powerdomainoutputs02 (Rule 19 of total 277) .... done (Time = 0.00s, Memory = 6.9K)
Checking Rule SGDC_supply01 (Rule 20 of total 277) .... done (Time = 0.00s, Memory = -24.6K)
Checking Rule SGDC_waive01 (Rule 21 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive02 (Rule 22 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive03 (Rule 23 of total 277) .... done (Time = 0.00s, Memory = -32.0K)
Checking Rule SGDC_waive04 (Rule 24 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive05 (Rule 25 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive06 (Rule 26 of total 277) .... done (Time = 0.00s, Memory = -31.1K)
Checking Rule SGDC_waive07 (Rule 27 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive08 (Rule 28 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive09 (Rule 29 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive10 (Rule 30 of total 277) .... done (Time = 0.00s, Memory = -2.9K)
Checking Rule SGDC_waive11 (Rule 31 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive12 (Rule 32 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive13 (Rule 33 of total 277) .... done (Time = 0.00s, Memory = -6.1K)
Checking Rule SGDC_waive21 (Rule 34 of total 277) .... done (Time = 0.00s, Memory = 1.6K)
Checking Rule SGDC_waive22 (Rule 35 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive30 (Rule 36 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive32 (Rule 37 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive33 (Rule 38 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive36 (Rule 39 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive38 (Rule 40 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_fifo01 (Rule 41 of total 277) .... done (Time = 0.00s, Memory = -0.5K)
Checking Rule SGDC_libgroup01 (Rule 42 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_libgroup02 (Rule 43 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_libgroup04 (Rule 44 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule SGDC_power_data01 (Rule 45 of total 277) .... done (Time = 0.00s, Memory = 1.5K)
Checking Rule SGDC_ungroup01 (Rule 46 of total 277) .... done (Time = 0.00s, Memory = 8.3K)
Checking Rule SGDC_abstract_port06 (Rule 47 of total 277) .... done (Time = 0.00s, Memory = 5.0K)
Checking Rule SGDC_abstract_port14 (Rule 48 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule SGDC_abstract_port15 (Rule 49 of total 277) .... done (Time = 0.00s, Memory = 1.4K)
Checking Rule SGDC_abstract_port18 (Rule 50 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule sdc_init_rule (Rule 51 of total 277) .... done (Time = 0.00s, Memory = 0.6K)
Checking Rule CMD_ignorelibs01 (Rule 52 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule ReportRuleNotRun (Rule 53 of total 277) .... done (Time = 0.03s, Memory = -29.3K)
Checking Rule STARC05-2.3.1.2c (Rule 54 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W442a (Rule 55 of total 277) .... done (Time = 0.00s, Memory = -0.3K)
Checking Rule W442b (Rule 56 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W442c (Rule 57 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W442f (Rule 58 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule mixedsenselist (Rule 59 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule badimplicitSM1 (Rule 60 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule badimplicitSM2 (Rule 61 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule badimplicitSM4 (Rule 62 of total 277) .... done (Time = 0.00s, Memory = 3.1K)
Checking Rule bothedges (Rule 63 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule BlockHeader (Rule 64 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
Checking Rule W421 (Rule 65 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.1.6.5 (Rule 66 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule ReportStopSummary (Rule 67 of total 277) .... done (Time = 0.00s, Memory = 1.6K)
Checking Rule ReportIgnoreSummary (Rule 68 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
##SGDEBUG [BENCHMARK_ABSOLUTE]: Analysis started: 8 sec, 687309 KB, 2777788 KB
##SGDEBUG [BENCHMARK_INCR]: Analysis started: 8 sec, 687309 KB, 2777788 KB
 Analyzing source file "../rtl/sync_fifo_64_to_128.v" ....
 Analyzing source file "../rtl/sync_fifo.v" ....
 Analyzing source file "../rtl/wchannel.v" ....
 Analyzing source file "../tb/tb_wchannel.v" ....
 SYNTH_196           -            -            ERROR                         
 SYNTH_106           -            -            ERROR                         
 SYNTH_196           -            -            ERROR                         
 SYNTH_196           -            -            ERROR                         
 SYNTH_106           -            -            ERROR                         
 SYNTH_196           -            -            ERROR                         
##SGDEBUG [BENCHMARK_ABSOLUTE]: Analysis finished: 8 sec, 753198 KB, 2843580 KB
##SGDEBUG [BENCHMARK_INCR]: Analysis finished: 0 sec, 65889 KB, 65792 KB
##SGDEBUG [BENCHMARK_ABSOLUTE]: Elaboration started: 8 sec, 753198 KB, 2843580 KB
##SGDEBUG [BENCHMARK_INCR]: Elaboration started: 0 sec, 0 KB, 0 KB
 Elaborating Top Verilog Design Unit 'tb_wchannel' ..... done
##SGDEBUG [BENCHMARK_ABSOLUTE]: Elaboration finished: 8 sec, 819075 KB, 2909372 KB
##SGDEBUG [BENCHMARK_INCR]: Elaboration finished: 0 sec, 65877 KB, 65792 KB
##SGDEBUG [BENCHMARK_ABSOLUTE]: RTL Semantic Checker started: 8 sec, 819072 KB, 2909372 KB
##SGDEBUG [BENCHMARK_INCR]: RTL Semantic Checker started: 0 sec, -3 KB, 0 KB
##SGDEBUG [BENCHMARK_ABSOLUTE]: RTL Semantic Checker finished: 8 sec, 819072 KB, 2909372 KB
##SGDEBUG [BENCHMARK_INCR]: RTL Semantic Checker finished: 0 sec, 0 KB, 0 KB
Checking Rule ElabSummary (Rule 69 of total 277)##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/elab_summary.rpt' in "w" mode ...
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/elab_summary.rpt' closed.
 .... done (Time = 0.00s, Memory = 8.3K)
Checking Rule ReportCheckDataSummary (Rule 70 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
 Reading waiver file "./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/constraint/spg_autogenerated_waivers.sgdc" ...
 Generating SGDC file "./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/constraint/pragma2Constraint.sgdc" from pragmas in HDL source files ....
 Generating WAIVER file "./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/waiver/pragma2Waiver.swl" from pragmas in HDL source files ....
Checking Rule DetectTopDesignUnits (Rule 71 of total 277) Detected 1 top level design units: 
     tb_wchannel
 .... done (Time = 0.00s, Memory = 0.6K)
Performing semantic checks on SGDC contents
..... SGDC semantic checks completed. (Time = 0.00s, Memory = 52.0K)
Checking Rule SGDC_testmode03 (Rule 72 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PECHECK09 (Rule 73 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Ac_multitop01 (Rule 74 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
Checking Rule ReportObsoletePragmas (Rule 75 of total 277) .... done (Time = 0.00s, Memory = -16.0K)
Checking Rule checkSGDC_01 (Rule 76 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule checkSGDC_03 (Rule 77 of total 277) .... done (Time = 0.00s, Memory = -1.1K)
Checking Rule checkSGDC_08 (Rule 78 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule GenerateConfMap (Rule 79 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
Checking Rule SGDC_memorywritepin04 (Rule 80 of total 277) .... done (Time = 0.00s, Memory = 33.2K)
Checking Rule SGDC_reset02 (Rule 81 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_reset03 (Rule 82 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule SGDC_libgroup03 (Rule 83 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_ungroup02 (Rule 84 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule HdlLibDuCheck (Rule 85 of total 277) .... done (Time = 0.00s, Memory = -0.2K)
Checking Rule RtlDesignInfo (Rule 86 of total 277)
##SGDEBUG [BENCHMARK_DATA]: Number of RTL Design Units = 4
##SGDEBUG: RTL statistics for Verilog design units:
##SGDEBUG[BENCHMARK_DATA]: RTL Ports = 29 487 8
##SGDEBUG[BENCHMARK_DATA]: RTL Insts = 27
##SGDEBUG[BENCHMARK_DATA]: RTL Nets = 44 756 25
##SGDEBUG[BENCHMARK_DATA]: RTL Terms = 77 487 8

##SGDEBUG: NOTE: Following estimated data is applicable for structural designs only.
##SGDEBUG:     In case of RTL designs, this data may differ significantly from the actual figure.
##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Insts = 2
##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Nets = 720
##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Terms = 220
##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Paths = 2
 .... done (Time = 0.00s, Memory = 0.9K)
Checking Rule sim_race02 (Rule 87 of total 277) .... done (Time = 0.00s, Memory = -3.3K)
Checking Rule W339a (Rule 88 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W416 (Rule 89 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule mixedsenselist (Rule 90 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W110a (Rule 91 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Pragma_setupa (Rule 92 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _deltaDelay (Rule 93 of total 277) .... done (Time = 0.00s, Memory = 1.9K)
Checking Rule _deltaDelay (Rule 94 of total 277) .... done (Time = 0.00s, Memory = -1.5K)
Checking Rule preReq_ConsCase2 (Rule 95 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule preReq_ConsCase (Rule 96 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-AlwaysParamSetup (Rule 97 of total 277) .... done (Time = 0.00s, Memory = 8.0K)
Checking Rule STARC05-ProcessParamSetup (Rule 98 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Latch_VePreReqRule (Rule 99 of total 277) .... done (Time = 0.00s, Memory = 9.5K)
Checking Rule CheckCelldefine (Rule 100 of total 277) .... done (Time = 0.00s, Memory = -24.0K)
Checking Rule SGDC_waive23 (Rule 101 of total 277) .... done (Time = 0.00s, Memory = 4.0K)
Checking Rule SGDC_waive26 (Rule 102 of total 277) .... done (Time = 0.00s, Memory = 0.3K)
Checking Rule SGDC_waive27 (Rule 103 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive29 (Rule 104 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Prereqs_RegOutputs (Rule 105 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.1.4.5 (Rule 106 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.3.1.5b (Rule 107 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.3.3.1 (Rule 108 of total 277) .... done (Time = 0.00s, Memory = 1.5K)
Checking Rule STARC05-2.3.3.1 (Rule 109 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.11.3.1 (Rule 110 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Prereqs_STARC05-1.6.2.1 (Rule 111 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Prereqs_STARC-1.6.2.1 (Rule 112 of total 277) .... done (Time = 0.00s, Memory = -5.6K)
Checking Rule STARC05-2.10.1.4a (Rule 113 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W496b (Rule 114 of total 277) .... done (Time = 0.00s, Memory = 3.9K)
Checking Rule W317 (Rule 115 of total 277) .... done (Time = 0.00s, Memory = -8.0K)
Checking Rule W422 (Rule 116 of total 277) .... done (Time = 0.00s, Memory = 0.8K)
Checking Rule W426 (Rule 117 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
Checking Rule W480 (Rule 118 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W481a (Rule 119 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W481b (Rule 120 of total 277) .... done (Time = 0.00s, Memory = -6.0K)
Checking Rule W422 (Rule 121 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W156 (Rule 122 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W292 (Rule 123 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W71 (Rule 124 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W287b (Rule 125 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W293 (Rule 126 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W398 (Rule 127 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W421 (Rule 128 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W424 (Rule 129 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W467 (Rule 130 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Prereqs_RegInputOutputs (Rule 131 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PragmaComments-ML (Rule 132 of total 277)##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/PragmaComments' in "a" mode ...
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/PragmaComments' closed.
 .... done (Time = 0.00s, Memory = 69.2K)
Checking Rule PragmaComments-ML (Rule 133 of total 277) .... done (Time = 0.00s, Memory = -2.0K)
Checking Rule CheckDelayTimescale-ML (Rule 134 of total 277) .... done (Time = 0.00s, Memory = -30.3K)
Checking Rule Prereqs_InclFileSetup-ML (Rule 135 of total 277) .... done (Time = 0.00s, Memory = 7.8K)
Checking ELABDU Rules for designUnit tb_wchannel
    Checking Rule syncRstReq (Rule 136 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule syncRstReq (Rule 137 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule AcOvlRtl (Rule 138 of total 277) .... done (Time = 0.00s, Memory = -0.3K)
    Checking Rule AcOvlRtl (Rule 139 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule Prereqs_STARC-2.3.6.1 (Rule 140 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
    Checking Rule GenTopLevelBlocksForAutoSoc (Rule 141 of total 277)##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/blocks.rpt' in "w" mode ...
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/blocks.rpt' closed.
 .... done (Time = 0.00s, Memory = 3.8K)
    Checking Rule STARC05-2.1.5.3 (Rule 142 of total 277) .... done (Time = 0.00s, Memory = -38.3K)
    Checking Rule STARC05-2.2.3.3 (Rule 143 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.3.1.6 (Rule 144 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.10.2.3 (Rule 145 of total 277) .... done (Time = 0.00s, Memory = -64.0K)
    Checking Rule STARC05-2.10.3.2a (Rule 146 of total 277) .... done (Time = 0.00s, Memory = -0.1K)
    Checking Rule STARC05-2.11.3.1 (Rule 147 of total 277) .... done (Time = 0.00s, Memory = 2.0K)
    Checking Rule STARC05-2.1.3.1 (Rule 148 of total 277) .... done (Time = 0.00s, Memory = 1.0K)
    Checking Rule STARC05-2.10.1.4b (Rule 149 of total 277) .... done (Time = 0.00s, Memory = -4.2K)
    Checking Rule W110 (Rule 150 of total 277) .... done (Time = 0.00s, Memory = 8.0K)
    Checking Rule W122 (Rule 151 of total 277) .... done (Time = 0.00s, Memory = 1.6K)
    Checking Rule W496a (Rule 152 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W19 (Rule 153 of total 277) .... done (Time = 0.00s, Memory = -20.4K)
    Checking Rule W66 (Rule 154 of total 277) .... done (Time = 0.00s, Memory = -9.8K)
    Checking Rule W116 (Rule 155 of total 277) .... done (Time = 0.00s, Memory = 0.4K)
    Checking Rule W123 (Rule 156 of total 277) .... done (Time = 0.00s, Memory = 19.0K)
    Checking Rule W156 (Rule 157 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W215 (Rule 158 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W216 (Rule 159 of total 277) .... done (Time = 0.00s, Memory = -0.5K)
    Checking Rule W218 (Rule 160 of total 277) .... done (Time = 0.00s, Memory = 0.1K)
    Checking Rule W224 (Rule 161 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W263 (Rule 162 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W289 (Rule 163 of total 277) .... done (Time = 0.00s, Memory = -2.6K)
    Checking Rule W337 (Rule 164 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W352 (Rule 165 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W362 (Rule 166 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W415a (Rule 167 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W486 (Rule 168 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W499 (Rule 169 of total 277) .... done (Time = 0.00s, Memory = 3.1K)
    Checking Rule W502 (Rule 170 of total 277) .... done (Time = 0.00s, Memory = 3.8K)
    Checking Rule W116 (Rule 171 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 172 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W123 (Rule 173 of total 277) .... done (Time = 0.00s, Memory = 0.6K)
    Checking Rule W71 (Rule 174 of total 277) .... done (Time = 0.00s, Memory = 27.8K)
    Checking Rule W240 (Rule 175 of total 277) .... done (Time = 0.00s, Memory = 3.1K)
    Checking Rule W240 (Rule 176 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W287a (Rule 177 of total 277) .... done (Time = 0.00s, Memory = 3.9K)
    Checking Rule W293 (Rule 178 of total 277) .... done (Time = 0.00s, Memory = -20.0K)
    Checking Rule W398 (Rule 179 of total 277) .... done (Time = 0.00s, Memory = -9.6K)
    Checking Rule W424 (Rule 180 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W467 (Rule 181 of total 277) .... done (Time = 0.00s, Memory = -0.2K)
    Checking Rule W505 (Rule 182 of total 277) .... done (Time = 0.00s, Memory = 7.5K)
    Checking Rule W505 (Rule 183 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W528 (Rule 184 of total 277) .... done (Time = 0.01s, Memory = 9.3K)
    Checking Rule W528 (Rule 185 of total 277) .... done (Time = 0.00s, Memory = 645.4K)
    Checking Rule Prereqs_Usage (Rule 186 of total 277) .... done (Time = 0.00s, Memory = -16.5K)
    Checking Rule Postreqs_CheckFuncTask (Rule 187 of total 277) .... done (Time = 0.00s, Memory = -24.0K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 188 of total 277) .... done (Time = 0.00s, Memory = -0.6K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 189 of total 277) .... done (Time = 0.00s, Memory = 0.4K)
    Checking Rule ReportPortInfo-ML (Rule 190 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule NoAssignX-ML (Rule 191 of total 277) .... done (Time = 0.00s, Memory = -6.0K)
    Checking Rule ParamWidthMismatch-ML (Rule 192 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule Postreqs_Usage_ML (Rule 193 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule NoXInCase-ML (Rule 194 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking ELABDU Rules for designUnit wchannel
    Checking Rule syncRstReq (Rule 136 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule syncRstReq (Rule 137 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule AcOvlRtl (Rule 138 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule AcOvlRtl (Rule 139 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule Prereqs_STARC-2.3.6.1 (Rule 140 of total 277) .... done (Time = 0.00s, Memory = -3.0K)
    Checking Rule GenTopLevelBlocksForAutoSoc (Rule 141 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.1.5.3 (Rule 142 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.2.3.3 (Rule 143 of total 277) .... done (Time = 0.00s, Memory = 3.6K)
    Checking Rule STARC05-2.3.1.6 (Rule 144 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.10.2.3 (Rule 145 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.10.3.2a (Rule 146 of total 277) .... done (Time = 0.00s, Memory = 23.0K)
    Checking Rule STARC05-2.11.3.1 (Rule 147 of total 277) .... done (Time = 0.01s, Memory = -10.8K)
    Checking Rule STARC05-2.1.3.1 (Rule 148 of total 277) .... done (Time = 0.00s, Memory = -16.3K)
    Checking Rule STARC05-2.10.1.4b (Rule 149 of total 277) .... done (Time = 0.00s, Memory = -9.9K)
    Checking Rule W110 (Rule 150 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 151 of total 277) .... done (Time = 0.00s, Memory = 1.2K)
    Checking Rule W496a (Rule 152 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W19 (Rule 153 of total 277) .... done (Time = 0.00s, Memory = 4.8K)
    Checking Rule W66 (Rule 154 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W116 (Rule 155 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W123 (Rule 156 of total 277) .... done (Time = 0.00s, Memory = 20.1K)
    Checking Rule W156 (Rule 157 of total 277) .... done (Time = 0.00s, Memory = -8.0K)
    Checking Rule W215 (Rule 158 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W216 (Rule 159 of total 277) .... done (Time = 0.00s, Memory = -0.4K)
    Checking Rule W218 (Rule 160 of total 277) .... done (Time = 0.00s, Memory = -30.0K)
    Checking Rule W224 (Rule 161 of total 277) .... done (Time = 0.00s, Memory = 5.1K)
    Checking Rule W263 (Rule 162 of total 277) .... done (Time = 0.00s, Memory = -0.4K)
    Checking Rule W289 (Rule 163 of total 277) .... done (Time = 0.00s, Memory = -9.1K)
    Checking Rule W337 (Rule 164 of total 277) .... done (Time = 0.00s, Memory = -4.2K)
    Checking Rule W352 (Rule 165 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W362 (Rule 166 of total 277) .... done (Time = 0.00s, Memory = 1.8K)
    Checking Rule W415a (Rule 167 of total 277) .... done (Time = 0.00s, Memory = -9.4K)
    Checking Rule W486 (Rule 168 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W499 (Rule 169 of total 277) .... done (Time = 0.00s, Memory = -21.1K)
    Checking Rule W502 (Rule 170 of total 277) .... done (Time = 0.00s, Memory = 4.7K)
    Checking Rule W116 (Rule 171 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 172 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W123 (Rule 173 of total 277) .... done (Time = 0.00s, Memory = 0.6K)
    Checking Rule W71 (Rule 174 of total 277) .... done (Time = 0.00s, Memory = -6.0K)
    Checking Rule W240 (Rule 175 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W240 (Rule 176 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W287a (Rule 177 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W293 (Rule 178 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W398 (Rule 179 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W424 (Rule 180 of total 277) .... done (Time = 0.00s, Memory = 16.0K)
    Checking Rule W467 (Rule 181 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W505 (Rule 182 of total 277) .... done (Time = 0.01s, Memory = 0.0K)
    Checking Rule W505 (Rule 183 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W528 (Rule 184 of total 277) .... done (Time = 0.00s, Memory = -45.5K)
    Checking Rule W528 (Rule 185 of total 277) .... done (Time = 0.00s, Memory = 645.4K)
    Checking Rule Prereqs_Usage (Rule 186 of total 277) .... done (Time = 0.00s, Memory = -13.0K)
    Checking Rule Postreqs_CheckFuncTask (Rule 187 of total 277) .... done (Time = 0.00s, Memory = 3.9K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 188 of total 277) .... done (Time = 0.00s, Memory = 0.8K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 189 of total 277) .... done (Time = 0.00s, Memory = 0.4K)
    Checking Rule ReportPortInfo-ML (Rule 190 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule NoAssignX-ML (Rule 191 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule ParamWidthMismatch-ML (Rule 192 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule Postreqs_Usage_ML (Rule 193 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
    Checking Rule NoXInCase-ML (Rule 194 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking ELABDU Rules for designUnit sync_fifo
    Checking Rule syncRstReq (Rule 136 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule syncRstReq (Rule 137 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule AcOvlRtl (Rule 138 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule AcOvlRtl (Rule 139 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule Prereqs_STARC-2.3.6.1 (Rule 140 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule GenTopLevelBlocksForAutoSoc (Rule 141 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
    Checking Rule STARC05-2.1.5.3 (Rule 142 of total 277) .... done (Time = 0.00s, Memory = 0.3K)
    Checking Rule STARC05-2.2.3.3 (Rule 143 of total 277) .... done (Time = 0.00s, Memory = -0.2K)
    Checking Rule STARC05-2.3.1.6 (Rule 144 of total 277) .... done (Time = 0.00s, Memory = -0.3K)
    Checking Rule STARC05-2.10.2.3 (Rule 145 of total 277) .... done (Time = 0.00s, Memory = -0.4K)
    Checking Rule STARC05-2.10.3.2a (Rule 146 of total 277) .... done (Time = 0.00s, Memory = -32.0K)
    Checking Rule STARC05-2.11.3.1 (Rule 147 of total 277) .... done (Time = 0.00s, Memory = -1.1K)
    Checking Rule STARC05-2.1.3.1 (Rule 148 of total 277) .... done (Time = 0.00s, Memory = 2.0K)
    Checking Rule STARC05-2.10.1.4b (Rule 149 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W110 (Rule 150 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 151 of total 277) .... done (Time = 0.00s, Memory = -0.8K)
    Checking Rule W496a (Rule 152 of total 277) .... done (Time = 0.00s, Memory = 34.8K)
    Checking Rule W19 (Rule 153 of total 277) .... done (Time = 0.00s, Memory = -8.0K)
    Checking Rule W66 (Rule 154 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W116 (Rule 155 of total 277) .... done (Time = 0.00s, Memory = -3.5K)
    Checking Rule W123 (Rule 156 of total 277) .... done (Time = 0.00s, Memory = -5.1K)
    Checking Rule W156 (Rule 157 of total 277) .... done (Time = 0.00s, Memory = -4.5K)
    Checking Rule W215 (Rule 158 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W216 (Rule 159 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W218 (Rule 160 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W224 (Rule 161 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W263 (Rule 162 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W289 (Rule 163 of total 277) .... done (Time = 0.00s, Memory = -4.0K)
    Checking Rule W337 (Rule 164 of total 277) .... done (Time = 0.00s, Memory = 8.0K)
    Checking Rule W352 (Rule 165 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W362 (Rule 166 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W415a (Rule 167 of total 277) .... done (Time = 0.00s, Memory = -3.5K)
    Checking Rule W486 (Rule 168 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W499 (Rule 169 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W502 (Rule 170 of total 277) .... done (Time = 0.00s, Memory = -0.2K)
    Checking Rule W116 (Rule 171 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 172 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W123 (Rule 173 of total 277) .... done (Time = 0.00s, Memory = 0.6K)
    Checking Rule W71 (Rule 174 of total 277) .... done (Time = 0.00s, Memory = -3.7K)
    Checking Rule W240 (Rule 175 of total 277) .... done (Time = 0.01s, Memory = 0.9K)
    Checking Rule W240 (Rule 176 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W287a (Rule 177 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W293 (Rule 178 of total 277) .... done (Time = 0.00s, Memory = -6.4K)
    Checking Rule W398 (Rule 179 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W424 (Rule 180 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
    Checking Rule W467 (Rule 181 of total 277) .... done (Time = 0.00s, Memory = 3.9K)
    Checking Rule W505 (Rule 182 of total 277) .... done (Time = 0.00s, Memory = 5.6K)
    Checking Rule W505 (Rule 183 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W528 (Rule 184 of total 277) .... done (Time = 0.00s, Memory = -15.3K)
    Checking Rule W528 (Rule 185 of total 277) .... done (Time = 0.00s, Memory = 645.4K)
    Checking Rule Prereqs_Usage (Rule 186 of total 277) .... done (Time = 0.00s, Memory = -12.0K)
    Checking Rule Postreqs_CheckFuncTask (Rule 187 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 188 of total 277) .... done (Time = 0.00s, Memory = -2.1K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 189 of total 277) .... done (Time = 0.00s, Memory = 0.4K)
    Checking Rule ReportPortInfo-ML (Rule 190 of total 277) .... done (Time = 0.00s, Memory = 3.5K)
    Checking Rule NoAssignX-ML (Rule 191 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule ParamWidthMismatch-ML (Rule 192 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule Postreqs_Usage_ML (Rule 193 of total 277) .... done (Time = 0.00s, Memory = -23.2K)
    Checking Rule NoXInCase-ML (Rule 194 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking ELABDU Rules for designUnit sync_fifo_64_to_128
    Checking Rule syncRstReq (Rule 136 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule syncRstReq (Rule 137 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule AcOvlRtl (Rule 138 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule AcOvlRtl (Rule 139 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule Prereqs_STARC-2.3.6.1 (Rule 140 of total 277) .... done (Time = 0.00s, Memory = 24.0K)
    Checking Rule GenTopLevelBlocksForAutoSoc (Rule 141 of total 277) .... done (Time = 0.00s, Memory = -0.9K)
    Checking Rule STARC05-2.1.5.3 (Rule 142 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.2.3.3 (Rule 143 of total 277) .... done (Time = 0.00s, Memory = -49.5K)
    Checking Rule STARC05-2.3.1.6 (Rule 144 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.10.2.3 (Rule 145 of total 277) .... done (Time = 0.00s, Memory = -1.5K)
    Checking Rule STARC05-2.10.3.2a (Rule 146 of total 277) .... done (Time = 0.00s, Memory = -4.7K)
    Checking Rule STARC05-2.11.3.1 (Rule 147 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.1.3.1 (Rule 148 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule STARC05-2.10.1.4b (Rule 149 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W110 (Rule 150 of total 277) .... done (Time = 0.00s, Memory = 32.0K)
    Checking Rule W122 (Rule 151 of total 277) .... done (Time = 0.00s, Memory = -18.2K)
    Checking Rule W496a (Rule 152 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W19 (Rule 153 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W66 (Rule 154 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W116 (Rule 155 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W123 (Rule 156 of total 277) .... done (Time = 0.00s, Memory = 14.2K)
    Checking Rule W156 (Rule 157 of total 277) .... done (Time = 0.00s, Memory = -0.0K)
    Checking Rule W215 (Rule 158 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W216 (Rule 159 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W218 (Rule 160 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W224 (Rule 161 of total 277) .... done (Time = 0.00s, Memory = -3.2K)
    Checking Rule W263 (Rule 162 of total 277) .... done (Time = 0.00s, Memory = 23.7K)
    Checking Rule W289 (Rule 163 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W337 (Rule 164 of total 277) .... done (Time = 0.00s, Memory = -8.0K)
    Checking Rule W352 (Rule 165 of total 277) .... done (Time = 0.00s, Memory = -8.0K)
    Checking Rule W362 (Rule 166 of total 277) .... done (Time = 0.00s, Memory = -58.0K)
    Checking Rule W415a (Rule 167 of total 277) .... done (Time = 0.00s, Memory = -1.4K)
    Checking Rule W486 (Rule 168 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W499 (Rule 169 of total 277) .... done (Time = 0.00s, Memory = 3.9K)
    Checking Rule W502 (Rule 170 of total 277) .... done (Time = 0.00s, Memory = 2.1K)
    Checking Rule W116 (Rule 171 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W122 (Rule 172 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W123 (Rule 173 of total 277) .... done (Time = 0.00s, Memory = 0.6K)
    Checking Rule W71 (Rule 174 of total 277) .... done (Time = 0.00s, Memory = -0.2K)
    Checking Rule W240 (Rule 175 of total 277) .... done (Time = 0.00s, Memory = -0.5K)
    Checking Rule W240 (Rule 176 of total 277) .... done (Time = 0.00s, Memory = 0.2K)
    Checking Rule W287a (Rule 177 of total 277) .... done (Time = 0.00s, Memory = 16.0K)
    Checking Rule W293 (Rule 178 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W398 (Rule 179 of total 277) .... done (Time = 0.00s, Memory = 4.0K)
    Checking Rule W424 (Rule 180 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W467 (Rule 181 of total 277) .... done (Time = 0.00s, Memory = -0.7K)
    Checking Rule W505 (Rule 182 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W505 (Rule 183 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W528 (Rule 184 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule W528 (Rule 185 of total 277) .... done (Time = 0.00s, Memory = 645.4K)
    Checking Rule Prereqs_Usage (Rule 186 of total 277) .... done (Time = 0.00s, Memory = -16.0K)
    Checking Rule Postreqs_CheckFuncTask (Rule 187 of total 277) .... done (Time = 0.00s, Memory = 15.5K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 188 of total 277) .... done (Time = 0.00s, Memory = -45.0K)
    Checking Rule Prereqs_ConstantInput-ML (Rule 189 of total 277) .... done (Time = 0.00s, Memory = 0.4K)
    Checking Rule ReportPortInfo-ML (Rule 190 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule NoAssignX-ML (Rule 191 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule ParamWidthMismatch-ML (Rule 192 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule Postreqs_Usage_ML (Rule 193 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
    Checking Rule NoXInCase-ML (Rule 194 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_meta_design_hier01 (Rule 195 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
##SGDEBUG [BENCHMARK_ABSOLUTE]: Synthesis started: 9 sec, 821141 KB, 2911684 KB
##SGDEBUG [BENCHMARK_INCR]: Synthesis started: 1 sec, 2069 KB, 2312 KB
 Synthesizing module: sync_fifo_64_to_128 (elaborated name: sync_fifo_64_to_128) ... (Module 1 of total 3)  done 
     (Memory Used = -135409.7K(incr), 755671.1K(tot), Cpu Time = 0.11s(incr))
 Synthesizing module: sync_fifo (elaborated name: sync_fifo) ... (Module 2 of total 3)  done 
     (Memory Used = 63.4K(incr), 755764.6K(tot), Cpu Time = 0.03s(incr))
 Synthesizing module: wchannel (elaborated name: wchannel) ... (Module 3 of total 3)  done 
     (Memory Used = 17.3K(incr), 755782.2K(tot), Cpu Time = 0.02s(incr))
 Skipping Synthesis for unsynthesizable module: tb_wchannel 
 Synthesis completed.
 1 module(s) not compiled. (Please see ErrorAnalyzeBBox and InfoAnalyzeBBBox message(s)) 
(You can also see './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/unsynth_modules.rpt' report for details)
##SGDEBUG [BENCHMARK_ABSOLUTE]: Synthesis completed: 9 sec, 756016 KB, 2851268 KB
##SGDEBUG [BENCHMARK_INCR]: Synthesis completed: 0 sec, -65125 KB, -60416 KB
Checking Rule InferBlackBox (Rule 196 of total 277) .... done (Time = 0.01s, Memory = -30.2K)
##SGDEBUG [BENCHMARK_DATA]: Number of NOM Modules = 3
##SGDEBUG [BENCHMARK_DATA]: Number of NOM Instances = 1747
##SGDEBUG [BENCHMARK_DATA]: Number of NOM Nets = 2220
##SGDEBUG [BENCHMARK_DATA]: Number of NOM Terminals = 9068
##SGDEBUG [BENCHMARK_DATA]: Number of NOM Instances per Module (max and avg) = 951, 582
##SGDEBUG [BENCHMARK_ABSOLUTE]: Saving NOM started: 9 sec, 755983 KB, 2851268 KB
##SGDEBUG [BENCHMARK_INCR]: Saving NOM started: 0 sec, -33 KB, 0 KB

INFO [234]    Saving design database in directory './spyglass-1/tb_wchannel/.SG_SaveRestoreDB/autogenerated__default_snapshot' ...
              done

##SGDEBUG [BENCHMARK_ABSOLUTE]: Saving NOM completed: 10 sec, 805342 KB, 2902216 KB
##SGDEBUG [BENCHMARK_INCR]: Saving NOM completed: 1 sec, 49359 KB, 50948 KB
     (Memory Used = 49310.4K(incr), 805293.7K(tot), Cpu Time = 0.03s(incr))
Checking Rule SGDC_waive37 (Rule 197 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive24 (Rule 198 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive25 (Rule 199 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive31 (Rule 200 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_waive35 (Rule 201 of total 277) .... done (Time = 0.00s, Memory = 1.0K)
Checking Rule Txv_SvaSetup01 for module sync_fifo_64_to_128 (Rule 202 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PESVASETUP01 for module sync_fifo_64_to_128 (Rule 203 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _cdc_save_license01 for module sync_fifo_64_to_128 (Rule 204 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Reset_check05 for module sync_fifo_64_to_128 (Rule 205 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _syncResetStyleRTL for module sync_fifo_64_to_128 (Rule 206 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _meta_delay01 for module sync_fifo_64_to_128 (Rule 207 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Ac_svasetup01 for module sync_fifo_64_to_128 (Rule 208 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule LogNMuxPrereq for module sync_fifo_64_to_128 (Rule 209 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC-1.3.2.2_prereq for module sync_fifo_64_to_128 (Rule 210 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W336 for module sync_fifo_64_to_128 (Rule 211 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W414 for module sync_fifo_64_to_128 (Rule 212 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W450L for module sync_fifo_64_to_128 (Rule 213 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule HangingNetPreReq-ML for module sync_fifo_64_to_128 (Rule 214 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule RegInputOutput-ML for module sync_fifo_64_to_128 (Rule 215 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.7 for module sync_fifo_64_to_128 (Rule 216 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.9 for module sync_fifo_64_to_128 (Rule 217 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Txv_SvaSetup01 for module sync_fifo (Rule 202 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PESVASETUP01 for module sync_fifo (Rule 203 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _cdc_save_license01 for module sync_fifo (Rule 204 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Reset_check05 for module sync_fifo (Rule 205 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _syncResetStyleRTL for module sync_fifo (Rule 206 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _meta_delay01 for module sync_fifo (Rule 207 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Ac_svasetup01 for module sync_fifo (Rule 208 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule LogNMuxPrereq for module sync_fifo (Rule 209 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC-1.3.2.2_prereq for module sync_fifo (Rule 210 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W336 for module sync_fifo (Rule 211 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W414 for module sync_fifo (Rule 212 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W450L for module sync_fifo (Rule 213 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule HangingNetPreReq-ML for module sync_fifo (Rule 214 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule RegInputOutput-ML for module sync_fifo (Rule 215 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.7 for module sync_fifo (Rule 216 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.9 for module sync_fifo (Rule 217 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Txv_SvaSetup01 for module wchannel (Rule 202 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule PESVASETUP01 for module wchannel (Rule 203 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _cdc_save_license01 for module wchannel (Rule 204 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Reset_check05 for module wchannel (Rule 205 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _syncResetStyleRTL for module wchannel (Rule 206 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _meta_delay01 for module wchannel (Rule 207 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule Ac_svasetup01 for module wchannel (Rule 208 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule LogNMuxPrereq for module wchannel (Rule 209 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC-1.3.2.2_prereq for module wchannel (Rule 210 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W336 for module wchannel (Rule 211 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W414 for module wchannel (Rule 212 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule W450L for module wchannel (Rule 213 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule HangingNetPreReq-ML for module wchannel (Rule 214 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule RegInputOutput-ML for module wchannel (Rule 215 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.7 for module wchannel (Rule 216 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule STARC05-2.5.1.9 for module wchannel (Rule 217 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Performing semantic checks on SGDC contents
..... SGDC semantic checks completed. (Time = 0.00s, Memory = -97.5K)
Checking Rule SGDC_testmode03 (Rule 72 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule _abstractPortSGDC (Rule 218 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port03 (Rule 219 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port04 (Rule 220 of total 277) .... done (Time = 0.00s, Memory = -34.0K)
Checking Rule SGDC_abstract_port05 (Rule 221 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port07 (Rule 222 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port08 (Rule 223 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port10 (Rule 224 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port11 (Rule 225 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port12 (Rule 226 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port13 (Rule 227 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule ReportUngroup (Rule 228 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule LINT_portReten (Rule 229 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule SGDC_abstract_port21 (Rule 230 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
Checking Rule InferLatch (Rule 231 of total 277) .... done (Time = 0.00s, Memory = 28.0K)
Checking Rule UndrivenInTerm-ML (Rule 232 of total 277) .... done (Time = 0.00s, Memory = 0.0K)
##SGDEBUG [BENCHMARK_ABSOLUTE]: VS rule checking finished...: 10 sec, 762224 KB, 2856656 KB
##SGDEBUG [BENCHMARK_INCR]: VS rule checking finished...: 0 sec, -43118 KB, -45560 KB
##SGDEBUG [BENCHMARK_ABSOLUTE]: Elab View Deletion Finished: 10 sec, 696275 KB, 2790864 KB
##SGDEBUG [BENCHMARK_INCR]: Elab View Deletion Finished: 0 sec, -65949 KB, -65792 KB
##SGDEBUG [BENCHMARK_ABSOLUTE]: After deleting RTL view: 10 sec, 628487 KB, 2723536 KB
##SGDEBUG [BENCHMARK_INCR]: After deleting RTL view: 0 sec, -67788 KB, -67328 KB
Checking Rule AnalyzeBBox (Rule 233 of total 277) .... done (Time = 0.00s, Memory = -90.0K)
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/openmore/CombLoopReport.rpt' closed.
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/lint/SignalUsageReport.rpt' closed.
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/RegInputOutput' closed.
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/morelint/ReportPortInfo' closed.
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/morelint/ReportPortInfo.csv' closed.
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch/morelint/ReportPorts' closed.
Checking Rule ReportCheckDataSummary (Rule 70 of total 277) .... done (Time = 0.00s, Memory = 0.0K)

Applying user specified and internally generated waivers on violation database .... done (Time = 0.05s)
##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/unsynth_modules.rpt' in "w" mode ...
##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/unsynth_modules.rpt' closed.

Generating data for Console...
##SGDEBUG [PEAK_MEMORY]: 2911684 KB for entire run at 'W415a' stage
##SGDEBUG [VMPEAK_MEMORY]: 3048636 KB for entire run
##SGDEBUG [BENCHMARK_ABSOLUTE]: Rule checking finished: 10 sec, 625405 KB, 2724252 KB
##SGDEBUG [BENCHMARK_INCR]: Rule checking finished: 0 sec, -3082 KB, 716 KB


=====================================================================================
							Rule Parameter Table
=====================================================================================

	PARAMETER-NAME                                     VALUE
-------------------------------------------------------------------------------------
	-allow_clk_in_condition                            no
	-allow_clock_on_output_port                        no
	-allow_combo_logic_base                            no
	-allviol                                           no
	-assume_driver_load                                yes
	-buf_count                                         -1
	-checkInHierarchy                                  yes
	-checkOperatorOverload                             yes
	-checkRTLCInst                                     yes
	-check_bbox_driver                                 no
	-check_clock_cell                                  0
	-check_clock_group_violations                      no
	-check_complete_design                             no
	-check_default_value                               yes
	-check_genvar                                      no
	-check_implicit_senselist                          no
	-check_initialization_assignment                   no
	-check_latch                                       no
	-check_pad_concat                                  no
	-check_sequential                                  no
	-check_shifted_only                                no
	-check_shifted_width                               no
	-check_sign_extend                                 no
	-check_static_value                                no
	-check_temporary_flop                              no
	-check_xassign_casedefault                         no
	-checkblocking                                     no
	-checkconstassign                                  yes
	-checkfullbus                                      yes
	-checkfullrecord                                   yes
	-checknonblocking                                  no
	-checksyncreset                                    yes
	-chkTopModule                                      yes
	-clk_EnableLatch                                   yes
	-debug_proc                                        no
	-depth_ml                                          -1
	-disable_rtl_deadcode                              no
	-do_not_run_W71                                    no
	-dump_array_bits                                   no
	-effort_level                                      100
	-enableE2Q                                         yes
	-fast                                              no
	-force_genclk_for_txv                              no
	-handle_greybox                                    yes
	-handle_hier_clock_reset                           no
	-handle_large_bus                                  no
	-handle_latch_setreset                             no
	-handle_shift_op                                   no
	-ignoreCellName                                    UNDEFINED
	-ignoreModuleInstance                              yes
	-ignoreRtlBuffer                                   no
	-ignoreSRlatch                                     no
	-ignoreSeqProcess                                  no
	-ignore_bitwiseor_assignment                       no
	-ignore_cell                                       0
	-ignore_fsm_counter                                no
	-ignore_hanging_flop                               no
	-ignore_inout                                      no
	-ignore_iopad                                      no
	-ignore_multi_assign_in_forloop                    no
	-ignore_nonBlockCondition                          no
	-ignore_sync_reset                                 no
	-ignore_unloaded_inst                              no
	-ignore_unloaded_port                              no
	-inv_count                                         1
	-library_gen_clock_naming                          yes
	-lp_ignore_SGDC_rules                              UNDEFINED
	-lp_instr_disable_isolation                        UNDEFINED
	-lp_instr_disable_level_shift                      UNDEFINED
	-lp_instr_disable_retention                        UNDEFINED
	-netlist_clock_polarity                            yes
	-new_flow_width                                    yes
	-nocheckoverflow                                   yes
	-not_used_signal                                   nil
	-overlappingLatchLoops                             yes
	-overlappingLoops                                  yes
	-pe_calibration_data_dir                           UNDEFINED
	-pe_ignore_SGDC_rules                              UNDEFINED
	-pe_use_calibration_data                           UNDEFINED
	-populate_comboelements_for_minmax_in_fromto       no
	-pragma_list_ml                                    synopsys
	-preserve_path                                     no
	-pt                                                yes
	-reportHangingLatch                                no
	-reportLibLatch                                    no
	-report_all_messages                               no
	-report_all_rst                                    no
	-report_allclk                                     no
	-report_blackbox_inst                              no
	-report_floating_source                            no
	-report_flop_clock_loop                            no
	-report_flop_reset_loop                            no
	-report_inferred_cell                              yes
	-report_module_configuration                       no
	-report_mux_select                                 yes
	-reportalwayslatch                                 no
	-reportconstassign                                 no
	-reportsimilarassgn                                no
	-reset_synchronizer_modname                        sgdummy1,sgdummy2
	-show_all_sdc_violations                           no
	-show_sdc_progress                                 no
	-sign_extend_func_names                            EXTEND
	-simplesense                                       no
	-skip_lib_cell_checking                            no
	-strict                                            W342,W343
	-supplyHigh                                        __null__
	-supplyLow                                         __null__
	-suppress_sdc_violation_in_abstract                no
	-tc_disable_caching                                no
	-tc_stop_parsing_ignored_commands                  no
	-traverse_function                                 no
	-treat_latch_as_combinational                      yes
	-truncate_through                                  yes
	-use_carry_bit                                     no
	-use_lrm_width                                     no
	-waiver_compat                                     no
	-write_sdc                                         no
=====================================================================================



=====================================================================================
                               Rule Status Table

 RULE-NAME                      POLICY-NAME     ENABLED VIOL-CNT RULE-TYPE   ERROR-MSG         
=====================================================================================
 Setup_CGC                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_setOvlDataInSynthesis       clock-reset     No             - ELABDU         -               
 Setup_req01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer10      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer08      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer07      clock-reset     No             - SETUP          -               
 SGDC_reset_synchronizer06      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer05      clock-reset     No             - SETUP          -               
 SGDC_reset_synchronizer04      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer03      clock-reset     No             - SETUP          -               
 SGDC_reset_synchronizer02      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_synchronizer01      clock-reset     No             - SETUP          -               
 Clock_exit01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_check02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_check01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_license01                   clock-reset     No             - SETUP          -               
 Ac_punsync01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_psync01                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_psetup01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_psync_init                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_upfsetup01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_upfsetup02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_blksgdc01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_quasi_static_validation03 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_quasi_static_validation02 clock-reset     No             - SETUP          -               
 SGDC_quasi_static_validation01 clock-reset     No             - SETUP          -               
 SGDC_define_reset_order_validation02 clock-reset     No             - SETUP          -               
 SGDC_define_reset_order_validation01 clock-reset     No             - SETUP          -               
 SGDC_cdc_false_path_validation01 clock-reset     No             - SETUP          -               
 SGDC_qualifier_validation02    clock-reset     No             - SETUP          -               
 SGDC_qualifier_validation01    clock-reset     No             - SETUP          -               
 SGDC_abstract_port_validation04 clock-reset     No             - SETUP          -               
 SGDC_abstract_port_validation03 clock-reset     No             - SETUP          -               
 SGDC_abstract_port_validation02 clock-reset     No             - SETUP          -               
 SGDC_abstract_port_validation01 clock-reset     No             - SETUP          -               
 SGDC_output_validation02       clock-reset     No             - SETUP          -               
 SGDC_output_validation01       clock-reset     No             - SETUP          -               
 SGDC_num_flops_validation02    clock-reset     No             - SETUP          -               
 SGDC_num_flops_validation01    clock-reset     No             - SETUP          -               
 SGDC_input_validation02        clock-reset     No             - SETUP          -               
 SGDC_input_validation01        clock-reset     No             - SETUP          -               
 SGDC_reset_validation04        clock-reset     No             - SETUP          -               
 SGDC_reset_validation03        clock-reset     No             - SETUP          -               
 SGDC_reset_validation02        clock-reset     No             - SETUP          -               
 SGDC_reset_validation01        clock-reset     No             - SETUP          -               
 SGDC_set_case_analysis_validation03 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_set_case_analysis_validation02 clock-reset     No             - SETUP          -               
 SGDC_set_case_analysis_validation01 clock-reset     No             - SETUP          -               
 SGDC_clock_domain_validation02 clock-reset     No             - SETUP          -               
 SGDC_clock_domain_validation01 clock-reset     No             - SETUP          -               
 SGDC_clock_validation02        clock-reset     No             - SETUP          -               
 SGDC_clock_validation01        clock-reset     No             - SETUP          -               
 SGDC_abstract_mapping01        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_abstract_validation02       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_abstract_validation01       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 top_vs_block_val_prereq        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_resetvalue01                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 AllowComboLogicSetup           clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_xclock01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_glitch02                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_glitch01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_report01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_clockperiod03               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_clockperiod02               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_clockperiod01               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_glitch03                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_abs01                       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_meta01                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_meta_monitor_attributes01 clock-reset     No             - SETUP          -               
 Ac_datahold01a                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_fifo01                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_handshake02                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_handshake01                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_glitch02          (Verilog) clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_cdc_define_transition01   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_cdc08                       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_cdc01c                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_cdc01b                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_cdc01a                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv05                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv04                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv03                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv01                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv02setup01               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_conv02                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync03b                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync03a                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_initstate01                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _glitch_init                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sanity07                    clock-reset     No             - SETUP          -               
 Ac_sanity06                    clock-reset     No             - SETUP          -               
 Ac_sanity05          (VHDL   ) clock-reset     No             - RTLDU          -               
 Ac_sanity05          (Verilog) clock-reset     No             - RTLDU          -               
 Ac_sanity04                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sanity03                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sanity02                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sanity01                    clock-reset     No             - SETUP          -               
 _ac_Auxi01                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_init01                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_initseq01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 PortTimeDelay        (VHDL   ) clock-reset     No             - RTLDULIST      -               
 SGDC_noclockcell_start01       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 NoClockCell                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_converge01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_converge01               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 DeltaDelay02                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 DeltaDelay01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _deltaDelayNom                 clock-reset     No             - VSDULIST       -               
 Clock_delay02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_delay01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check08                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_repeater01                clock-reset     No             - SETUP          -               
 Ac_repeater01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check10                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check06b                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check06a                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_overlap01                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check07                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_clockreset01             clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Param_clockreset06             clock-reset     No             - SETUP          -               
 Param_clockreset05             clock-reset     No             - SETUP          -               
 Param_clockreset04             clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Param_clockreset02             clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_clockreset02              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_Reset_check01            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_sync03                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_sync02                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_sync01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_syncrstrtl01                clock-reset     No             - SETUP          -               
 Ar_syncrstpragma01             clock-reset     No             - SETUP          -               
 Ar_syncrstactive01             clock-reset     No             - SETUP          -               
 Ar_syncrstcombo01              clock-reset     No             - SETUP          -               
 Ar_syncrstload02               clock-reset     No             - SETUP          -               
 Ar_syncrstload01               clock-reset     No             - SETUP          -               
 Reset_check04                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check07                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check10                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info15                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _constrCoverage                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_sync_init                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_syncdeassert01              clock-reset     No             - SETUP          -               
 Ar_asyncdeassert01             clock-reset     No             - SETUP          -               
 Ar_sync01                      clock-reset     No             - SETUP          -               
 Ar_unsync01                    clock-reset     No             - SETUP          -               
 Reset_sync04                   clock-reset     No             - SETUP          -               
 Reset_check12                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_glitch01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check06                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _clock_hier_rules              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_hier03                   clock-reset     No             - SETUP          -               
 Clock_hier02                   clock-reset     No             - SETUP          -               
 Clock_hier01                   clock-reset     No             - SETUP          -               
 SGDC_clock_path_wrapper_module01 clock-reset     No             - SETUP          -               
 _clkWrapModules                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check04                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check03                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_Reset_check03            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_Reset_check02            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check01        (Verilog) clock-reset     No             - VSDU           -               
 Reset_check03                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_Reset_info01             clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check05                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_glitch05                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_glitch04                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_glitch03                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_glitch02                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_glitch01                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info17                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info07                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info06                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info05c                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info05b                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info05a                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info16                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info05                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_syncrstTree                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_info02                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info02                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync09                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync08a                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync08                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync06                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync05                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info14                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_abstract01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_info09b                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_info09a                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_resetcross_matrix01         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_resetcross01                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_rdc01                    clock-reset     No             - SETUP          -               
 Ac_resetcross01                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check11                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check09                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_check02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_library01                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_blackbox01               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_port01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info18                   clock-reset     No             - SETUP          -               
 _reset_sync                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_converge02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Propagate_Resets               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_check01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_info01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_crossing01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_cross_analysis01            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sync02                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_cross_analysis              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_sync01                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_glitch04                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_unsync02                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_unsync01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_coherency06                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_Cross_Init                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _propagate_cdcAttrib           clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_Sync_Init                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _debugData                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Gen_diff01                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info03c                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info03b                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info03a                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_cdc01                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 CDCSet_License01               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_fifo14                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_fifo13                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_fifo12                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_fifo11                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _sync_qualifier                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_sync02p                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _synci                         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _sync_and                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _sync_gp                       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _sync_clock                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncg                         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncd                         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncdw                        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncUDfifo                    clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncfifo                      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _fifo01                        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 FalsePathSetup                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _resetPathCross                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncb                         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncc                         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_cdc_false_path08          clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_cdc_false_path07          clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_cdc_false_path06          clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_cdc_false_path05          clock-reset     No             - SETUP          -               
 SGDC_cdc_false_path04          clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_virtualclock_validation01 clock-reset     No             - SETUP          -               
 _syncreset_prop                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Propagate_Clocks               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_generated_clock06         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Reset_prop                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_prop                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clockmatrix01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ar_syncrst_setupcheck01        clock-reset     No             - SETUP          -               
 Setup_clock02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Setup_clock01                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_info01                   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Pragma_setupb                  clock-reset     No             - RTLDULIST      -               
 Clock_setup02                  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _abstract_port                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Clock_setup01                  clock-reset     No             - SETUP          -               
 Param_clockreset07             clock-reset     No             - SETUP          -               
 SGDC_define_reset_order05      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_define_reset_order04      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_define_reset_order03      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_define_reset_order02      clock-reset     No             - SETUP          -               
 SGDC_reset_filter_path07c      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path07b      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path07a      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path06a      clock-reset     No             - SETUP          -               
 SGDC_reset_filter_path05a      clock-reset     No             - SETUP          -               
 SGDC_reset_filter_path04b      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path04a      clock-reset     No             - SETUP          -               
 SGDC_reset_filter_path03c      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path03b      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path03a      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path02c      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path02b      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path02a      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_reset_filter_path01       clock-reset     No             - SETUP          -               
 RFPSetup                       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _repeaterCellInst              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _syncCellDelayedQualifier      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _rstSyncCellInst               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _ipblock                       clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 _allowInst                     clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 Ac_topology01                  clock-reset     No             - VSTOPDU        -               
 _portReten                     clock-reset     No             - VSTOPDU        -               
 _portRetenClocknReset          clock-reset     No             - VSTOPDU        -               
 SGDC_abstract_port20           clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_abstract_port19           clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_virtualreset01            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_virtualclock01            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_allow_combo_logic02       clock-reset     No             - VSTOPDU        -               
 SGDC_allow_combo_logic01       clock-reset     No             - SETUP          -               
 SGDC_qualifier25               clock-reset     No             - SETUP          -               
 SGDC_qualifier24               clock-reset     No             - SETUP          -               
 SGDC_qualifier23               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier22               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier21               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier20b              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier20a              clock-reset     No             - SETUP          -               
 SGDC_qualifier19c              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier19b              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier19a              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier18               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier17               clock-reset     No             - SETUP          -               
 SGDC_qualifier16               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier15               clock-reset     No             - SETUP          -               
 SGDC_qualifier14               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier13               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier12               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier11               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier10               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier09               clock-reset     No             - SETUP          -               
 SGDC_validation_filter_path03  clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_validation_filter_path02  clock-reset     No             - SETUP          -               
 SGDC_validation_filter_path01  clock-reset     No             - SETUP          -               
 SGDC_cdc_waive03               clock-reset     No             - SETUP          -               
 SGDC_cdc_waive02               clock-reset     No             - SETUP          -               
 SGDC_cdc_waive01               clock-reset     No             - SETUP          -               
 SignalTypeSetup                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 ResetSynchronizerSetup         clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 QualifierSetup                 clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier08               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier06               clock-reset     No             - SETUP          -               
 SGDC_qualifier05               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier04               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier03d              clock-reset     No             - SETUP          -               
 SGDC_qualifier03c              clock-reset     No             - RTLDULIST      -               
 SGDC_qualifier03b              clock-reset     No             - RTLDULIST      -               
 SGDC_qualifier03a              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier02c              clock-reset     No             - RTLDULIST      -               
 SGDC_qualifier02b              clock-reset     No             - RTLDULIST      -               
 SGDC_qualifier02a              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_qualifier01               clock-reset     No             - SETUP          -               
 SGDC_sync_cell11               clock-reset     No             - RTLDULIST      -               
 SyncCellSetup                  clock-reset     No             - SETUP          -               
 SGDC_sync_cell10               clock-reset     No             - SETUP          -               
 SGDC_sync_cell09b              clock-reset     No             - SETUP          -               
 SGDC_sync_cell09a              clock-reset     No             - SETUP          -               
 SGDC_sync_cell08b              clock-reset     No             - SETUP          -               
 SGDC_sync_cell08a              clock-reset     No             - SETUP          -               
 SGDC_sync_cell07               clock-reset     No             - SETUP          -               
 SGDC_sync_cell06               clock-reset     No             - SETUP          -               
 SGDC_sync_cell05               clock-reset     No             - SETUP          -               
 SGDC_sync_cell04               clock-reset     No             - SETUP          -               
 SGDC_sync_cell03b              clock-reset     No             - SETUP          -               
 SGDC_sync_cell03a              clock-reset     No             - SETUP          -               
 SGDC_sync_cell02d              clock-reset     No             - SETUP          -               
 SGDC_sync_cell02c              clock-reset     No             - SETUP          -               
 SGDC_sync_cell02b              clock-reset     No             - VSTOPDU        -               
 SGDC_sync_cell02a              clock-reset     No             - SETUP          -               
 SGDC_gray_signals03            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_gray_signals02            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_gray_signals01            clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 CheckClockRelationSetup        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation05b   clock-reset     No             - SETUP          -               
 SGDC_check_clock_relation05a   clock-reset     No             - SETUP          -               
 SGDC_check_clock_relation04b   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation04a   clock-reset     No             - SETUP          -               
 SGDC_check_clock_relation03b   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation03a   clock-reset     No             - SETUP          -               
 SGDC_check_clock_relation02c   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation02b   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation02a   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation01c   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation01b   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_check_clock_relation01a   clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_sgclkgroup03              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_sgclkgroup02              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_sgclkgroup01              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_clocksense04              clock-reset     No             - SETUP          -               
 SGDC_clocksense03              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_clocksense02              clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_clocksense01              clock-reset     No             - SETUP          -               
 SGDC_numflops14                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops13                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops12                clock-reset     No             - RTLDULIST      -               
 SGDC_numflops11                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops10                clock-reset     No             - SETUP          -               
 SGDC_numflops09                clock-reset     No             - SETUP          -               
 SGDC_numflops08                clock-reset     No             - SETUP          -               
 SGDC_numflops07                clock-reset     No             - SETUP          -               
 SGDC_numflops06                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops05                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops04                clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops03d               clock-reset     No             - SETUP          -               
 SGDC_numflops03c               clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_numflops03b               clock-reset     No             - RTLDULIST      -               
 SGDC_numflops03a               clock-reset     No             - RTLDULIST      -               
 SGDC_numflops01                clock-reset     No             - SETUP          -               
 SGDC_porttimedelay01           clock-reset     No             - SETUP          -               
 SGDC_deltacheck_ignore_instance01 clock-reset     No             - SETUP          -               
 SGDC_deltacheck_ignore_module01 clock-reset     No             - SETUP          -               
 SGDC_deltacheck_stop_instance01 clock-reset     No             - SETUP          -               
 SGDC_deltacheck_stop_module01  clock-reset     No             - SETUP          -               
 SGDC_deltacheck_stop_signal01  clock-reset     No             - SETUP          -               
 SGDC_deltacheck_start02        clock-reset     No             - SETUP          -               
 SGDC_deltacheck_start01        clock-reset     No             - SETUP          -               
 SGDC_noclockcell04             clock-reset     No             - SETUP          -               
 SGDC_noclockcell03             clock-reset     No             - SETUP          -               
 SGDC_noclockcell02             clock-reset     No             - SETUP          -               
 SGDC_noclockcell01             clock-reset     No             - SETUP          -               
 SGDC_cdc_false_path03          clock-reset     No             - SETUP          -               
 SGDC_cdc_false_path02          clock-reset     No             - SETUP          -               
 SGDC_cdc_false_path01          clock-reset     No             - SETUP          -               
 SGDC_output_not_used01         clock-reset     No             - SETUP          -               
 SGDC_network_allowed_cells02   clock-reset     No             - SETUP          -               
 SGDC_network_allowed_cells01   clock-reset     No             - SETUP          -               
 SGDC_syncresetstyle01          clock-reset     No             - SETUP          -               
 SGDC_signal_in_domain04        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_signal_in_domain03        clock-reset     No             - SETUP          -               
 SGDC_signal_in_domain02        clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_signal_in_domain01        clock-reset     No             - SETUP          -               
 Setup_quasi_static01           clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_quasi_static_style02      clock-reset     No             - SETUP          -               
 SGDC_quasi_static_style01      clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_quasi_static01            clock-reset     No             - SETUP          -               
 SGDC_generated_clock05         clock-reset     No             - SETUP          -               
 SGDC_generated_clock04         clock-reset     No             - SETUP          -               
 SGDC_generated_clock03         clock-reset     No             - SETUP          -               
 SGDC_generated_clock02         clock-reset     No             - SETUP          -               
 SGDC_generated_clock01         clock-reset     No             - SETUP          -               
 SGDC_inputoutput01             clock-reset     No             - FLATDU2_ABSTRACT_PRD_WL   -               
 SGDC_output03                  clock-reset     No             - SETUP          -               
 SGDC_output04                  clock-reset     No             - RTLDULIST      -               
 SGDC_output02                  clock-reset     No             - RTLDULIST      -               
 SGDC_output01                  clock-reset     No             - SETUP          -               
 SGDC_input04                   clock-reset     No             - SETUP          -               
 SGDC_input03                   clock-reset     No             - RTLDULIST      -               
 SGDC_input02                   clock-reset     No             - RTLDULIST      -               
 SGDC_input01                   clock-reset     No             - SETUP          -               
 Const_Prelim_SDCCHECK          const_intern1   No             - SETUP          -               
 Sanity_Rule                    const_intern1   No             - SETUP          -               
 Consis_Auxi                    constraints     No             - SETUP          -               
 SDC_Consis_Block               constraints     No             - FLATBLOCKDU    -               
 SDC_Consis                     constraints     No             - FLATDU2_WL     -               
 SDC_Methodology74              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology73              constraints     No             - VSDU           -               
 SDC_Methodology72              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology71              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology70              constraints     No             - VSDU           -               
 XBuf_Auxi01                    constraints     No             - SETUP          -               
 XBuf01                         constraints     No             - FLATBLOCKDU    -               
 Check_Timing04                 constraints     No             - BLOCKDU_CD     -               
 Check_Timing03                 constraints     No             - FLATBLOCKDU    -               
 Check_Timing02                 constraints     No             - FLATBLOCKDU    -               
 Show_Clock_Propagation         constraints     No             - FLATBLOCKDU    -               
 VS_Show_Case_Analysis          constraints     No             - VSDU           -               
 Show_Case_Analysis             constraints     No             - FLATBLOCKDU    -               
 Test_Rules06                   constraints     No             - FLATBLOCKDU    -               
 Test_Rules05                   constraints     No             - FLATBLOCKDU    -               
 Test_Rules04                   constraints     No             - BLOCKDU_CD     -               
 Test_Rules03                   constraints     No             - FLATBLOCKDU    -               
 Test_Rules02                   constraints     No             - FLATBLOCKDU    -               
 Test_Rules01                   constraints     No             - BLOCKDU_CD     -               
 Load03                         constraints     No             - VSDU           -               
 SDC_DnStrm08                   constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology68              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology67              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology66              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology65              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology69              constraints     No             - VSDU           -               
 SDC_Methodology64              constraints     No             - VSDU           -               
 SDC_Methodology61              constraints     No             - VSDU           -               
 SDC_Methodology60              constraints     No             - VSDU           -               
 SDC_Methodology39              constraints     No             - VSDU           -               
 SDC_Methodology38              constraints     No             - VSDU           -               
 SDC_Methodology37              constraints     No             - VSDU           -               
 SDC_Methodology36              constraints     No             - VSDU           -               
 SDC_Methodology35              constraints     No             - VSDU           -               
 SDC_Methodology34              constraints     No             - VSDU           -               
 SDC_Methodology33              constraints     No             - VSDU           -               
 SDC_Methodology32              constraints     No             - VSDU           -               
 SDC_Methodology31              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology30              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology29              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology28              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology27              constraints     No             - VSDU           -               
 SDC_Case_Sanity01              constraints     No             - FLATBLOCKDU    -               
 SDC_Misc_Command01             constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology26              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology25              constraints     No             - BLOCKDU_CD     -               
 SDC_Misc_Power01               constraints     No             - BLOCKDU_CD     -               
 SDC_Report04                   constraints     No             - BLOCKDU_CD     -               
 SDC_Report03                   constraints     No             - VSDU           -               
 SDC_Methodology24              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology23              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology22              constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm07                   constraints     No             - BLOCKDU_CD     -               
 SDC_Misc_Setup01               constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology21              constraints     No             - VSDU           -               
 SDC_Methodology18              constraints     No             - VSDU           -               
 SDC_Methodology16              constraints     No             - VSDU           -               
 SDC_Methodology13              constraints     No             - VSDU           -               
 SDC_Methodology12              constraints     No             - VSDU           -               
 SDC_Methodology11              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology10              constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm06                   constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm05                   constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology09              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology07              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology06              constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology05a             constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology03              constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm04a                  constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm04                   constraints     No             - BLOCKDU_CD     -               
 SDC_Methodology02              constraints     No             - VSDU           -               
 SDC_Methodology01              constraints     No             - BLOCKDU_CD     -               
 SDC_DnStrm03                   constraints     No             - VSDU           -               
 SDC_DnStrm02                   constraints     No             - VSDU           -               
 SDC_DnStrm01                   constraints     No             - VSDU           -               
 SDC_Misc_WLM01                 constraints     No             - VSDU           -               
 SDC_Report01                   constraints     No             - FLATBLOCKDU    -               
 SDC_MergeBlocks                constraints     No             - VSTOPDU        -               
 Derate01                       constraints     No             - FLATBLOCKDU    -               
 SDC_ModeMerge                  constraints     No             - FLATDU2_WL     -               
 CONS_abstract01                constraints     No             - FLATBLOCKDU    -               
 SDC_DataSheet                  constraints     No             - FLATDU2_WL     -               
 SDC_Coverage                   constraints     No             - FLATDU2_WL     -               
 SDC_GenerateIncr               constraints     No             - FLATBLOCKDU    -               
 PRDGenAuxi                     constraints     No             - VSDU           -               
 Disable_Timing02               constraints     No             - FLATBLOCKDU    -               
 Disable_Timing01               constraints     No             - FLATBLOCKDU    -               
 CheckMCP                       constraints     No             - FLATBLOCKDU    -               
 MCP09                          constraints     No             - FLATBLOCKDU    -               
 MCP08                          constraints     No             - VSDU           -               
 MCP05                          constraints     No             - FLATBLOCKDU    -               
 MCP04b                         constraints     No             - VSDU           -               
 MCP04a                         constraints     No             - FLATBLOCKDU    -               
 MCP04                          constraints     No             - FLATBLOCKDU    -               
 MCP03                          constraints     No             - FLATBLOCKDU    -               
 MCP01                          constraints     No             - FLATBLOCKDU    -               
 False_Path13                   constraints     No             - FLATBLOCKDU    -               
 False_Path12                   constraints     No             - FLATBLOCKDU    -               
 False_Path11                   constraints     No             - VSDU           -               
 False_Path10                   constraints     No             - VSDU           -               
 False_Path09                   constraints     No             - VSDU           -               
 False_Path08                   constraints     No             - FLATBLOCKDU    -               
 False_Path07                   constraints     No             - FLATBLOCKDU    -               
 TE_Consis02                    constraints     No             - FLATBLOCKDU    -               
 TE_Consis01                    constraints     No             - FLATBLOCKDU    -               
 TE_Conflict01                  constraints     No             - FLATBLOCKDU    -               
 False_Path04b                  constraints     No             - VSDU           -               
 False_Path04a                  constraints     No             - FLATBLOCKDU    -               
 False_Path04                   constraints     No             - FLATBLOCKDU    -               
 False_Path03                   constraints     No             - FLATBLOCKDU    -               
 False_Path01                   constraints     No             - FLATBLOCKDU    -               
 IO_Consis07                    constraints     No             - FLATBLOCKDU    -               
 IO_Consis02                    constraints     No             - BLOCKDU_CD     -               
 IO_Consis01                    constraints     No             - BLOCKDU_CD     -               
 Combo_Paths06                  constraints     No             - FLATBLOCKDU    -               
 Combo_Paths04                  constraints     No             - FLATBLOCKDU    -               
 Combo_Paths03                  constraints     No             - FLATBLOCKDU    -               
 Combo_Paths02                  constraints     No             - BLOCKDU_CD     -               
 Combo_Paths01                  constraints     No             - FLATBLOCKDU    -               
 Load04                         constraints     No             - FLATBLOCKDU    -               
 Load02b                        constraints     No             - FLATBLOCKDU    -               
 Load02a                        constraints     No             - FLATBLOCKDU    -               
 Load01                         constraints     No             - BLOCKDU_CD     -               
 TE_Methodology02               constraints     No             - VSDU           -               
 Op_Del15                       constraints     No             - FLATBLOCKDU    -               
 Op_Del14                       constraints     No             - FLATBLOCKDU    -               
 Op_Del13                       constraints     No             - VSDU           -               
 Op_Del12                       constraints     No             - VSDU           -               
 Op_Del11                       constraints     No             - VSDU           -               
 Op_Del10                       constraints     No             - VSDU           -               
 Op_Del09                       constraints     No             - FLATBLOCKDU    -               
 Op_Del08                       constraints     No             - VSDU           -               
 Op_Del07a                      constraints     No             - FLATBLOCKDU    -               
 Op_Del07                       constraints     No             - FLATBLOCKDU    -               
 Op_Del05                       constraints     No             - BLOCKDU_CD     -               
 Op_Del04                       constraints     No             - VSDU           -               
 Op_Del03b                      constraints     No             - FLATBLOCKDU    -               
 Op_Del03a                      constraints     No             - FLATBLOCKDU    -               
 Op_Del02                       constraints     No             - FLATBLOCKDU    -               
 Op_Del01c                      constraints     No             - FLATBLOCKDU    -               
 Op_Del01b                      constraints     No             - FLATBLOCKDU    -               
 Op_Del01a                      constraints     No             - FLATBLOCKDU    -               
 Inp_Trans09                    constraints     No             - VSDU           -               
 Inp_Trans08                    constraints     No             - VSDU           -               
 Inp_Trans07                    constraints     No             - BLOCKDU_CD     -               
 Inp_Trans06                    constraints     No             - BLOCKDU_CD     -               
 Inp_Trans05                    constraints     No             - FLATBLOCKDU    -               
 Inp_Trans04                    constraints     No             - VSDU           -               
 Inp_Trans03a                   constraints     No             - VSDU           -               
 Inp_Trans03                    constraints     No             - VSDU           -               
 Inp_Trans02                    constraints     No             - VSDU           -               
 Inp_Trans01a                   constraints     No             - FLATBLOCKDU    -               
 Inp_Trans01                    constraints     No             - FLATBLOCKDU    -               
 Inp_Del15                      constraints     No             - FLATBLOCKDU    -               
 Inp_Del14                      constraints     No             - FLATBLOCKDU    -               
 Inp_Del13                      constraints     No             - VSDU           -               
 Inp_Del12                      constraints     No             - VSDU           -               
 Inp_Del11                      constraints     No             - VSDU           -               
 Inp_Del10                      constraints     No             - VSDU           -               
 Inp_Del09                      constraints     No             - FLATBLOCKDU    -               
 Inp_Del08                      constraints     No             - VSDU           -               
 Inp_Del07a                     constraints     No             - FLATBLOCKDU    -               
 Inp_Del07                      constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology63              constraints     No             - FLATBLOCKDU    -               
 SDC_Methodology62              constraints     No             - FLATBLOCKDU    -               
 Inp_Del05                      constraints     No             - BLOCKDU_CD     -               
 Inp_Del04                      constraints     No             - VSDU           -               
 Inp_Del03b                     constraints     No             - FLATBLOCKDU    -               
 Inp_Del03a                     constraints     No             - FLATBLOCKDU    -               
 Inp_Del02                      constraints     No             - FLATBLOCKDU    -               
 Inp_Del01c                     constraints     No             - FLATBLOCKDU    -               
 Inp_Del01b                     constraints     No             - FLATBLOCKDU    -               
 Inp_Del01a                     constraints     No             - FLATBLOCKDU    -               
 Clk_Consis05                   constraints     No             - BLOCKDU_CD     -               
 High_Fan16                     constraints     No             - FLATDU2_WL     -               
 High_Fan15                     constraints     No             - FLATBLOCKDU    -               
 High_Fan14                     constraints     No             - FLATBLOCKDU    -               
 High_Fan12                     constraints     No             - BLOCKDU_CD     -               
 High_Fan11                     constraints     No             - BLOCKDU_CD     -               
 High_Fan10                     constraints     No             - FLATBLOCKDU    -               
 High_Fan09                     constraints     No             - BLOCKDU_CD     -               
 High_Fan08                     constraints     No             - BLOCKDU_CD     -               
 High_Fan07                     constraints     No             - FLATBLOCKDU    -               
 High_Fan06                     constraints     No             - FLATBLOCKDU    -               
 High_Fan05                     constraints     No             - BLOCKDU_CD     -               
 High_Fan04                     constraints     No             - BLOCKDU_CD     -               
 High_Fan03b                    constraints     No             - FLATBLOCKDU    -               
 High_Fan03a                    constraints     No             - FLATBLOCKDU    -               
 High_Fan02                     constraints     No             - FLATBLOCKDU    -               
 High_Fan01a                    constraints     No             - BLOCKDU_CD     -               
 High_Fan01                     constraints     No             - BLOCKDU_CD     -               
 Dont_Touch05                   constraints     No             - BLOCKDU_CD     -               
 Dont_Touch04                   constraints     No             - FLATBLOCKDU    -               
 Dont_Touch03                   constraints     No             - FLATBLOCKDU    -               
 Dont_Touch02                   constraints     No             - FLATBLOCKDU    -               
 Clk_Trans17                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans16                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans15                    constraints     No             - VSDU           -               
 Clk_Trans13                    constraints     No             - VSDU           -               
 Clk_Trans12                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans11                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans09                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans08                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans07                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans06                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans05                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans04                    constraints     No             - BLOCKDU_CD     -               
 Clk_Trans03                    constraints     No             - VSDU           -               
 Clk_Trans02a                   constraints     No             - VSDU           -               
 Clk_Trans02                    constraints     No             - BLOCKDU_CD     -               
 Clk_Uncert11                   constraints     No             - VSDU           -               
 Clk_Uncert10                   constraints     No             - VSDU           -               
 Clk_Uncert09                   constraints     No             - VSDU           -               
 Clk_Uncert08                   constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert07                   constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert06                   constraints     No             - VSDU           -               
 Clk_Uncert05                   constraints     No             - BLOCKDU_CD     -               
 Clk_Uncert04                   constraints     No             - VSDU           -               
 Clk_Uncert03                   constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert02c                  constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert02b                  constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert02a                  constraints     No             - FLATBLOCKDU    -               
 Clk_Uncert01                   constraints     No             - FLATBLOCKDU    -               
 SCG05                          constraints     No             - FLATBLOCKDU    -               
 SCG04                          constraints     No             - FLATBLOCKDU    -               
 SCG03                          constraints     No             - FLATBLOCKDU    -               
 SCG02                          constraints     No             - FLATBLOCKDU    -               
 SCG01                          constraints     No             - FLATBLOCKDU    -               
 Clk_Lat12                      constraints     No             - VSDU           -               
 Clk_Lat10                      constraints     No             - VSDU           -               
 Clk_Lat09                      constraints     No             - BLOCKDU_CD     -               
 Clk_Lat08                      constraints     No             - VSDU           -               
 Clk_Lat07                      constraints     No             - BLOCKDU_CD     -               
 Clk_Lat06                      constraints     No             - BLOCKDU_CD     -               
 Clk_Lat05                      constraints     No             - VSDU           -               
 Clk_Lat04b                     constraints     No             - VSDU           -               
 Clk_Lat04a                     constraints     No             - VSDU           -               
 Clk_Lat03                      constraints     No             - FLATBLOCKDU    -               
 Clk_Lat02                      constraints     No             - FLATBLOCKDU    -               
 Clk_Lat01                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen36                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen35                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen34                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen33                      constraints     No             - FLATBLOCKDU    -               
 Gen33_Data                     constraints     No             - SETUP          -               
 Clk_Gen32                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen31                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen30                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen29                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen27                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen26                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen25                      constraints     No             - VSDU           -               
 Clk_Gen24                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen23a                     constraints     No             - FLATBLOCKDU    -               
 Clk_Gen23                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen22                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen21                      constraints     No             - BLOCKDU_CD     -               
 Clk_Gen20                      constraints     No             - VSDU           -               
 Clk_Gen19                      constraints     No             - VSDU           -               
 Clk_Gen18                      constraints     No             - BLOCKDU_CD     -               
 Clk_Gen17                      constraints     No             - BLOCKDU_CD     -               
 Clk_Gen15                      constraints     No             - VSDU           -               
 Clk_Gen14                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen13                      constraints     No             - BLOCKDU_CD     -               
 Clk_Gen10                      constraints     No             - VSDU           -               
 Clk_Gen09                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen08                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen07                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen06                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen05                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen03                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen02                      constraints     No             - FLATBLOCKDU    -               
 Clk_Gen01b                     constraints     No             - FLATBLOCKDU    -               
 Clk_Gen01a                     constraints     No             - FLATBLOCKDU    -               
 IO_Consis04                    constraints     No             - VSDU           -               
 MCP_B2BConsis01                constraints     No             - VSDU           -               
 Block06                        constraints     No             - FLATBLOCKDU    -               
 Block05                        constraints     No             - FLATBLOCKDU    -               
 Block13                        constraints     No             - FLATBLOCKDU    -               
 Block12                        constraints     No             - FLATBLOCKDU    -               
 Block11                        constraints     No             - FLATBLOCKDU    -               
 Block02                        constraints     No             - FLATDU2_WL     -               
 Const_Struct10                 constraints     No             - VSDU           -               
 Const_Struct09                 constraints     No             - BLOCKDU_CD     -               
 Const_Struct08                 constraints     No             - VSDU           -               
 Const_Struct07                 constraints     No             - VSDU           -               
 Const_Struct05                 constraints     No             - BLOCKDU_CD     -               
 Const_Struct04b                constraints     No             - FLATBLOCKDU    -               
 Const_Struct04a                constraints     No             - FLATBLOCKDU    -               
 Const_Struct03                 constraints     No             - VSDU           -               
 Const_Struct02                 constraints     No             - BLOCKDU_CD     -               
 Const_Struct01                 constraints     No             - BLOCKDU_CD     -               
 Domain_SGDC_Consis             constraints     No             - FLATBLOCKDU    -               
 DomainError                    constraints     No             - FLATBLOCKDU    -               
 DomainInfo                     constraints     No             - FLATBLOCKDU    -               
 Delay_Split                    constraints     No             - VSTOPDU        -               
 Delay_Auxi                     constraints     No             - SETUP          -               
 DomainAnalysis                 constraints     No             - FLATBLOCKDU    -               
 Block10                        constraints     No             - FLATBLOCKDU    -               
 GenSDCCrossingData             constraints     No             - FLATBLOCKDU    -               
 GenSDCData                     constraints     No             - FLATBLOCKDU    -               
 Block10_Data                   constraints     No             - SETUP          -               
 Constraints_MasterRule         constraints     No             - FLATBLOCKDU    -               
 Cons_SDC_Report                constraints     No             - FLATBLOCKDU    -               
 ConsReportAuxi01               constraints     No             - SETUP          -               
 ParamSanityCheck01b            constraints     No             - RTLALLDULIST   -               
 InternalRule01a                constraints     No             - RTLALLDULIST   -               
 ParamSanityCheck01a            constraints     No             - SETUP          -               
 DomainSanityCheck              constraints     No             - VSDU           -               
 Nom_Le_Call                    constraints     No             - VSDU           -               
 SDCPARSE                       constraints     No             - VSDU           -               
 Const_Sanity_Rule              constraints     No             - SETUP          -               
 dftFLATDU_RFExit               dft             No             - FLATDU2_PRD_WL   -               
 Coverage_audit                 dft             No             - FLATDU2_PRD_WL   -               
 Info_dft_deprecated            dft             No             - FLATDU2_PRD_WL   -               
 Info_DftDebugData              dft             No             - FLATDU2_PRD_WL   -               
 Tristate_18                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_17                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_16                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_15                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_14                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_13                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_12                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_11                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_10                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_09                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_08_shift              dft             No             - FLATDU2_PRD_WL   -               
 Tristate_08_capture            dft             No             - FLATDU2_PRD_WL   -               
 Tristate_07_shift              dft             No             - FLATDU2_PRD_WL   -               
 Tristate_07_capture            dft             No             - FLATDU2_PRD_WL   -               
 Tristate_06                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_05                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_04_shift              dft             No             - FLATDU2_PRD_WL   -               
 Tristate_04_capture            dft             No             - FLATDU2_PRD_WL   -               
 Tristate_03                    dft             No             - FLATDU2_PRD_WL   -               
 Tristate_01                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_15                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_14                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_13                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_12                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_11                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_10                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_09                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_07_flat               dft             No             - FLATDU2_PRD_WL   -               
 Topology_05                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_04                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_03                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_02                    dft             No             - FLATDU2_PRD_WL   -               
 Topology_01                    dft             No             - FLATDU2_PRD_WL   -               
 TA_10                          dft             No             - FLATDU2_PRD_WL   -               
 TA_09                          dft             No             - FLATDU2_PRD_WL   -               
 TA_08                          dft             No             - FLATDU2_PRD_WL   -               
 TA_07                          dft             No             - FLATDU2_PRD_WL   -               
 TA_06                          dft             No             - FLATDU2_PRD_WL   -               
 TA_02                          dft             No             - FLATDU2_PRD_WL   -               
 TA_01                          dft             No             - FLATDU2_PRD_WL   -               
 Scan_41                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_40                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_39                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_38                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_36                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_35                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_34                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_33                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_32                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_31                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_30                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_29                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_28                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_27                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_26                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_25                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_24                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_23                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_22                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_21                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_20                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_19                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_18                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_17                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_16                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_11                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_08                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_07                        dft             No             - FLATDU2_PRD_WL   -               
 Scan_06                        dft             No             - FLATDU2_PRD_WL   -               
 RAM_11                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_10                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_09                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_08                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_07                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_06                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_05                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_04                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_03                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_02                         dft             No             - FLATDU2_PRD_WL   -               
 RAM_01                         dft             No             - FLATDU2_PRD_WL   -               
 Power_01                       dft             No             - FLATDU2_PRD_WL   -               
 Info_latchMapping              dft             No             - FLATDU2_PRD_WL   -               
 Info_latch                     dft             No             - FLATDU2_PRD_WL   -               
 Latch_19                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_18                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_16                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_15                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_10                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_08                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_06                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_04                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_02                       dft             No             - FLATDU2_PRD_WL   -               
 Latch_01                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_30                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_29                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_28                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_27                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_26                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_25                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_24                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_23                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_22                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_21                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_18                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_17                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_16                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_14                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_11_capture               dft             No             - FLATDU2_PRD_WL   -               
 Clock_11                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_10                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_09                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_08                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_05                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_04                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_03                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_02                       dft             No             - FLATDU2_PRD_WL   -               
 Clock_01                       dft             No             - FLATDU2_PRD_WL   -               
 BIST_05                        dft             No             - FLATDU2_PRD_WL   -               
 BIST_04                        dft             No             - FLATDU2_PRD_WL   -               
 BIST_03                        dft             No             - FLATDU2_PRD_WL   -               
 BIST_02                        dft             No             - FLATDU2_PRD_WL   -               
 BIST_01                        dft             No             - FLATDU2_PRD_WL   -               
 Async_16                       dft             No             - FLATDU2_PRD_WL   -               
 Async_15                       dft             No             - FLATDU2_PRD_WL   -               
 Async_13                       dft             No             - FLATDU2_PRD_WL   -               
 Async_12                       dft             No             - FLATDU2_PRD_WL   -               
 Async_11                       dft             No             - FLATDU2_PRD_WL   -               
 Async_10                       dft             No             - FLATDU2_PRD_WL   -               
 Async_09                       dft             No             - FLATDU2_PRD_WL   -               
 Async_08                       dft             No             - FLATDU2_PRD_WL   -               
 Async_07Lssd                   dft             No             - FLATDU2_PRD_WL   -               
 Async_07                       dft             No             - FLATDU2_PRD_WL   -               
 Async_06                       dft             No             - FLATDU2_PRD_WL   -               
 Async_05                       dft             No             - FLATDU2_PRD_WL   -               
 Async_04                       dft             No             - FLATDU2_PRD_WL   -               
 Async_03                       dft             No             - FLATDU2_PRD_WL   -               
 Async_02_shift                 dft             No             - FLATDU2_PRD_WL   -               
 Async_02_capture               dft             No             - FLATDU2_PRD_WL   -               
 Async_01                       dft             No             - FLATDU2_PRD_WL   -               
 Info_dBist                     dft             No             - FLATDU2_PRD_WL   -               
 Info_scanwrap                  dft             No             - FLATDU2_PRD_WL   -               
 Info_blackboxDriver            dft             No             - FLATDU2_PRD_WL   -               
 Info_addFault                  dft             No             - FLATDU2_PRD_WL   -               
 Info_stilFile                  dft             No             - FLATDU2_PRD_WL   -               
 Info_scanchain                 dft             No             - FLATDU2_PRD_WL   -               
 Info_inferredNoScan            dft             No             - FLATDU2_PRD_WL   -               
 Info_forcedScan                dft             No             - FLATDU2_PRD_WL   -               
 Info_noScan                    dft             No             - FLATDU2_PRD_WL   -               
 Info_noFault                   dft             No             - FLATDU2_PRD_WL   -               
 Info_memoryforce               dft             No             - FLATDU2_PRD_WL   -               
 Info_memorywritedisable        dft             No             - FLATDU2_PRD_WL   -               
 Info_testclock                 dft             No             - FLATDU2_PRD_WL   -               
 Info_testmode_conflict_01      dft             No             - FLATDU2_PRD_WL   -               
 Info_testmode                  dft             No             - FLATDU2_PRD_WL   -               
 Info_undetectCause             dft             No             - FLATDU2_PRD_WL   -               
 Info_coverageAtGateLevel       dft             No             - FLATDU2_PRD_WL   -               
 Info_potDetectable             dft             No             - FLATDU2_PRD_WL   -               
 Info_coverage                  dft             No             - FLATDU2_PRD_WL   -               
 Info_logicalRedundant          dft             No             - FLATDU2_PRD_WL   -               
 Info_untestable                dft             No             - FLATDU2_PRD_WL   -               
 Info_unobservable              dft             No             - FLATDU2_PRD_WL   -               
 Info_pwrGndSim                 dft             No             - FLATDU2_PRD_WL   -               
 Info_path                      dft             No             - FLATDU2_PRD_WL   -               
 Info_uncontrollable            dft             No             - FLATDU2_PRD_WL   -               
 Info_unused                    dft             No             - FLATDU2_PRD_WL   -               
 Info_synthRedundant            dft             No             - FLATDU2_PRD_WL   -               
 Info_levelize                  dft             No             - FLATDU2_PRD_WL   -               
 Diagnose_testclock             dft             No             - FLATDU2_PRD_WL   -               
 Diagnose_testmode              dft             No             - FLATDU2_PRD_WL   -               
 CreateDebugSGDC                dft             No             - FLATDU2_PRD_WL   -               
 Diagnose_ScanChain             dft             No             - FLATDU2_PRD_WL   -               
 dumpBlackBox                   dft             No             - FLATDU2_PRD_WL   -               
 dftMultiplyDrivenPowerRail     dft             No             - FLATDU2_PRD_WL   -               
 dftParamCheck_01               dft             No             - SETUP          -               
 dftSGDCSTX_075                 dft             No             - SETUP          -               
 dftSGDCSTX_071                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_070                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_078                 dft             No             - SETUP          -               
 dftSGDCSTX_077                 dft             No             - SETUP          -               
 dftSGDCSTX_076                 dft             No             - SETUP          -               
 dftSGDCSTX_074                 dft             No             - SETUP          -               
 dftSGDCSTX_072                 dft             No             - SETUP          -               
 dftSGDCSTX_068                 dft             No             - SETUP          -               
 dftSGDCSTX_067                 dft             No             - SETUP          -               
 dftSGDCSTX_066                 dft             No             - SETUP          -               
 dftSGDCSTX_065                 dft             No             - SETUP          -               
 dftSGDCSTX_064                 dft             No             - FLATDU2_PRD_WL   -               
 Conn_12                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_11                        dft             No             - FLATDU2_PRD_WL   -               
 Soc_12                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_11                         dft             No             - FLATDU2_PRD_WL   -               
 Info_define_tag                dft             No             - FLATDU2_PRD_WL   -               
 Conn_15                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_14                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_10                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_09                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_08                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_07                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_02                        dft             No             - FLATDU2_PRD_WL   -               
 Conn_01                        dft             No             - FLATDU2_PRD_WL   -               
 Soc_14                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_10                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_09                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_08                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_07_Info                    dft             No             - FLATDU2_PRD_WL   -               
 Soc_07                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_06                         dft             No             - VSTOPDU        -               
 Soc_04                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_02_Info                    dft             No             - FLATDU2_PRD_WL   -               
 Soc_02                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_01_Info                    dft             No             - FLATDU2_PRD_WL   -               
 Soc_01                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_00                         dft             No             - FLATDU2_PRD_WL   -               
 Soc_05                         dft             No             - FLATDU2_PRD_WL   -               
 dftUserMacroSanityCheck_01     dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_063                 dft             No             - SETUP          -               
 dftSGDCSTX_062                 dft             No             - SETUP          -               
 dftSGDCSTX_057                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_055                 dft             No             - SETUP          -               
 dftSGDCSTX_054                 dft             No             - SETUP          -               
 dftSGDCSTX_053                 dft             No             - SETUP          -               
 dftSGDCSTX_051                 dft             No             - SETUP          -               
 dftFLATDU_RFSetUp              dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_069                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_061                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_060                 dft             No             - FLATDU2_PRD_WL   -               
 dftSGDCSTX_059                 dft             No             - FLATDU2_PRD_WL   -               
 dftVSTOPDUExit                 dft             No             - VSTOPDU        -               
 Clock_06                       dft             No             - VSTOPDU        -               
 dftVSTOPDUSetUp                dft             No             - VSTOPDU        -               
 dftRTLTOPDUExit                dft             No             - RTLTOPDU       -               
 Topology_07_rtl      (Verilog) dft             No             - RTLTOPDU       -               
 dftOptional_Constraint_Check   dft             No             - RTLTOPDU       -               
 dftMandatory_Constraint_Check  dft             No             - RTLTOPDU       -               
 dftSGDCExistence_00            dft             No             - RTLALLDULIST   -               
 dftRTLTOPDUSetUp               dft             No             - RTLTOPDU       -               
 dftCumulativeFaultStatusFileCheck dft             No             - SETUP          -               
 dftSGDCSTX_058                 dft             No             - SETUP          -               
 dftSGDCSTX_073                 dft             No             - SETUP          -               
 dftAutoFixSelective            dft             No             - FLATDU2_PRD_WL   -               
 dftSetup                       dft             No             - SETUP          -               
 dsmFLATDU_RFExit               dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_transitionCoverage_audit  dft_dsm         No             - FLATDU2_PRD_WL   -               
 TC_05                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 TC_04                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 TC_03                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 TC_02                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 TC_01                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SP_05                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SP_04                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SP_03                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SP_02                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SP_01                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_06                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_05                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_04                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_03                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_02                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_01                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_Sanity_05                   dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_Sanity_04                   dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_Sanity_03                   dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_Sanity_02                   dft_dsm         No             - FLATDU2_PRD_WL   -               
 SE_Sanity_01                   dft_dsm         No             - FLATDU2_PRD_WL   -               
 PLL_03                         dft_dsm         No             - FLATDU2_PRD_WL   -               
 PLL_02                         dft_dsm         No             - FLATDU2_PRD_WL   -               
 PLL_01                         dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_enabledFlops              dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_Top_SGDC_Report           dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_IP_Report                 dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_Atspeed_21                dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_noAtspeed                 dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_atspeedClockSynchronization dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_faultNode                 dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_transitionCoverage        dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_random_resistance         dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_atSpeedFrequency_EnableConflict dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_atSpeedFrequency          dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_atSpeedClock              dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_atSpeedDomain             dft_dsm         No             - FLATDU2_PRD_WL   -               
 Info_freqAssignTable           dft_dsm         No             - SETUP          -               
 Diagnose_04                    dft_dsm         No             - FLATDU2_PRD_WL   -               
 Diagnose_03                    dft_dsm         No             - FLATDU2_PRD_WL   -               
 Diagnose_02                    dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_consistency                 dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_generateReport              dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_07                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_06                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_05                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_04                          dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_03_atspeed                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_03_capture                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_02_atspeed                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_02_capture                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_01_atspeed                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_01_capture                  dft_dsm         No             - FLATDU2_PRD_WL   -               
 CG_01_shift                    dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_34                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_33                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_32                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_31                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_30                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_29                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_27                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_26                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_25                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_24                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_23                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_22                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_21                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_20                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_19                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_17_captureatspeed      dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_17_capture             dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_17_shift               dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_15                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_14                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_13                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_12                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_11                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_10                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_09                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_08                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_07                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_06                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_05                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_04                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_03                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 Atspeed_01                     dft_dsm         No             - FLATDU2_PRD_WL   -               
 dftDsmConstraintCheck_08       dft_dsm         No             - FLATDU2_PRD_WL   -               
 dftDsmConstraintCheck_07       dft_dsm         No             - FLATDU2_PRD_WL   -               
 dsmFLATDU_WL_Init              dft_dsm         No             - FLATDU2_PRD_WL   -               
 dsmBlockDU_ReadSDC             dft_dsm         No             - FLATBLOCKDU    -               
 dsmVSTOPDU_Init                dft_dsm         No             - VSDU           -               
 dftDsmConstraintCheck_06       dft_dsm         No             - FLATDU2_PRD_WL   -               
 dftDsmConstraintCheck_ComplexCell dft_dsm         No             - FLATDU2_PRD_WL   -               
 dftDsmConstraintCheck_05(VHDL   ) dft_dsm         No             - ELABDU         -               
 dftDsmConstraintCheck_04(Verilog) dft_dsm         No             - ELABDU         -               
 dftDsmConstraintCheck_02       dft_dsm         No             - SETUP          -               
 dftDsmConstraintCheck_01       dft_dsm         No             - SETUP          -               
 DFT_LP_LIB_DATA                dft_dsm         No             - VSTOPDU        -               
 DFT_LP_POWERDATA_CHECK         dft_dsm         No             - SETUP          -               
 dsmCumulativeFaultStatusFileCheck dft_dsm         No             - SETUP          -               
 dsmSetup                       dft_dsm         No             - SETUP          -               
 dsmParamCheck_00               dft_dsm         No             - SETUP          -               
 LPSVM44                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM58                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM57                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM56B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM56A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM55                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM54                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM49                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM36                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM33                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB12                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM46                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM45                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB18B                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB18A                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB14                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB14PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB13                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB11                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB10                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB08                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB07                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB07PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB16                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB15                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB06                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB05                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB04                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB04PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 PLIB_PREREQ_CHECKS             lowpower        No             - VSTOPDU        -               
 PLIB_CONSTR_CHECKS             lowpower        No             - VSTOPDU        -               
 LPSVM15                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM29                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM41                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM38                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM37                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC06                        lowpower        No             - FLATDU2_PRD_WL   -               
 LP_FLATDU_EXIT                 lowpower        No             - FLATDU2_PRD_WL   -               
 LP_INTERMEDIATE_DOMAIN_CROSSING_CHECK lowpower        No             - FLATDU2_PRD_WL   -               
 LP_MULTI_DOMAIN_CROSSING_CHECK lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN06                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN05C                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN05B                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN05A                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN05PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04E                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04D                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04C                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04B                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04A                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN04PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN03                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH02                        lowpower        No             - VSTOPDU        -               
 LPLSH01                        lowpower        No             - VSTOPDU        -               
 LPCONN02                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN01                       lowpower        No             - FLATDU2_PRD_WL   -               
 LP_LSH_REPORT                  lowpower        No             - FLATDU2_PRD_WL   -               
 LP_ISO_REPORT                  lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO07                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO06B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO06A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC05                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC04B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC04A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC03A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC02B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC02A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC01C                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC01B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERC01A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPERCPR                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM53                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO05B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO05A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO04D                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO04C                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO04B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO04A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISOPR                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSUP03                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSUP01                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO03B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO03A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO02                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPTIE02                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPTIE01                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPSW04                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPSW03                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPSW02                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPSW01                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPAON02                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPAON01                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM52                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM43                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM42                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM59                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM51                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM50                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM48                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM47                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM35                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM34                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM33A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM28                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM40                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM31                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB20                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB19A                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB17                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB17PR                     lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower22                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower11                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower21                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower17                 lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM26                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM24                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM60                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM22                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPISO01                        lowpower        No             - FLATDU2_PRD_WL   -               
 vdPDInfo                       lowpower        No             - FLATDU2_PRD_WL   -               
 PairWiseVDCrossing             lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM17                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM12B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM12A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM12PR                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM10                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM09                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM08C                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM08B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM08A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM60PR                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM08PR                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH08                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH07                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH06                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH05B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH05A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH04                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN09                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN08                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN07B                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPCONN07A                      lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSH03                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPLSHPR                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04E                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04D                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04C                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPSVM04PR                      lowpower        No             - FLATDU2_PRD_WL   -               
 LP_FLATPRD_EXIT                lowpower        No             - FLATDU2_PRD_WL   -               
 LP_SDC_PARSE_DEBUG             lowpower        No             - VSDU           -               
 LP_INTERNAL_RULE_FOR_SV        lowpower        No             - VSTOPDU        -               
 LP_DECOMPILE_CONSTR            lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower15                 lowpower        No             - FLATDU2_PRD_WL   -               
 PV_AbstractReadInfo            lowpower        No             - FLATDU2_PRD_WL   -               
 PV_Abstract01                  lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower30                 lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET04B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET04A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET03B                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET03A                       lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET02                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPRETPR                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPRET01                        lowpower        No             - FLATDU2_PRD_WL   -               
 LPPLIB00                       lowpower        No             - RTLTOPDU       -               
 LPCheckVCD                     lowpower        No             - FLATDU         -               
 LP_SPECIAL_PIN_CONNECTION      lowpower        No             - FLATDU2_PRD_WL   -               
 LPLIB_check04                  lowpower        No             - VSTOPDU        -               
 LPLIB_check03                  lowpower        No             - VSTOPDU        -               
 LPLIB_check02                  lowpower        No             - VSTOPDU        -               
 LPLIB_check01                  lowpower        No             - VSTOPDU        -               
 LpWildCardMatchReport          lowpower        No             - VSTOPDU        -               
 LPCheckLEF                     lowpower        No             - SETUP          -               
 LpParamSanityCheck             lowpower        No             - SETUP          -               
 PV_MasterRule                  lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_ISO_PRD_ASSOCIATION        lowpower        No             - FLATDU2_PRD_WL   -               
 LP_CHECK_CONSTR                lowpower        No             - VSTOPDU        -               
 LpWildCardMatchReportSetup     lowpower        No             - VSTOPDU        -               
 LP_LIB_DATA                    lowpower        No             - VSTOPDU        -               
 SGDC_lowpower_RuleReq          lowpower        No             - VSTOPDU        -               
 UPF_lowpower27                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower26                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower25                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower29                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower28                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower24                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower20                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower19                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower18                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower16                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower13                 lowpower        No             - FLATDU2_PRD_WL   -               
 SGDC_lowpower120               lowpower        No             - FLATDU2_PRD_WL   -               
 checkCPF_existence             lowpower        No             - VSTOPDU        -               
 CPF_lowpower10                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower09                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower07                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower05                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower04                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower03                 lowpower        No             - VSTOPDU        -               
 CPF_lowpower01                 lowpower        No             - VSTOPDU        -               
 SGDC_lowpower119               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower118               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower117               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower116               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower115               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower114               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower113               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower112               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower110               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower109               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower108               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower107               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower105               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower104               lowpower        No             - VSTOPDU        -               
 SGDC_lowpower103               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower101               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower100               lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower99                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower98                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower97                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower96                lowpower        No             - SETUP          -               
 SGDC_lowpower95                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower94                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower93                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower92                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower91                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower90                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower89                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower87                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower86                lowpower        No             - SETUP          -               
 SGDC_lowpower85                lowpower        No             - SETUP          -               
 SGDC_lowpower82                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower78                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower77                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower75                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower72                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower71                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower69                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower68                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower67                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower66                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower65                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower62                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower61                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower60                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower59                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower52                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower48                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower47                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower40                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower34                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower32                lowpower        No             - VSTOPDU        -               
 SGDC_lowpower31                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower30                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower24                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower23                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower19                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower18                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower17                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower15                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower12                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower09                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower07                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower06                lowpower        No             - RTLTOPDU       -               
 SGDC_lowpower05                lowpower        No             - RTLTOPDU       -               
 LP_SGDC_CHECKS                 lowpower        No             - VSTOPDU        -               
 LP_CROSSING_DATA               lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower12                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower23                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower09                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower09PR               lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower07                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower07PR               lowpower        No             - FLATDU2_PRD_WL   -               
 LP_BLACKBOX_CHECK              lowpower        No             - FLATDU2_PRD_WL   -               
 LP_CROSSING_DATA_SETUP         lowpower        No             - FLATDU2_PRD_WL   -               
 checkUPF_existence             lowpower        No             - VSTOPDU        -               
 LPwrRulesSetup                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower14                 lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower14PR               lowpower        No             - FLATDU2_PRD_WL   -               
 UPF_lowpower10                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower08                 lowpower        No             - FLATDU2_ABSTRACT_PRD_WL   -               
 UPF_lowpower08PR               lowpower        No             - FLATDU2_ABSTRACT_PRD_WL   -               
 UPF_lowpower06                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower05                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower05PR               lowpower        No             - VSTOPDU        -               
 UPF_lowpower04                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower03                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower02                 lowpower        No             - VSTOPDU        -               
 UPF_lowpower01                 lowpower        No             - VSTOPDU        -               
 LP_POWERDATA_INFO              lowpower        No             - VSTOPDU        -               
 LP_POWERDATA_READ              lowpower        No             - SETUP          -               
 LP_POWERDATA_CHECK             lowpower        No             - SETUP          -               
 PECHECK54                      power_est       No             - SETUP          -               
 PRCHECK01                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK48                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK55                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK51                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK52                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK45                      power_est       No             - RTLALLDULIST   -               
 PECHECK44                      power_est       No             - RTLALLDULIST   -               
 PECHECK47                      power_est       No             - SETUP          -               
 PECHECK46                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK38                      power_est       No             - RTLALLDULIST   -               
 PECHECK34                      power_est       No             - SETUP          -               
 PECHECK33                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK32                      power_est       No             - SETUP          -               
 PECHECK53                      power_est       No             - SETUP          -               
 PECHECK31                      power_est       No             - SETUP          -               
 PECHECK29                      power_est       No             - SETUP          -               
 PECHECK28                      power_est       No             - SETUP          -               
 PECHECK25                      power_est       No             - RTLALLDULIST   -               
 PECHECK24                      power_est       No             - SETUP          -               
 PESTR32              (Verilog) power_est       No             - ELABDU         -               
 PESTR32              (VHDL   ) power_est       No             - ELABDU         -               
 PEPWR18                        power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK22                      power_est       No             - RTLALLDULIST   -               
 PESAE08                        power_est       No             - FLATDU2_PRD_WL   -               
 PECDMISGDC                     power_est       No             - FLATDU2_PRD_WL   -               
 PECWL                          power_est       No             - FLATDU2_PRD_WL   -               
 PESAE07                        power_est       No             - FLATDU2_PRD_WL   -               
 PESAE06                        power_est       No             - FLATDU2_PRD_WL   -               
 poweraudit                     power_est       No             - FLATDU2_PRD_WL   -               
 PESTR12                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR11                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR10                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR09                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR08                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR06                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR06                        power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK21                      power_est       No             - FLATDU2_PRD_WL   -               
 PESTR13                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR13                        power_est       No             - FLATDU2_PRD_WL   -               
 PECON01                        power_est       No             - FLATDU2_PRD_WL   -               
 PERES02                        power_est       No             - FLATDU2_PRD_WL   -               
 PERES01                        power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK27                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK26                      power_est       No             - FLATDU2_PRD_WL   -               
 PESTR05                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR03                        power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK50                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK30                      power_est       No             - SETUP          -               
 PECHECK20                      power_est       No             - SETUP          -               
 PECHECK23                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK16                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK15                      power_est       No             - VSTOPDU        -               
 PECHECK14                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK42                      power_est       No             - VSTOPDU        -               
 PECHECK08                      power_est       No             - VSTOPDU        -               
 PECHECK07                      power_est       No             - RTLALLDULIST   -               
 PECHECK06                      power_est       No             - FLATDU2_PRD_WL   -               
 sgdc2sdc                       power_est       No             - RTLALLDULIST   -               
 PECHECK05                      power_est       No             - RTLALLDULIST   -               
 PECHECK03                      power_est       No             - FLATDU2_PRD_WL   -               
 PESAE04                        power_est       No             - FLATDU2_PRD_WL   -               
 PESAE03                        power_est       No             - FLATDU2_PRD_WL   -               
 PECLKTREE                      power_est       No             - FLATDU2_PRD_WL   -               
 PESETUP01                      power_est       No             - FLATDU2_PRD_WL   -               
 PEPESD01                       power_est       No             - FLATDU2_PRD_WL   -               
 PRFIFOS01                      power_est       No             - FLATDU2_PRD_WL   -               
 PRARITH01                      power_est       No             - FLATDU2_PRD_WL   -               
 PRCOUNT01                      power_est       No             - FLATDU2_PRD_WL   -               
 PESAE02                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR02                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR14                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR05                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR27                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR03                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR26                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR30                        power_est       No             - FLATDU2_PRD_WL   -               
 PESLEWEXTRACT                  power_est       No             - FLATDU2_PRD_WL   -               
 PEVLESSINIT                    power_est       No             - FLATDU2_PRD_WL   -               
 PESTR31                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR25                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR29                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR28                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR24                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR23                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR22                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR21                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR20                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR25                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR29                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR28                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR24                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR23                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR22                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR21                        power_est       No             - FLATDU2_PRD_WL   -               
 PESTR20                        power_est       No             - FLATDU2_PRD_WL   -               
 PEPWR01                        power_est       No             - FLATDU2_PRD_WL   -               
 PEATD01                        power_est       No             - FLATDU2_PRD_WL   -               
 PECSA01                        power_est       No             - FLATDU2_PRD_WL   -               
 PEVTDIST                       power_est       No             - FLATDU2_PRD_WL   -               
 PECELLDIST                     power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK02                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK12                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK41                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK39                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK11                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK10                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK01                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK13B                     power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK13                      power_est       No             - FLATDU2_PRD_WL   -               
 PECHECK37                      power_est       No             - SETUP          -               
 PECHECK40                      power_est       No             - FLATDU2_WL     -               
 PESDCINIT                      power_est       No             - VSDU           -               
 PESPEFINIT                     power_est       No             - VSTOPDU        -               
 PECHECK49                      power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_set_black_box_power02     power_est       No             - SETUP          -               
 SGDC_set_black_box_power01     power_est       No             - SETUP          -               
 SGDC_power_est68               power_est       No             - SETUP          -               
 SGDC_power_est67               power_est       No             - SETUP          -               
 SGDC_power_est66               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est65               power_est       No             - SETUP          -               
 SGDC_power_est63               power_est       No             - SETUP          -               
 SGDC_power_est61               power_est       No             - SETUP          -               
 SGDC_power_est62               power_est       No             - SETUP          -               
 SGDC_power_est59               power_est       No             - SETUP          -               
 SGDC_power_est58               power_est       No             - SETUP          -               
 SGDC_power_est57               power_est       No             - SETUP          -               
 SGDC_power_est56               power_est       No             - VSTOPDU        -               
 SGDC_power_est55               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est54               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est53               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est52               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est47               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est64               power_est       No             - VSTOPDU        -               
 SGDC_power_est46               power_est       No             - SETUP          -               
 SGDC_power_est45               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est44               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est43               power_est       No             - VSTOPDU        -               
 SGDC_power_est42               power_est       No             - SETUP          -               
 SGDC_power_est41               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est40               power_est       No             - SETUP          -               
 SGDC_power_est39               power_est       No             - SETUP          -               
 SGDC_power_est38               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est37               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est36               power_est       No             - RTLTOPDU       -               
 SGDC_power_est35               power_est       No             - RTLTOPDU       -               
 SGDC_power_est34               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est33               power_est       No             - RTLALLDULIST   -               
 UPF_power_est05                power_est       No             - RTLTOPDU       -               
 UPF_power_est04                power_est       No             - RTLTOPDU       -               
 UPF_power_est03                power_est       No             - RTLTOPDU       -               
 UPF_power_est02                power_est       No             - RTLTOPDU       -               
 UPF_power_est01                power_est       No             - VSTOPDU        -               
 SGDC_power_est48               power_est       No             - FLATDU2_PRD_WL   -               
 CPF_power_est02                power_est       No             - RTLTOPDU       -               
 CPF_power_est01                power_est       No             - VSTOPDU        -               
 SGDC_power_est51               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est50               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est49               power_est       No             - RTLTOPDU       -               
 SGDC_power_est31               power_est       No             - VSTOPDU        -               
 SGDC_power_est30               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est32               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est28               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est27               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est26               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est25               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est24               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est23               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est22               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est21               power_est       No             - FLATDU2_PRD_WL   -               
 SGDC_power_est20               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est18               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est17               power_est       No             - SETUP          -               
 SGDC_power_est16               power_est       No             - SETUP          -               
 SGDC_power_est15               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est14               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est13               power_est       No             - SETUP          -               
 SGDC_power_est12               power_est       No             - SETUP          -               
 SGDC_power_est11               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est10               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est09               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est08               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est05               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est04               power_est       No             - RTLALLDULIST   -               
 SGDC_power_est03               power_est       No             - RTLALLDULIST   -               
 Txv_Incremental_Sanity         txv             No             - FLATBLOCKDU    -               
 Txv_PC01                       txv             No             - FLATBLOCKDU    -               
 Txv_Gen_Assert                 txv             No             - FLATBLOCKDU    -               
 Txv_ignored_comment            txv             No             - FLATBLOCKDU    -               
 Txv_MCP_StartEnd01             txv             No             - FLATBLOCKDU    -               
 Txv_MCP_Warn04                 txv             No             - FLATBLOCKDU    -               
 Txv_FP_Warn04                  txv             No             - FLATBLOCKDU    -               
 MCP_Info03                     txv             No             - FLATBLOCKDU    -               
 MCP_Info02                     txv             No             - FLATBLOCKDU    -               
 Txv_Info09                     txv             No             - FLATBLOCKDU    -               
 Txv_Info08                     txv             No             - FLATBLOCKDU    -               
 Txv_Info06                     txv             No             - FLATBLOCKDU    -               
 MCP_Verif01                    txv             No             - SETUP          -               
 Txv_C2C_Fp                     txv             No             - FLATBLOCKDU    -               
 Txv_FP_Glitch01                txv             No             - FLATBLOCKDU    -               
 FP_Verif01                     txv             No             - SETUP          -               
 Txv_Auxi04                     txv             No             - SETUP          -               
 Txv_Auxi03                     txv             No             - SETUP          -               
 Txv_Auxi02                     txv             No             - SETUP          -               
 Txv_Auxi01                     txv             No             - SETUP          -               
 Txv_Info01                     txv             No             - FLATBLOCKDU    -               
 TXV_ClockGen01                 txv             No             - FLATBLOCKDU    -               
 TXV_ClockVerify01              txv             No             - FLATBLOCKDU    -               
 Txv_GenMCP                     txv             No             - FLATBLOCKDU    -               
 Txv_CP01                       txv             No             - FLATBLOCKDU    -               
 Txv_MCP01                      txv             No             - FLATBLOCKDU    -               
 Txv_SCG01                      txv             No             - FLATBLOCKDU    -               
 Txv_FP01                       txv             No             - FLATBLOCKDU    -               
 Txv_MCP_Warn05                 txv             No             - FLATBLOCKDU    -               
 Txv_FP_Warn05                  txv             No             - FLATBLOCKDU    -               
 Txv_InitState01                txv             No             - FLATBLOCKDU    -               
 Txv_Info07                     txv             No             - FLATBLOCKDU    -               
 Txv_CP_Skip01                  txv             No             - FLATBLOCKDU    -               
 Txv_Info04                     txv             No             - FLATBLOCKDU    -               
 Txv_OvlRtl           (VHDL   ) txv             No             - ELABDU         -               
 Txv_OvlRtl           (Verilog) txv             No             - ELABDU         -               
 Txv_DomainMatrix               txv             No             - FLATBLOCKDU    -               
 Txv_DomainMissing              txv             No             - FLATBLOCKDU    -               
 Txv_DomainConflict             txv             No             - FLATBLOCKDU    -               
 Txv_assume_waveform            txv             No             - FLATBLOCKDU    -               
 Txv_mcp_info                   txv             No             - FLATBLOCKDU    -               
 Txv_TotalRunTime               txv             No             - FLATBLOCKDU    -               
 Populate_sdc                   txv             No             - VSDU           -               
 Txv_Sanity_Rule                txv             No             - SETUP          -               
 REDUNDANT_CIRCUIT              starcad-21      No             - FLATDU2_WL     -               
 CLOCK_WHEN                     starcad-21      No             - FLATDU2_WL     -               
 CLOCK_NO_TIMINGARC             starcad-21      No             - FLATDU2_WL     -               
 SYNC_MULTICLOCK                starcad-21      No             - FLATDU2_WL     -               
 CLOCK_COMB_MERGE               starcad-21      No             - FLATDU2_WL     -               
 starcad_21_Prereq              starcad-21      No             - FLATDU2_WL     -               
 SYSTEM_SETRESET                starcad-21      No             - FLATDU2_WL     -               
 BOTH_SETRESET                  starcad-21      No             - FLATDU2_WL     -               
 CLOCK_MUX_S                    starcad-21      No             - FLATDU2_WL     -               
 MANDATORY_BLOCK_CONNECTION     starcad-21      No             - FLATDU2_WL     -               
 INHIBIT_BLOCK_CONNECTION       starcad-21      No             - FLATDU2_WL     -               
 LAYOUT_MODULE_OUTPINCONNTOTRISTATE starcad-21      No             - VSTOPDU        -               
 LAYOUT_MODULE_PINCONNTOLATCH   starcad-21      No             - VSTOPDU        -               
 LAYOUT_MODULE_TIE              starcad-21      No             - VSTOPDU        -               
 LAYOUT_MODULE_INOUTPIN         starcad-21      No             - VSTOPDU        -               
 setup_blockfile                starcad-21      No             - VSTOPDU        -               
 MODULE_PORTS                   starcad-21      No             - RTLDU          -               
 CELL_INFO                      starcad-21      No             - RTLDULIST      -               
 TOTAL_PINPAIRS                 starcad-21      No             - FLATDU2_WL     -               
 TOTAL_GRIDS                    starcad-21      No             - FLATDU2_WL     -               
 CLOCK_DISALLOWCELL             starcad-21      No             - FLATDU2_WL     -               
 CONNECT_PAD                    starcad-21      No             - FLATDU2_WL     -               
 BLACKBOX_CHECK                 starcad-21      No             - FLATDU2_WL     -               
 MULTI_DRIVE                    starcad-21      No             - FLATDU         -               
 CHIP_PORT_NAME_LENGTH(VHDL   ) starcad-21      No             - RTLDULIST      -               
 CHIP_PORT_NAME_LENGTH(Verilog) starcad-21      No             - RTLDULIST      -               
 CHIP_MODULE_NAME_LENGTH(VHDL   ) starcad-21      No             - RTLDULIST      -               
 CHIP_MODULE_NAME_LENGTH(Verilog) starcad-21      No             - RTLDULIST      -               
 RESERVE_NAME         (VHDL   ) starcad-21      No             - RTLDULIST      -               
 RESERVE_NAME         (Verilog) starcad-21      No             - RTLDULIST      -               
 NAME_LENGTH          (VHDL   ) starcad-21      No             - RTLDULIST      -               
 NAME_LENGTH          (Verilog) starcad-21      No             - RTLDULIST      -               
 ALLOW_CELL           (VHDL   ) starcad-21      No             - RTLDULIST      -               
 ALLOW_CELL           (Verilog) starcad-21      No             - RTLDULIST      -               
 DISALLOW_CELL        (VHDL   ) starcad-21      No             - RTLDULIST      -               
 DISALLOW_CELL        (Verilog) starcad-21      No             - RTLDULIST      -               
 Mux01                          miscellaneous   No             - FLATDU2_WL     -               
 ConstSig                       miscellaneous   No             - FLATDU2_WL     -               
 DeadCode                       miscellaneous   No             - FLATDU2_WL     -               
 LongName                       miscellaneous   No             - VSTOPDU        -               
 ResourceShare                  area            No             - ALLVIEWS       -               
 GateCount                      area            No             - VSTOPDU        -               
 _close_Audits_vdb              Audits          No             - FLATDU2_WL     -               
 Audit3run                      Audits          No             - RTLDULIST      -               
 Audit3ID             (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit3ID             (Verilog) Audits          No             - RTLDULIST      -               
 AuditReportCell                Audits          No             - FLATDU2_WL     -               
 Audit2FileNameDump             Audits          No             - ELABDU         -               
 Audit4Dump                     Audits          No             - FLATDU2_WL     -               
 Audit4Count                    Audits          No             - FLATDU2_WL     -               
 Audit4ID             (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit4ID             (Verilog) Audits          No             - RTLDULIST      -               
 Audit2Stats8                   Audits          No             - RTLDULIST      -               
 Audit2Stats7b        (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2Stats7a        (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2Stats6         (Verilog) Audits          No             - LEXICAL        -               
 Audit2Stats6         (VHDL   ) Audits          No             - LEXICAL        -               
 Audit2Stats5         (Verilog) Audits          No             - LEXICAL        -               
 Audit2Stats5         (VHDL   ) Audits          No             - LEXICAL        -               
 Audit2Stats4         (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2Stats4         (Verilog) Audits          No             - RTLDULIST      -               
 Audit2Stats3         (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2Stats3         (Verilog) Audits          No             - RTLDULIST      -               
 Audit2Stats          (Verilog) Audits          No             - RTLDULIST      -               
 Audit2Stats          (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2ID             (VHDL   ) Audits          No             - RTLDULIST      -               
 Audit2ID             (Verilog) Audits          No             - RTLDULIST      -               
 _open_Audits_vdb               Audits          No             - SETUP          -               
 STARC05-2.2.2.2a     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-3.1.3.5      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.1.3     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.7.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-3.2.4.1      (VHDL   ) starc2005       No             - RTLDU          -               
 STARC05-2.1.1.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.4.8     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.4.7     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.9      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.5a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.10.13    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.10.12    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.10.11    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.10.10    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.10.9     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.6      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.2.2.2b     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.2.2.2a     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.3.1.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-3.5.6.7      (Verilog) starc2005       No             - LEXICAL        -               
 STARC05-2.10.7.1     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.5.5     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.3.7     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.1.7     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.8.3.7      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.5a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.3.2.3                starc2005       No             - FLATDU2_WL     -               
 STARC05-3.3.3.1                starc2005       No             - FLATDU2_WL     -               
 STARC05-3.3.6.2                starc2005       No             - FLATDU2_WL     -               
 STARC05-2.5.1.6                starc2005       No             - VSDU           -               
 STARC05-3.3.2.2                starc2005       No             - FLATDU2_WL     -               
 STARC05-2.10.6.6     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.6.6     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.5.1.8      (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-2.5.1.8      (Verilog) starc2005       No             - VSDU           -               
 STARC05-2.4.1.4                starc2005       No             - FLATDU2_WL     -               
 STARC05-1.4.3.6      (VHDL   ) starc2005       No             - RTLDU          -               
 STARC05-1.4.3.6      (Verilog) starc2005       No             - RTLDU          -               
 ClockEnableRace                timing          No             - FLATDU2_WL     -               
 DumpHist                       timing          No             - RTLDULIST      -               
 LogicHist                      timing          No             - FLATDU2_ABSTRACT_PRD_WL   -               
 LogicDepth                     timing          No             - FLATDU2_ABSTRACT_PRD_WL   -               
 ShiftReg                       timing          No             - FLATDU2_WL     -               
 MaxFanout                      timing          No             - FLATDU2_WL     -               
 LogNMux                        timing          No             - FLATDU2_WL     -               
 DeepMux              (VHDL   ) timing          No             - RTLDULIST      -               
 DeepMux              (Verilog) timing          No             - RTLDULIST      -               
 MixedResetEdges-ML   (VHDL   ) morelint        No             - RTLDULIST      -               
 CloseCaseWithX-ML    (VHDL   ) morelint        No             - ELABDU         -               
 SigAssignZ-ML        (VHDL   ) morelint        No             - ELABDU         -               
 SigAssignX-ML        (VHDL   ) morelint        No             - ELABDU         -               
 EntityCompMismatch-ML(VHDL   ) morelint        No             - RTLDULIST      -               
 FindStringsInComment-ML(VHDL   ) morelint        No             - RTLDULIST      -               
 CheckAssignToVecBits-ML(VHDL   ) morelint        No             - RTLDU          -               
 ConstWithoutValue-ML (VHDL   ) morelint        No             - RTLDU          -               
 GenIndexNonInt-ML    (VHDL   ) morelint        No             - RTLDU          -               
 NoFuncOrProc-ML      (VHDL   ) morelint        No             - RTLDU          -               
 SameLabelsInGenerate-ML(VHDL   ) morelint        No             - RTLDU          -               
 MultiOpInModule-ML   (VHDL   ) morelint        No             - RTLDU          -               
 ConflictVar-ML       (VHDL   ) morelint        No             - RTLDU          -               
 MultiAssign-ML       (VHDL   ) morelint        No             - RTLDULIST      -               
 DisallowVal-ML       (VHDL   ) morelint        No             - RTLDULIST      -               
 NoOpen-ML            (VHDL   ) morelint        No             - LEXICAL        -               
 ReserveNameSystemVerilog-ML(VHDL   ) morelint        No             - SETUP          -               
 ValueSizeOverFlow-ML (VHDL   ) morelint        No             - ELABDU         -               
 NestedCaseStmt-ML    (VHDL   ) morelint        No             - LEXICAL        -               
 NoOthersInAsgn-ML    (VHDL   ) morelint        No             - RTLDU          -               
 CheckSynthPragma-ML  (VHDL   ) morelint        No             - RTLDULIST      -               
 IntRange-ML          (VHDL   ) morelint        No             - RTLDULIST      -               
 ReserveNameV2K-ML    (VHDL   ) morelint        No             - SETUP          -               
 NoGenericMap-ML      (VHDL   ) morelint        No             - RTLDULIST      -               
 UnConstrLoop-ML      (VHDL   ) morelint        No             - RTLDULIST      -               
 SingleEntInFile-ML   (VHDL   ) morelint        No             - RTLDULIST      -               
 NullOthers-ML        (VHDL   ) morelint        No             - RTLDULIST      -               
 AsgnOverflow-ML      (VHDL   ) morelint        No             - ELABDU         -               
 SynchValueUsed-ML    (VHDL   ) morelint        No             - ELABDU         -               
 SetBeforeRead-ML     (VHDL   ) morelint        No             - RTLDULIST      -               
 AsgnNextSt-ML        (VHDL   ) morelint        No             - RTLDULIST      -               
 RedundantLogicalOp-ML(VHDL   ) morelint        No             - RTLDULIST      -               
 UseBusWidth-ML       (VHDL   ) morelint        No             - RTLDULIST      -               
 CondSigAsgnDelay-ML  (VHDL   ) morelint        No             - RTLDULIST      -               
 SigAsgnDelay-ML      (VHDL   ) morelint        No             - RTLDULIST      -               
 ScopedVarUsedBeforeDefine-ML(Verilog) morelint        No             - ELABDU         -               
 EnableXPropagation-ML(Verilog) morelint        No             - ELABDU         -               
 OperShortCircuit-ML  (Verilog) morelint        No             - ELABDU         -               
 NonVoidFunction-ML   (Verilog) morelint        No             - ELABDU         -               
 MultOperVar-ML       (Verilog) morelint        No             - ELABDU         -               
 DiffDelayInNonBlock-ML(Verilog) morelint        No             - RTLDULIST      -               
 UseSVCasting-ML      (Verilog) morelint        No             - ELABDU         -               
 UseSVAlways-ML       (Verilog) morelint        No             - ELABDU         -               
 NoConstSourceInAlways-ML(Verilog) morelint        No             - ELABDU         -               
 TypedefNameConflict-ML(Verilog) morelint        No             - ELABDU         -               
 AlwaysFalseTrueCond-ML(Verilog) morelint        No             - ELABDU         -               
 EnumBaseComparison-ML(Verilog) morelint        No             - ELABDU         -               
 UseLogic-ML          (Verilog) morelint        No             - ELABDU         -               
 IncludeFileForEachModule-ML(Verilog) morelint        No             - LEXICAL        -               
 CheckShiftOperator-ML(Verilog) morelint        No             - RTLDU          -               
 NoGenLabel-ML        (Verilog) morelint        No             - RTLDULIST      -               
 BitDataType-ML       (Verilog) morelint        No             - RTLDULIST      -               
 UnUsedFunctionInput-ML(Verilog) morelint        No             - ELABDU         -               
 InterfaceNameConflicts-ML(Verilog) morelint        No             - RTLDULIST      -               
 OneLineComm-ML       (Verilog) morelint        No             - SETUP          -               
 OneModule-ML         (Verilog) morelint        No             - RTLDULIST      -               
 NoVerilogPrims-ML    (Verilog) morelint        No             - RTLDULIST      -               
 PartSelectRange-ML   (Verilog) morelint        No             - LEXICAL        -               
 GenvarUsage-ML       (Verilog) morelint        No             - ELABDU         -               
 UnConstrLoop-ML      (Verilog) morelint        No             - VSTOPDU        -               
 DirectiveCheck-ML    (Verilog) morelint        No             - RTLDULIST      -               
 SigAssignZ-ML        (Verilog) morelint        No             - ELABDU         -               
 SigAssignX-ML        (Verilog) morelint        No             - ELABDU         -               
 SameLoopIndexUsed-ML (Verilog) morelint        No             - RTLDULIST      -               
 FindStringsInComment-ML(Verilog) morelint        No             - RTLDULIST      -               
 AMSKeyword-ML        (Verilog) morelint        No             - SETUP          -               
 MultiOpInModule-ML   (Verilog) morelint        No             - RTLDU          -               
 EventControlInRHS-ML (Verilog) morelint        No             - RTLDU          -               
 SignedUnsignedExpr-ML(Verilog) morelint        No             - ELABDU         -               
 SetBeforeRead-ML     (Verilog) morelint        No             - ELABDU         -               
 UnsuppCompDir-ML     (Verilog) morelint        No             - RTLDULIST      -               
 NonWireSignal-ML     (Verilog) morelint        No             - RTLDULIST      -               
 DuplicateCase-ML     (Verilog) morelint        No             - ELABDU         -               
 AlwaysCombExhaustive-ML(Verilog) morelint        No             - ELABDU         -               
 CheckSyncReset-ML    (Verilog) morelint        No             - RTLDULIST      -               
 ReserveNameSystemVerilog-ML(Verilog) morelint        No             - SETUP          -               
 CheckParamSensList-ML(Verilog) morelint        No             - RTLDULIST      -               
 CoveragePragma-ML    (Verilog) morelint        No             - RTLDULIST      -               
 CheckSynthPragma-ML  (Verilog) morelint        No             - RTLDULIST      -               
 NonStaticMacro-ML    (Verilog) morelint        No             - SETUP          -               
 BitOrder-ML          (Verilog) morelint        No             - ELABDU         -               
 ChkUndefMacro-ML     (Verilog) morelint        No             - RTLDULIST      -               
 UniqueCase-ML        (Verilog) morelint        No             - ELABDU         -               
 DuplicateCaseLabel-ML(Verilog) morelint        No             - ELABDU         -               
 MultipleFilesCellDefine-ML(Verilog) morelint        No             - SETUP          -               
 NestedCellDefine-ML  (Verilog) morelint        No             - SETUP          -               
 MultiModuleInCellDefine-ML(Verilog) morelint        No             - SETUP          -               
 SVConstruct-ML       (Verilog) morelint        No             - SETUP          -               
 V2KConstruct-ML      (Verilog) morelint        No             - SETUP          -               
 ReserveNameV2K-ML    (Verilog) morelint        No             - SETUP          -               
 EnumStateDecl-ML     (Verilog) morelint        No             - RTLDU          -               
 ParamOverrideMismatch-ML(Verilog) morelint        No             - ELABDU         -               
 NoExprInPort-ML      (Verilog) morelint        No             - RTLDULIST      -               
 NoWidthInBasedNum-ML (Verilog) morelint        No             - RTLDULIST      -               
 GroupOFAsgn-ML       (Verilog) morelint        No             - RTLDULIST      -               
 MacroFileName-ML     (Verilog) morelint        No             - RTLDULIST      -               
 FuncFileName-ML      (Verilog) morelint        No             - RTLDULIST      -               
 TaskFileName-ML      (Verilog) morelint        No             - RTLDULIST      -               
 NullPort-ML          (Verilog) morelint        No             - RTLDU          -               
 SepTFMacro-ML        (Verilog) morelint        No             - RTLDULIST      -               
 RedundantLogicalOp-ML(Verilog) morelint        No             - RTLDULIST      -               
 MemConflict-ML       (Verilog) morelint        No             - ELABDU         -               
 UseBusWidth-ML       (Verilog) morelint        No             - RTLDULIST      -               
 PartConnPort-ML      (Verilog) morelint        No             - ELABDU         -               
 AsgnToOneBit-ML      (Verilog) morelint        No             - ELABDU         -               
 DisallowTimeArr-ML   (Verilog) morelint        No             - RTLDULIST      -               
 SelfAssignment-ML    (Verilog) morelint        No             - ELABDU         -               
 SelfDeterminedExpr-ML(Verilog) morelint        No             - ELABDU         -               
 NoRealFunc-ML        (Verilog) morelint        No             - RTLDULIST      -               
 NoDisableInFunc-ML   (Verilog) morelint        No             - RTLDULIST      -               
 NoDisableInTask-ML   (Verilog) morelint        No             - RTLDULIST      -               
 NoStrengthInput-ML   (Verilog) morelint        No             - RTLDULIST      -               
 NoArray-ML           (Verilog) morelint        No             - RTLDU          -               
 NoParamMultConcat-ML (Verilog) morelint        No             - RTLDULIST      -               
 NoSigCaseX-ML        (Verilog) morelint        No             - RTLDULIST      -               
 DisallowXInCaseZ-ML  (Verilog) morelint        No             - ELABDU         -               
 DisallowCaseZ-ML     (Verilog) morelint        No             - ELABDU         -               
 DisallowCaseX-ML     (Verilog) morelint        No             - ELABDU         -               
 InterfaceWithoutModport-ML(Verilog) morelint        No             - RTLDULIST      -               
 UnpackedStructUsed-ML(Verilog) morelint        No             - RTLDULIST      -               
 LogicEnumBase-ML     (Verilog) morelint        No             - RTLDULIST      -               
 TwoStateData-ML      (Verilog) morelint        No             - RTLDULIST      -               
 NestedCaseStmt-ML    (Verilog) morelint        No             - LEXICAL        -               
 ChkSensExprPar-ML    (Verilog) morelint        No             - LEXICAL        -               
 DiffTimescaleUsed-ML (Verilog) morelint        No             - RTLDULIST      -               
 UniqueInputOutputSampling-ML   morelint        No             - FLATDU2_WL     -               
 NoTopCombPath-ML               morelint        No             - FLATDU2_WL     -               
 IfOverlap-ML         (VHDL   ) morelint        No             - ELABDU         -               
 IfOverlap-ML         (Verilog) morelint        No             - ELABDU         -               
 ConstDrivenNet-ML    (VHDL   ) morelint        No             - RTLDULIST      -               
 ConstDrivenNet-ML    (Verilog) morelint        No             - RTLDULIST      -               
 SynthElabDuName-ML             morelint        No             - ELABDU         -               
 RptNegEdgeFF-ML                morelint        No             - FLATDU2_WL     -               
 HangingFlopOutput-ML           morelint        No             - VSTOPDU        -               
 PortRange-ML                   morelint        No             - FLATDU2_WL     -               
 UnUsedFlopOutput-ML            morelint        No             - FLATDU2_WL     -               
 MaxFanoutCount-ML              morelint        No             - FLATDU2_WL     -               
 UnInitTopDuParam-ML  (VHDL   ) morelint        No             - RTLDULIST      -               
 UnInitTopDuParam-ML  (Verilog) morelint        No             - RTLDULIST      -               
 UnInitParam-ML       (VHDL   ) morelint        No             - RTLDULIST      -               
 UnInitParam-ML       (Verilog) morelint        No             - RTLDULIST      -               
 HierarchicalModule-ML          morelint        No             - VSDU           -               
 SameDu-ML                      morelint        No             - RTLDULIST      -               
 DetectBlackBoxes-ML            morelint        No             - FLATDU2_WL     -               
 UndrivenOutTermNLoaded-ML      morelint        No             - VSTOPDU        -               
 ExoticClock-ML                 morelint        No             - FLATDU2_WL     -               
 SameControlNDataNet-ML         morelint        No             - FLATDU2_WL     -               
 SetResetConverge-ML            morelint        No             - FLATDU2_WL     -               
 NonConstReset-ML     (VHDL   ) morelint        No             - ELABDU         -               
 NonConstReset-ML     (Verilog) morelint        No             - ELABDU         -               
 UnrecSynthDir-ML     (VHDL   ) morelint        No             - RTLDULIST      -               
 UnrecSynthDir-ML     (Verilog) morelint        No             - RTLDULIST      -               
 NoArithOp-ML         (VHDL   ) morelint        No             - RTLDULIST      -               
 NoArithOp-ML         (Verilog) morelint        No             - RTLDULIST      -               
 ComplexExpr-ML       (VHDL   ) morelint        No             - RTLDULIST      -               
 ComplexExpr-ML       (Verilog) morelint        No             - ELABDU         -               
 CAPA-ML              (VHDL   ) morelint        No             - LEXICAL        -               
 CAPA-ML              (Verilog) morelint        No             - LEXICAL        -               
 RegInput-ML                    morelint        No             - FLATDU2_WL     -               
 ChkCarriageReturn-ML (VHDL   ) morelint        No             - LEXICAL        -               
 ChkCarriageReturn-ML (Verilog) morelint        No             - LEXICAL        -               
 ConstantInput-ML               morelint        No             - VSDU           -               
 WrapInstance-ML      (VHDL   ) morelint        No             - RTLDU          -               
 WrapInstance-ML      (Verilog) morelint        No             - RTLDU          -               
 SensListRepeat-ML    (VHDL   ) morelint        No             - ELABDU         -               
 SensListRepeat-ML    (Verilog) morelint        No             - ELABDU         -               
 IfWithoutElse-ML     (VHDL   ) morelint        No             - ELABDU         -               
 IfWithoutElse-ML     (Verilog) morelint        No             - ELABDU         -               
 NoFeedThrus-ML                 morelint        No             - VSTOPDU        -               
 InlineComment-ML     (VHDL   ) morelint        No             - LEXICAL        -               
 InlineComment-ML     (Verilog) morelint        No             - LEXICAL        -               
 NoBusPartClock-ML              morelint        No             - FLATDU2_WL     -               
 DisallowDWComp-ML    (VHDL   ) morelint        No             - ELABDU         -               
 DisallowDWComp-ML    (Verilog) morelint        No             - RTLDULIST      -               
 DisallowMult-ML      (VHDL   ) morelint        No             - ELABDU         -               
 DisallowMult-ML      (Verilog) morelint        No             - ELABDU         -               
 ReEntrantOutput-ML             morelint        No             - VSDU           -               
 ResetFlop-ML                   morelint        No             - VSDU           -               
 SynchReset-ML        (VHDL   ) morelint        No             - RTLDULIST      -               
 SynchReset-ML        (Verilog) morelint        No             - RTLDULIST      -               
 NoInoutPort-ML       (Verilog) morelint        No             - ELABDU         -               
 NoInoutPort-ML       (VHDL   ) morelint        No             - ELABDU         -               
 NoBitArray-ML        (VHDL   ) morelint        No             - ELABDU         -               
 NoBitArray-ML        (Verilog) morelint        No             - ELABDU         -               
 ModuleName-ML        (VHDL   ) morelint        No             - RTLDULIST      -               
 ModuleName-ML        (Verilog) morelint        No             - RTLDULIST      -               
 HangingInst-ML                 morelint        No             - VSDU           -               
 HangingInstOutput-ML           morelint        No             - VSDU           -               
 DirectTopInputToInout-ML       morelint        No             - VSTOPDU        -               
 HangingInstInput-ML            morelint        No             - VSTOPDU        -               
 UndrivenNUnloaded-ML           morelint        No             - VSTOPDU        -               
 UnloadedNet-ML                 morelint        No             - VSTOPDU        -               
 UnloadedOutTerm-ML             morelint        No             - VSTOPDU        -               
 UnloadedInPort-ML              morelint        No             - VSTOPDU        -               
 UndrivenNet-ML                 morelint        No             - VSTOPDU        -               
 UndrivenOutPort-ML             morelint        No             - VSTOPDU        -               
 TristateSig-ML                 morelint        No             - VSDU           -               
 TristatePort-ML                morelint        No             - VSDU           -               
 MergeFlops-ML                  morelint        No             - FLATDU2_WL     -               
 ResetPreventSRL-ML             morelint        No             - FLATDU2_WL     -               
 UseSRLPrim-ML                  morelint        No             - FLATDU2_WL     -               
 W429L                (Verilog) latch           No             - VSDU           -               
 W428L                (Verilog) latch           No             - VSDU           -               
 W442bL               (Verilog) latch           No             - VSDU           -               
 W442aL               (Verilog) latch           No             - VSDU           -               
 W122L                (Verilog) latch           No             - VSDU           -               
 W336L                (Verilog) latch           No             - ALLVIEWS       -               
 W422L                (Verilog) latch           No             - FLATDU2_WL     -               
 W449L                (Verilog) latch           No             - VSDU           -               
 W392bL                         latch           No             - FLATDU2_WL     -               
 W392aL                         latch           No             - FLATDU2_WL     -               
 LatchReset                     latch           No             - FLATDU2_WL     -               
 GatedReset                     latch           No             - FLATDU2_WL     -               
 LatchGatedClock                latch           No             - FLATDU2_WL     -               
 ClockEdges                     latch           No             - FLATDU2_WL     -               
 LINT_blksgdc01                 lint            No             - FLATDU2_PRD_WL   -               
 W120                 (VHDL   ) lint            No             - ELABDU         -               
 W120                 (Verilog) lint            No             - ELABDU         -               
 LINT_sca_validation            lint            No             - FLATDU2_ABSTRACT_WL   -               
 LINT_abstract01                lint            No             - FLATDU2_WL     -               
 W448                           lint            No             - FLATDU2_WL     -               
 W401                           lint            No             - FLATDU2_WL     -               
 W395                 (Verilog) lint            No             - ELABDU         -               
 W395                 (VHDL   ) lint            No             - RTLDULIST      -               
 W391                           lint            No             - FLATDU2_WL     -               
 W18                            lint            No             - VSTOPDU        -               
 W495                 (VHDL   ) lint            No             - ELABDU         -               
 W495                 (Verilog) lint            No             - ELABDU         -               
 W494                 (VHDL   ) lint            No             - ELABDU         -               
 W494                 (Verilog) lint            No             - ELABDU         -               
 W490                 (VHDL   ) lint            No             - RTLDULIST      -               
 W490                 (Verilog) lint            No             - ELABDU         -               
 W444                 (VHDL   ) lint            No             - RTLDULIST      -               
 W444                 (Verilog) lint            No             - ELABDU         -               
 W443                 (VHDL   ) lint            No             - RTLDULIST      -               
 W443                 (Verilog) lint            No             - ELABDU         -               
 W425                 (VHDL   ) lint            No             - RTLDULIST      -               
 W425                 (Verilog) lint            No             - ELABDU         -               
 W351                 (VHDL   ) lint            No             - RTLDULIST      -               
 W351                 (Verilog) lint            No             - RTLDULIST      -               
 W345                 (VHDL   ) lint            No             - SETUP          -               
 W345                 (Verilog) lint            No             - RTLDULIST      -               
 W287c                (VHDL   ) lint            No             - VSDU           -               
 W287c                (Verilog) lint            No             - ELABDU         -               
 W257                 (VHDL   ) lint            No             - SETUP          -               
 W257                 (Verilog) lint            No             - RTLDULIST      -               
 W241                 (VHDL   ) lint            No             - ELABDU         -               
 W241                 (Verilog) lint            No             - ELABDU         -               
 W210                 (VHDL   ) lint            No             - ELABDU         -               
 W210                 (Verilog) lint            No             - RTLDULIST      -               
 W191                 (VHDL   ) lint            No             - RTLDULIST      -               
 W191                 (Verilog) lint            No             - ELABDU         -               
 W190                 (VHDL   ) lint            No             - RTLDULIST      -               
 W190                 (Verilog) lint            No             - ELABDU         -               
 W187                 (VHDL   ) lint            No             - SETUP          -               
 W187                 (Verilog) lint            No             - ELABDU         -               
 W175                 (VHDL   ) lint            No             - RTLDULIST      -               
 W175                 (Verilog) lint            No             - RTLDULIST      -               
 W167                 (VHDL   ) lint            No             - RTLDULIST      -               
 W167                 (Verilog) lint            No             - RTLDULIST      -               
 W164b                (VHDL   ) lint            No             - ELABDU         -               
 W164b                (Verilog) lint            No             - ELABDU         -               
 W164a                (VHDL   ) lint            No             - ELABDU         -               
 W164a                (Verilog) lint            No             - ELABDU         -               
 W146                 (VHDL   ) lint            No             - SETUP          -               
 W146                 (Verilog) lint            No             - RTLDULIST      -               
 W128                 (VHDL   ) lint            No             - SETUP          -               
 W128                 (Verilog) lint            No             - RTLDULIST      -               
 W111                 (VHDL   ) lint            No             - ELABDU         -               
 W111                 (Verilog) lint            No             - ELABDU         -               
 W493                 (VHDL   ) lint            No             - RTLDULIST      -               
 W493                 (Verilog) lint            No             - SETUP          -               
 W17                  (VHDL   ) lint            No             - ELABDU         -               
 W17                  (Verilog) lint            No             - ELABDU         -               
 W402                 (VHDL   ) lint            No             - FLATDU2_WL     -               
 PhysicalTypes        (VHDL   ) lint            No             - SETUP          -               
 W86                  (VHDL   ) lint            No             - ELABDU         -               
 W526                 (VHDL   ) lint            No             - RTLDULIST      -               
 W501                 (VHDL   ) lint            No             - ELABDU         -               
 W500                 (VHDL   ) lint            No             - ELABDU         -               
 W494b                (VHDL   ) lint            No             - ELABDU         -               
 W494a                (VHDL   ) lint            No             - ELABDU         -               
 W488                 (VHDL   ) lint            No             - ELABDU         -               
 W464                 (VHDL   ) lint            No             - RTLDULIST      -               
 W456a                (VHDL   ) lint            No             - ELABDU         -               
 W456                 (VHDL   ) lint            No             - ELABDU         -               
 W43                  (VHDL   ) lint            No             - RTLDULIST      -               
 W396                 (VHDL   ) lint            No             - VSDU           -               
 W259                 (VHDL   ) lint            No             - ELABDU         -               
 W226                 (VHDL   ) lint            No             - RTLDULIST      -               
 ClockStyle           (VHDL   ) lint            No             - RTLDULIST      -               
 W489                 (VHDL   ) lint            No             - RTLDULIST      -               
 W242                 (VHDL   ) lint            No             - RTLDULIST      -               
 SynthIfStmt          (VHDL   ) lint            No             - RTLDULIST      -               
 InitPorts            (VHDL   ) lint            No             - RTLDULIST      -               
 NoTimeOut            (VHDL   ) lint            No             - SETUP          -               
 MultipleWait         (VHDL   ) lint            No             - RTLDULIST      -               
 ArrayEnumIndex       (VHDL   ) lint            No             - SETUP          -               
 PortType             (VHDL   ) lint            No             - SETUP          -               
 ResFunction          (VHDL   ) lint            No             - SETUP          -               
 PreDefAttr           (VHDL   ) lint            No             - SETUP          -               
 UserDefAttr          (VHDL   ) lint            No             - SETUP          -               
 AllocExpr            (VHDL   ) lint            No             - SETUP          -               
 LinkagePort          (VHDL   ) lint            No             - SETUP          -               
 DisconnSpec          (VHDL   ) lint            No             - SETUP          -               
 IncompleteType       (VHDL   ) lint            No             - SETUP          -               
 LoopBound            (VHDL   ) lint            No             - SETUP          -               
 BothPhase            (VHDL   ) lint            No             - RTLDULIST      -               
 ForLoopWait          (VHDL   ) lint            No             - SETUP          -               
 WhileInSubProg       (VHDL   ) lint            No             - RTLDULIST      -               
 IntGeneric           (VHDL   ) lint            No             - SETUP          -               
 SigVarInit           (VHDL   ) lint            No             - RTLDULIST      -               
 AssertStmt           (VHDL   ) lint            No             - SETUP          -               
 EntityStmt           (VHDL   ) lint            No             - SETUP          -               
 W397                 (VHDL   ) lint            No             - SETUP          -               
 W164c                (Verilog) lint            No             - ELABDU         -               
 W402b                (Verilog) lint            No             - FLATDU2_WL     -               
 W402a                (Verilog) lint            No             - RTLDU          -               
 W323                 (Verilog) lint            No             - FLATDU2_WL     -               
 W541                 (Verilog) lint            No             - VSDU           -               
 W438                 (Verilog) lint            No             - VSDU           -               
 W428                 (Verilog) lint            No             - VSDU           -               
 W701                 (Verilog) lint            No             - RTLDULIST      -               
 W576                 (Verilog) lint            No             - ELABDU         -               
 W575                 (Verilog) lint            No             - ELABDU         -               
 W563                 (Verilog) lint            No             - ELABDU         -               
 W551                 (Verilog) lint            No             - ELABDU         -               
 W529                 (Verilog) lint            No             - RTLDULIST      -               
 W527                 (Verilog) lint            No             - RTLDULIST      -               
 W526                 (Verilog) lint            No             - RTLDULIST      -               
 W208                 (Verilog) lint            No             - SETUP          -               
 W189                 (Verilog) lint            No             - RTLDULIST      -               
 W504                 (Verilog) lint            No             - ELABDU         -               
 W503                 (Verilog) lint            No             - RTLDULIST      -               
 W498                 (Verilog) lint            No             - ELABDU         -               
 W497                 (Verilog) lint            No             - ELABDU         -               
 W491                 (Verilog) lint            No             - ELABDU         -               
 W489                 (Verilog) lint            No             - ELABDU         -               
 W484                 (Verilog) lint            No             - ELABDU         -               
 W479                 (Verilog) lint            No             - RTLDULIST      -               
 W477                 (Verilog) lint            No             - RTLDULIST      -               
 W476                 (Verilog) lint            No             - RTLDULIST      -               
 W475                 (Verilog) lint            No             - RTLDULIST      -               
 W474                 (Verilog) lint            No             - RTLDULIST      -               
 W468                 (Verilog) lint            No             - ELABDU         -               
 W464                 (Verilog) lint            No             - RTLDULIST      -               
 W446                 (Verilog) lint            No             - ELABDU         -               
 W433                 (Verilog) lint            No             - RTLDULIST      -               
 W430                 (Verilog) lint            No             - RTLDULIST      -               
 W427                 (Verilog) lint            No             - RTLDULIST      -               
 W423                 (Verilog) lint            No             - ELABDU         -               
 W373                 (Verilog) lint            No             - RTLDULIST      -               
 W372                 (Verilog) lint            No             - RTLDULIST      -               
 W350                 (Verilog) lint            No             - RTLDULIST      -               
 W346                 (Verilog) lint            No             - RTLDULIST      -               
 W343                 (Verilog) lint            No             - ELABDU         -               
 W342                 (Verilog) lint            No             - ELABDU         -               
 W341                 (Verilog) lint            No             - ELABDU         -               
 W333                 (Verilog) lint            No             - RTLDULIST      -               
 W332                 (Verilog) lint            No             - ELABDU         -               
 W316                 (Verilog) lint            No             - ELABDU         -               
 W314                 (Verilog) lint            No             - ELABDU         -               
 W313                 (Verilog) lint            No             - RTLDULIST      -               
 W312                 (Verilog) lint            No             - RTLDULIST      -               
 W311                 (Verilog) lint            No             - RTLDULIST      -               
 W310                 (Verilog) lint            No             - RTLDULIST      -               
 W309                 (Verilog) lint            No             - RTLDULIST      -               
 W308                 (Verilog) lint            No             - RTLDULIST      -               
 W307                 (Verilog) lint            No             - RTLDULIST      -               
 W306                 (Verilog) lint            No             - RTLDULIST      -               
 W280                 (Verilog) lint            No             - RTLDULIST      -               
 W256                 (Verilog) lint            No             - RTLDULIST      -               
 W254                 (Verilog) lint            No             - RTLDULIST      -               
 W253                 (Verilog) lint            No             - RTLDULIST      -               
 W250                 (Verilog) lint            No             - RTLDULIST      -               
 W245                 (Verilog) lint            No             - ELABDU         -               
 W243                 (Verilog) lint            No             - RTLDULIST      -               
 W238                 (Verilog) lint            No             - ELABDU         -               
 W226                 (Verilog) lint            No             - ELABDU         -               
 W213                 (Verilog) lint            No             - RTLDULIST      -               
 W193                 (Verilog) lint            No             - RTLDULIST      -               
 W192                 (Verilog) lint            No             - RTLDULIST      -               
 W188                 (Verilog) lint            No             - RTLDULIST      -               
 W171                 (Verilog) lint            No             - ELABDU         -               
 W162                 (Verilog) lint            No             - ELABDU         -               
 W159                 (Verilog) lint            No             - ELABDU         -               
 W154                 (Verilog) lint            No             - RTLDULIST      -               
 W129                 (Verilog) lint            No             - RTLDULIST      -               
 W127                 (Verilog) lint            No             - RTLDULIST      -               
 W126                 (Verilog) lint            No             - RTLDULIST      -               
 W121                 (Verilog) lint            No             - RTLDULIST      -               
 W107                 (Verilog) lint            No             - ELABDU         -               
 W88                  (Verilog) lint            No             - ELABDU         -               
 W69                  (Verilog) lint            No             - ELABDU         -               
 W553                 (Verilog) lint            No             - ELABDU         -               
 W552                 (Verilog) lint            No             - ELABDU         -               
 W488                 (Verilog) lint            No             - ELABDU         -               
 W456a                (Verilog) lint            No             - ELABDU         -               
 W456                 (Verilog) lint            No             - ELABDU         -               
 W429                 (Verilog) lint            No             - ELABDU         -               
 W328                 (Verilog) lint            No             - ELABDU         -               
 W294                 (Verilog) lint            No             - RTLDULIST      -               
 W163                 (Verilog) lint            No             - ELABDU         -               
 W34                  (Verilog) lint            No             - RTLDULIST      -               
 W239                 (Verilog) lint            No             - ELABDU         -               
 infiniteloop         (Verilog) lint            No             - SETUP          -               
 readclock            (Verilog) lint            No             - SETUP          -               
 W561                 (Verilog) lint            No             - SETUP          -               
 W546                 (Verilog) lint            No             - SETUP          -               
 W453                 (Verilog) lint            No             - ELABDU         -               
 W182n                (Verilog) lint            No             - SETUP          -               
 W182k                (Verilog) lint            No             - SETUP          -               
 W182h                (Verilog) lint            No             - SETUP          -               
 W182g                (Verilog) lint            No             - SETUP          -               
 W182c                (Verilog) lint            No             - RTLDULIST      -               
 W348                 (Verilog) lint            No             - SETUP          -               
 W326                 (Verilog) lint            No             - SETUP          -               
 W295                 (Verilog) lint            No             - RTLDULIST      -               
 W143                 (Verilog) lint            No             - SETUP          -               
 VerilintPragma       (Verilog) lint            No             - RTLDULIST      -               
 sim_loop01           (Verilog) simulation      No             - RTLDULIST      -               
 sim_race08           (Verilog) simulation      No             - FLATDU2_WL     -               
 sim_race07           (Verilog) simulation      No             - ALLVIEWS       -               
 sim_race06           (Verilog) simulation      No             - ALLVIEWS       -               
 sim_race03           (Verilog) simulation      No             - ALLVIEWS       -               
 sim_race05           (Verilog) simulation      No             - RTLDULIST      -               
 sim_race04           (Verilog) simulation      No             - RTLDU          -               
 sim_race11           (Verilog) simulation      No             - ALLVIEWS       -               
 sim_race01           (Verilog) simulation      No             - RTLDU          -               
 pwrdnPinConnToSeqOrIOCells     erc             No             - FLATDU2_WL     -               
 elementsAllowedPerScanChain    erc             No             - FLATDU2_WL     -               
 delayLineDependentCkt          erc             No             - FLATDU2_WL     -               
 noCombinatorialFeedBack        erc             No             - FLATDU2_WL     -               
 setPinConnectedToSetNet        erc             No             - FLATDU2_WL     -               
 resetPinConnectedToResetNet    erc             No             - FLATDU2_WL     -               
 clockPinsConnectedToClkNets    erc             No             - FLATDU2_WL     -               
 listTristateBuses              erc             No             - FLATDU2_WL     -               
 checkTristateBuses             erc             No             - FLATDU2_WL     -               
 checkOPPinConnectedToNet_b     erc             No             - FLATDU2_WL     -               
 checkOPPinConnectedToNet_a     erc             No             - FLATDU2_WL     -               
 checkIOPinConnectedToNet       erc             No             - FLATDU2_WL     -               
 checkMultipleDrivers           erc             No             - FLATDU2_WL     -               
 checkNetReceiver               erc             No             - FLATDU2_WL     -               
 checkNetDriver                 erc             No             - FLATDU2_WL     -               
 Underload                      erc             No             - FLATDU2_WL     -               
 NearOverload                   erc             No             - FLATDU2_WL     -               
 Overload                       erc             No             - FLATDU2_WL     -               
 OutNotUsed                     erc             No             - FLATDU2_WL     -               
 NoContAssign         (Verilog) erc             No             - RTLDULIST      -               
 MuxSelConst                    erc             No             - FLATDU2_WL     -               
 TristateConst                  erc             No             - FLATDU2_WL     -               
 DisabledOr                     erc             No             - FLATDU2_WL     -               
 DisabledAnd                    erc             No             - FLATDU2_WL     -               
 LatchDataX                     erc             No             - FLATDU2_WL     -               
 LatchDataConstant              erc             No             - FLATDU2_WL     -               
 LatchDataUndriven              erc             No             - FLATDU2_WL     -               
 LatchEnableX                   erc             No             - FLATDU2_WL     -               
 LatchEnableConstant            erc             No             - FLATDU2_WL     -               
 LatchEnableUndriven            erc             No             - FLATDU2_WL     -               
 FlopSR                         erc             No             - FLATDU2_WL     -               
 FlopSREX                       erc             No             - FLATDU2_WL     -               
 FlopDataX                      erc             No             - FLATDU2_WL     -               
 FlopDataConstant               erc             No             - FLATDU2_WL     -               
 FlopDataUndriven               erc             No             - FLATDU2_WL     -               
 FlopClockX                     erc             No             - FLATDU2_WL     -               
 FlopClockUndriven              erc             No             - FLATDU2_WL     -               
 FloatingInputs                 erc             No             - FLATDU2_WL     -               
 erc_Prereq                     erc             No             - FLATDU2_WL     -               
 STARC05-1.3.1.7                starc2005       No             - FLATDU2_WL     -               
 STARC05-3.3.1.4b               starc2005       No             - FLATDU2_WL     -               
 STARC05-3.5.6.6                starc2005       No             - LEXICAL        -               
 STARC05-3.1.3.3v     (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-3.1.3.3      (Verilog) starc2005       No             - VSDU           -               
 STARC05-3.1.3.2vc    (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-3.1.3.2vb    (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-3.1.3.2va    (VHDL   ) starc2005       No             - FLATDU2_WL     -               
 STARC05-3.1.3.2b     (Verilog) starc2005       No             - VSDU           -               
 STARC05-3.1.3.2a     (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC05-2.5.1.5a     (VHDL   ) starc2005       No             - FLATDU2_WL     -               
 STARC05-2.5.1.5a     (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC05-2.5.1.1      (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-2.5.1.1      (Verilog) starc2005       No             - VSDU           -               
 STARC05-2.3.1.7a               starc2005       No             - VSDU           -               
 STARC05-2.2.1.2      (VHDL   ) starc2005       No             - VSTOPDU        -               
 STARC05-2.2.1.2      (Verilog) starc2005       No             - VSTOPDU        -               
 STARC05-1.6.3.2                starc2005       No             - FLATDU2_WL     -               
 STARC05-1.6.3.1                starc2005       No             - FLATDU2_WL     -               
 STARC05-1.6.2.2a               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.6.1.2                starc2005       No             - FLATDU2_WL     -               
 STARC05-1.6.1.1b               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.6.1.1a               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.4.3.1b               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.4.3.1a               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.3.2.1b     (VHDL   ) starc2005       No             - FLATDU2_WL     -               
 STARC05-1.3.2.1b     (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC05-1.1.5.4      (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-1.1.5.4      (Verilog) starc2005       No             - VSDU           -               
 STARC05-1.1.5.2b               starc2005       No             - FLATDU2_WL     -               
 STARC05-1.1.5.1      (VHDL   ) starc2005       No             - VSDU           -               
 STARC05-1.1.5.1      (Verilog) starc2005       No             - VSDU           -               
 STARC05-1.1.4.6b               starc2005       No             - VSDU           -               
 STARC05-1.1.4.6a               starc2005       No             - VSDU           -               
 STARC05-3.5.6.2vb    (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-3.5.6.2va    (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-3.5.2.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-3.2.3.1v     (VHDL   ) starc2005       No             - SETUP          -               
 STARC05-3.2.2.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-3.1.5.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-3.1.4.2      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-2.11.1.4     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.11.1.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.8.3     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.8.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.8.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.6.5     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.10.5.3     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.5.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.5.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.4.6v    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.4.4     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.10.3.1v    (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.10.1.8     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.10.1.5     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.1.4v    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.9.2.3      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.8.3.6      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.8.3.4b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.8.3.4a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.8.3.2      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.8.2.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.8.2.1      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.8.1.3      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.7.3.1c     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.3.1b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.3.1a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.2.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.2.2      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.6.2.2      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.6.1.4b     (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-2.6.1.4a     (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-2.6.1.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.5.1.5b     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-2.3.6.2b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.6.2a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.2vc    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.2vb    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.2va    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.7b     (VHDL   ) starc2005       No             - RTLDU          -               
 STARC05-2.3.2.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.2.2.3v     (VHDL   ) starc2005       No             - RTLDU          -               
 STARC05-2.1.6.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.5.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.4.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.3.4v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.3.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.5v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.4v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.3v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.1.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.1.1v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.9v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.8v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.4v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.3v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.6.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.2v     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.1va    (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC05-1.1.3.3d     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3c     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.2.1b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.2.1a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9d     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9c     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.8v     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-1.1.1.7      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.6v     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC05-1.1.1.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.3va    (VHDL   ) starc2005       No             - SETUP          -               
 STARC05-2.10.3.2b_sb (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.3.2b_sa (Verilog) starc2005       No             - ELABDU         -               
 STARC05-3.5.6.2      (Verilog) starc2005       No             - LEXICAL        -               
 STARC05-3.5.2.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.2.3.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.2.2.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.2.2.2b     (Verilog) starc2005       No             - LEXICAL        -               
 STARC05-3.2.2.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.1.5.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-3.1.4.2      (Verilog) starc2005       No             - LEXICAL        -               
 STARC05-2.11.1.4     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.11.1.2     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.8.3     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.8.2     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.8.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.6.5     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.5.3     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.5.2     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.10.5.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.4.6     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.4.5     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.4.1     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.10.3.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.1.8     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.10.1.6     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.10.1.4c    (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.9.2.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.9.1.2e     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.8.3.6      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.8.3.4b     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.8.3.4a     (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.8.3.3      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.8.3.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.8.2.2      (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.8.2.1      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.8.1.3      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.7.4.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.3.1c     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.7.3.1b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.3.1a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.2.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.7.2.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.6.2.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.6.1.4b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.6.1.4a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.6.1.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.6.2b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.6.2a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.4.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.2.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.3.1.2b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.3.1.2a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.2.2.3b     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.2.2.3a     (Verilog) starc2005       No             - RTLDU          -               
 STARC05-2.1.6.1      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.5.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.4.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.3.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.2.5      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.2.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.2.3      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.2.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.2.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-2.1.1.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC05-2.1.1.1      (Verilog) starc2005       No             - VSDU           -               
 STARC05-1.1.4.9      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.8      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.4      (Verilog) starc2005       No             - LEXICAL        -               
 STARC05-1.1.4.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.2b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.2a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.4.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3e     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3d     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3c     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.3.3a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.2.1b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.2.1a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9d     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9c     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.9a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.8      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.7      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.6      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC05-1.1.1.3      (Verilog) starc2005       No             - SETUP          -               
 STARC-2.10.1.5c      (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.10.1.5c      (Verilog) starc           No             - ELABDU         -               
 STARC-3.1.3.2c       (VHDL   ) starc           No             - ELABDU         -               
 STARC-3.1.3.2b                 starc           No             - VSDU           -               
 STARC-3.1.3.2a                 starc           No             - FLATDU2_WL     -               
 STARC-3.3.2.3                  starc           No             - FLATDU2_WL     -               
 STARC-3.3.2.2b                 starc           No             - FLATDU2_WL     -               
 STARC05-3.3.1.4a               starc2005       No             - FLATDU2_WL     -               
 STARC-3.3.2.2a                 starc           No             - FLATDU2_WL     -               
 STARC05-3.3.1.1                starc2005       No             - FLATDU2_WL     -               
 STARC-3.1.4.5        (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-3.1.4.5      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-3.1.4.5        (Verilog) starc           No             - LEXICAL        -               
 STARC05-3.1.4.5      (Verilog) starc2005       No             - LEXICAL        -               
 STARC-2.3.6.1                  starc           No             - VSDU           -               
 STARC05-2.3.6.1                starc2005       No             - VSDU           -               
 STARC-2.5.2.1                  starc           No             - FLATDU2_WL     -               
 STARC05-2.5.2.1                starc2005       No             - FLATDU2_WL     -               
 STARC-2.5.1.4                  starc           No             - FLATDU2_WL     -               
 STARC05-2.5.1.4                starc2005       No             - FLATDU2_WL     -               
 STARC-2.3.5.1                  starc           No             - FLATDU2_WL     -               
 STARC05-2.3.5.1                starc2005       No             - FLATDU2_WL     -               
 STARC-2.3.4.3                  starc           No             - FLATDU2_WL     -               
 STARC-2.3.3.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.3.2b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.3.3.3        (Verilog) starc           No             - RTLDU          -               
 STARC05-2.3.3.2b     (Verilog) starc2005       No             - RTLDU          -               
 STARC-1.6.3.2                  starc           No             - FLATDU2_WL     -               
 STARC-1.6.3.1                  starc           No             - FLATDU2_WL     -               
 STARC-1.6.2.2a                 starc           No             - FLATDU2_WL     -               
 STARC-1.6.2.2                  starc           No             - FLATDU2_WL     -               
 STARC05-1.6.2.2                starc2005       No             - FLATDU2_WL     -               
 STARC-1.6.1.2                  starc           No             - FLATDU2_WL     -               
 STARC-1.6.1.1                  starc           No             - FLATDU2_WL     -               
 STARC-1.5.1.5                  starc           No             - FLATDU2_WL     -               
 STARC-1.5.1.2                  starc           No             - FLATDU2_WL     -               
 STARC05-1.5.1.2                starc2005       No             - FLATDU2_WL     -               
 STARC-1.5.1.1                  starc           No             - FLATDU2_WL     -               
 STARC05-1.5.1.1                starc2005       No             - FLATDU2_WL     -               
 STARC-1.4.3.4                  starc           No             - FLATDU2_WL     -               
 STARC-1.4.3.2                  starc           No             - FLATDU2_WL     -               
 STARC05-1.4.3.2                starc2005       No             - FLATDU2_WL     -               
 STARC-1.4.3.1b                 starc           No             - FLATDU2_WL     -               
 STARC05-1.4.3.1c               starc2005       No             - FLATDU2_WL     -               
 STARC-1.4.3.1a                 starc           No             - FLATDU2_WL     -               
 STARC-1.4.1.1                  starc           No             - FLATDU2_WL     -               
 STARC05-1.4.1.1                starc2005       No             - FLATDU2_WL     -               
 STARC-1.3.3.4                  starc           No             - FLATDU2_WL     -               
 STARC-1.3.2.2                  starc           No             - FLATDU2_WL     -               
 STARC05-1.3.2.2                starc2005       No             - FLATDU2_WL     -               
 STARC-1.3.2.1                  starc           No             - FLATDU2_WL     -               
 STARC05-1.3.2.1a               starc2005       No             - FLATDU2_WL     -               
 STARC-1.3.1.7                  starc           No             - FLATDU2_WL     -               
 STARC-1.3.1.6                  starc           No             - FLATDU2_WL     -               
 STARC05-1.3.1.6                starc2005       No             - FLATDU2_WL     -               
 STARC-1.3.1.3a                 starc           No             - FLATDU2_WL     -               
 STARC-1.3.1.3                  starc           No             - FLATDU2_WL     -               
 STARC-1.2.1.3                  starc           No             - FLATDU2_WL     -               
 STARC05-1.2.1.3                starc2005       No             - FLATDU2_WL     -               
 STARC-1.2.1.2                  starc           No             - FLATDU2_WL     -               
 STARC-1.2.1.1b                 starc           No             - FLATDU2_WL     -               
 STARC05-1.2.1.1b               starc2005       No             - FLATDU2_WL     -               
 STARC-1.2.1.1a                 starc           No             - FLATDU2_WL     -               
 STARC05-1.2.1.1a               starc2005       No             - FLATDU2_WL     -               
 STARC-2.5.1.2                  starc           No             - FLATDU2_WL     -               
 STARC-2.5.1.1                  starc           No             - VSDU           -               
 STARC-2.4.1.2                  starc           No             - VSDU           -               
 STARC05-2.4.1.2                starc2005       No             - VSDU           -               
 STARC-2.2.1.3                  starc           No             - VSTOPDU        -               
 STARC-1.6.2.1                  starc           No             - VSDU           -               
 STARC05-1.6.2.1                starc2005       No             - VSDU           -               
 Prereqs_STARC-1.6.2.1          starc           No             - RTLDULIST      -               
 Prereqs_STARC05-1.6.2.1        starc2005       No             - RTLDULIST      -               
 STARC-1.1.5.4        (VHDL   ) starc           No             - VSDU           -               
 STARC-1.1.5.4        (Verilog) starc           No             - VSDU           -               
 STARC-1.1.5.3        (VHDL   ) starc           No             - VSDU           -               
 STARC05-1.1.5.3      (VHDL   ) starc2005       No             - VSDU           -               
 STARC-1.1.5.3        (Verilog) starc           No             - VSDU           -               
 STARC05-1.1.5.3      (Verilog) starc2005       No             - VSDU           -               
 STARC-1.1.5.1        (VHDL   ) starc           No             - VSDU           -               
 STARC-1.1.5.1        (Verilog) starc           No             - VSDU           -               
 STARC-1.1.2.1b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.2.1b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.5.6.3b       (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-3.5.6.3b     (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-3.5.3.1        (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-3.5.3.1      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-3.1.4.3        (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-3.1.4.3      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-3.1.2.7        (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-3.1.2.7      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-2.7.3.5        (VHDL   ) starc           No             - LEXICAL        -               
 STARC-2.6.1.4        (VHDL   ) starc           No             - LEXICAL        -               
 STARC-1.3.1.5b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.5b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.3.1.5a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.5a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.5        (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-1.1.1.5      (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-1.1.4.1b       (VHDL   ) starc           No             - LEXICAL        -               
 STARC05-1.1.4.1vb    (VHDL   ) starc2005       No             - LEXICAL        -               
 STARC-1.1.4.1a       (VHDL   ) starc           No             - LEXICAL        -               
 STARC-1.1.1.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.1.3.3        (VHDL   ) starc           No             - VSDU           -               
 STARC-1.1.5.2c       (VHDL   ) starc           No             - FLATDU2_WL     -               
 STARC05-1.1.5.2c     (VHDL   ) starc2005       No             - FLATDU2_WL     -               
 STARC-1.1.5.2b       (VHDL   ) starc           No             - FLATDU2_WL     -               
 STARC-1.1.5.2a       (VHDL   ) starc           No             - FLATDU2_WL     -               
 STARC05-1.1.5.2a     (VHDL   ) starc2005       No             - FLATDU2_WL     -               
 STARC-2.4.1.3        (VHDL   ) starc           No             - VSDU           -               
 STARC05-2.4.1.3      (VHDL   ) starc2005       No             - VSDU           -               
 STARC-2.3.4.1        (VHDL   ) starc           No             - VSDU           -               
 STARC-3.5.6.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.5.6.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.5.6.3a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.5.6.3a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.5.6.2b       (VHDL   ) starc           No             - LEXICAL        -               
 STARC-3.5.6.2a       (VHDL   ) starc           No             - LEXICAL        -               
 STARC-3.2.3.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.2.3.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.2.3.1        (VHDL   ) starc           No             - SETUP          -               
 STARC-3.2.2.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-3.1.6.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.1.6.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.1.6.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.1.6.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.1.5.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-3.1.4.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-3.1.4.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.1.3.5        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.11.5.2       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.11.5.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.11.4.1       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.11.4.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.11.3.1       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.11.2.1       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.11.2.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.11.1.4       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.11.1.3       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.11.1.2       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.11.1.1       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.7.2       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.10.7.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.10.6.6       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.6.5       (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.10.4.7       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.4.5       (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.10.4.3       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.10.4.3     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.10.3.1       (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.10.1.6       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.1.5a      (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.1.4       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.10.1.2       (VHDL   ) starc           No             - SETUP          -               
 STARC05-2.10.1.2     (VHDL   ) starc2005       No             - SETUP          -               
 STARC-2.9.3.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.9.3.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.9.2.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.9.2.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.9.2.3        (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.9.2.2        (VHDL   ) starc           No             - ELABDU         -               
 STARC05-2.9.2.2      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC-2.9.2.1        (VHDL   ) starc           No             - ELABDU         -               
 STARC05-2.9.2.1      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC-2.9.1.1        (VHDL   ) starc           No             - ELABDU         -               
 STARC05-2.9.1.1      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC-2.8.3.4a       (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.8.3.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.8.3.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.8.2.1        (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.8.1.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.8.1.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.7.3.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.7.3.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.7.3.3c       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.3.3b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.3.3a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.3.1c       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.3.1b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.3.1a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.7.2.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.7.2.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.7.1.3b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.7.1.3b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.7.1.3a       (VHDL   ) starc           No             - ELABDU         -               
 STARC05-2.7.1.3a     (VHDL   ) starc2005       No             - ELABDU         -               
 STARC-2.6.2.2        (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.6.2.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.6.2.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.6.1.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.6.1.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.5.1.5b       (VHDL   ) starc           No             - FLATDU2_WL     -               
 STARC-2.5.1.5a       (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.3.6.2b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.6.2a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.3.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.3.2a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.3.3.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.2.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.2.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.3.2.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.8        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.1.8      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.3.1.5a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.1.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.3.1.2c       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.2b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.2a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.3.1.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.3.1.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.2.2.2        (VHDL   ) starc           No             - ELABDU         -               
 STARC-2.2.2.1        (VHDL   ) starc           No             - ELABDU         -               
 STARC05-2.2.2.1      (VHDL   ) starc2005       No             - ELABDU         -               
 STARC-2.1.10.8       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.8     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.6       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.6     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.5       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.5     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.4       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.4     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.3       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.3     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.2       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.2     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.10.1       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.10.1     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.9.5        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.9.5      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.9.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.9.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.9        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.9      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.7        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.10     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.6        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.6      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.5b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.5b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.5a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.5a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.8.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.8.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.7.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.7.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.7.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.7.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.6.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.6.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.6.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.6.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.6.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.5.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.4.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.3.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.3.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-2.1.3.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-2.1.3.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.2.5        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.2.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.2.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.2.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.2.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.1.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-2.1.1.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.6.6.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.6.6.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.6.1.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.6.1.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.3.1.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.6.5        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.6.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.6.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.6.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.4.9        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.4.8        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.4.7        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.4.7      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.4.6        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.4.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.3.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.3.1        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.3.1      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.6b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.6b     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.6a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.6a     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.5        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.5      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.4      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.3        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.3      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.1a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.1.11       (VHDL   ) starc           No             - ELABDU         -               
 STARC-1.1.1.10       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.10     (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.9b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.1.9a       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.1.8        (VHDL   ) starc           No             - ELABDU         -               
 STARC-1.1.1.7        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.1.4        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC-1.1.1.3b       (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.3vb    (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.3a       (VHDL   ) starc           No             - SETUP          -               
 STARC-1.1.1.2        (VHDL   ) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.2      (VHDL   ) starc2005       No             - RTLDULIST      -               
 STARC-3.5.3.1        (Verilog) starc           No             - LEXICAL        -               
 STARC05-3.5.3.1      (Verilog) starc2005       No             - LEXICAL        -               
 STARC-3.2.2.7        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.2.2.7      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.2.2.3        (Verilog) starc           No             - LEXICAL        -               
 STARC05-3.2.2.3      (Verilog) starc2005       No             - LEXICAL        -               
 STARC-3.2.2.2        (Verilog) starc           No             - LEXICAL        -               
 STARC-3.1.4.3        (Verilog) starc           No             - LEXICAL        -               
 STARC05-3.1.4.3      (Verilog) starc2005       No             - LEXICAL        -               
 STARC-3.1.3.4b       (Verilog) starc           No             - LEXICAL        -               
 STARC05-3.1.3.4b     (Verilog) starc2005       No             - LEXICAL        -               
 STARC-2.7.3.5        (Verilog) starc           No             - LEXICAL        -               
 STARC-2.7.3.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.7.3.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.4.4        (Verilog) starc           No             - LEXICAL        -               
 STARC-2.5.1.5a       (Verilog) starc           No             - FLATDU2_WL     -               
 STARC-2.3.6.2b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.1.3        (Verilog) starc           No             - VSDU           -               
 STARC05-2.3.1.3      (Verilog) starc2005       No             - VSDU           -               
 STARC-1.4.4.2        (Verilog) starc           No             - FLATDU2_WL     -               
 STARC05-1.4.4.2      (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC-1.1.5.2c       (Verilog) starc           No             - FLATDU2_WL     -               
 STARC05-1.1.5.2c     (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC-1.1.5.2b       (Verilog) starc           No             - FLATDU2_WL     -               
 STARC-1.1.5.2a       (Verilog) starc           No             - FLATDU2_WL     -               
 STARC05-1.1.5.2a     (Verilog) starc2005       No             - FLATDU2_WL     -               
 STARC-3.1.3.3        (Verilog) starc           No             - VSDU           -               
 STARC-2.4.1.3        (Verilog) starc           No             - VSDU           -               
 STARC05-2.4.1.3      (Verilog) starc2005       No             - VSDU           -               
 STARC-2.3.2.1        (Verilog) starc           No             - VSDU           -               
 STARC05-2.3.2.1      (Verilog) starc2005       No             - VSDU           -               
 STARC-2.2.3.1        (Verilog) starc           No             - VSDU           -               
 STARC05-2.2.3.1      (Verilog) starc2005       No             - VSDU           -               
 STARC-2.1.1.1        (Verilog) starc           No             - VSDU           -               
 STARC-3.5.6.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.5.6.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.5.6.2a       (Verilog) starc           No             - LEXICAL        -               
 STARC-3.5.2.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.2.3.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.2.2.5        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.2.2.5      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.2.2.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.2.2.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.1.5.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC-3.1.4.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.1.4.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.1.3.4a       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.1.3.4a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.1.3.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-3.1.3.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.1.2.7        (Verilog) starc           No             - SETUP          -               
 STARC05-3.1.2.7      (Verilog) starc2005       No             - SETUP          -               
 STARC-2.11.4.2       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.11.4.2     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.11.4.1       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.11.4.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.11.3.1       (Verilog) starc           No             - ELABDU         -               
 STARC-2.11.2.1       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.11.2.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.11.1.4       (Verilog) starc           No             - ELABDU         -               
 STARC-2.11.1.2       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.6.6       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.10.6.5       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.6.1       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.10.6.1     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.10.5.1       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.4.6       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.4.5       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.3.6       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.10.3.6     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.10.3.5       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.10.3.5     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.10.3.2c      (Verilog) starc           No             - ELABDU         -               
 STARC05-2.10.3.2c    (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.10.3.2b      (Verilog) starc           No             - ELABDU         -               
 STARC05-2.10.3.2b    (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.10.3.2a      (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.3.1       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.2.3       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.1.6       (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.1.5b      (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.10.1.5a      (Verilog) starc           No             - ELABDU         -               
 STARC-2.10.1.4       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.9.2.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.2.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.2.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.9.2.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.2.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.2.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.2.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.1.2d       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.9.1.2d     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.9.1.2c       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.1.2c     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.1.2b       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.1.2b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.1.2a       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.1.2a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.9.1.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.9.1.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.5.5        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.5.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.5.4        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.5.3      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.5.3        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.5.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.5.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.8.5.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.4.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.8.4.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.4.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.8.4.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.4.1b       (Verilog) starc           No             - RTLDU          -               
 STARC05-2.8.4.1b     (Verilog) starc2005       No             - RTLDU          -               
 STARC-2.8.4.1a       (Verilog) starc           No             - RTLDU          -               
 STARC05-2.8.4.1a     (Verilog) starc2005       No             - RTLDU          -               
 STARC-2.8.3.5        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.3.5      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.3.4b       (Verilog) starc           No             - ELABDU         -               
 STARC-2.8.3.4a       (Verilog) starc           No             - ELABDU         -               
 STARC-2.8.3.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.8.3.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.2.1        (Verilog) starc           No             - ELABDU         -               
 STARC-2.8.1.6        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.1.6      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.1.5        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.8.1.5      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.8.1.4        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.8.1.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.8.1.3        (Verilog) starc           No             - ELABDU         -               
 STARC-2.7.4.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.7.4.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.7.3.3c       (Verilog) starc           No             - RTLDU          -               
 STARC-2.7.3.3b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.7.3.3a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.7.3.1c       (Verilog) starc           No             - RTLDU          -               
 STARC-2.7.3.1b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.7.3.1a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.7.2.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.7.2.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.7.1.3b       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.7.1.3b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.7.1.3a       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.7.1.3a     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.6.2.2        (Verilog) starc           No             - ELABDU         -               
 STARC-2.6.2.1        (Verilog) starc           No             - RTLDU          -               
 STARC05-2.6.2.1      (Verilog) starc2005       No             - RTLDU          -               
 STARC-2.6.1.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.6.1.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.6.1.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.3.6.2a       (Verilog) starc           No             - ELABDU         -               
 STARC-2.3.4.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.3.4.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.3.4.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.3.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-2.3.3.2a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-2.3.3.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.2.2        (Verilog) starc           No             - ELABDU         -               
 STARC-2.3.1.6        (Verilog) starc           No             - ELABDU         -               
 STARC-2.3.1.5b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.1.5a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.1.4        (Verilog) starc           No             - ELABDU         -               
 STARC-2.3.1.2b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.3.1.2a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.2.3.3        (Verilog) starc           No             - ELABDU         -               
 STARC-2.2.3.2        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.2.3.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.2.2.2        (Verilog) starc           No             - ELABDU         -               
 STARC-2.2.2.1        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.2.2.1      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.6.4        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.6.4      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.6.3        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.6.3      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.6.2        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.6.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.6.1        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.5.3        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.5.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.1.4.7b       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.4.6b     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.4.7a       (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.4.6a     (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.4.6        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.1.4.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.1.4.1        (Verilog) starc           No             - SETUP          -               
 STARC05-2.1.4.1      (Verilog) starc2005       No             - SETUP          -               
 STARC-2.1.3.5        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.3.5      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.3.4        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.3.2        (Verilog) starc           No             - ELABDU         -               
 STARC05-2.1.3.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.1.3.1        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.2.6        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.2.5        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.2.4        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.2.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC-2.1.2.2        (Verilog) starc           No             - ELABDU         -               
 STARC-2.1.1.2        (Verilog) starc           No             - ELABDU         -               
 STARC-1.6.6.3        (Verilog) starc           No             - ELABDU         -               
 STARC-1.6.6.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.6.1.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.6.1.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.3.1.5b       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.5b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.3.1.5a       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.5a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.3.1.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.3.1.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.4.9a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.4.9        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.4.8        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.4.7        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.4.7      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.4.6        (Verilog) starc           No             - ELABDU         -               
 STARC-1.1.4.5        (Verilog) starc           No             - LEXICAL        -               
 STARC05-1.1.4.5      (Verilog) starc2005       No             - LEXICAL        -               
 STARC-1.1.4.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.4.1a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.3.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.3.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.6b       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.6b     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.6a       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.6a     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.5        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.5      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.4      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.3        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.3      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.2.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.2.1a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.10       (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.10     (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.9b       (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.9a       (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.8        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.7        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.6        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.5        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.5      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.4        (Verilog) starc           No             - RTLDULIST      -               
 STARC-1.1.1.2        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.2      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-1.1.1.1        (Verilog) starc           No             - RTLDULIST      -               
 STARC05-1.1.1.1      (Verilog) starc2005       No             - RTLDULIST      -               
 STARC-3.2.4.3        (Verilog) starc           No             - RTLDU          -               
 STARC05-3.2.4.3      (Verilog) starc2005       No             - RTLDU          -               
 STARC-3.2.3.2        (Verilog) starc           No             - ELABDU         -               
 STARC05-3.2.3.2      (Verilog) starc2005       No             - ELABDU         -               
 STARC-2.3.1.2c       (Verilog) starc           No             - SETUP          -               
 STARC-2.3.1.1        (Verilog) starc           No             - VSDU           -               
 STARC05-2.3.1.1      (Verilog) starc2005       No             - VSDU           -               
 STARC-1.1.1.3a       (Verilog) starc           No             - SETUP          -               
 PortOrder_C          (VHDL   ) openmore        No             - ELABDU         -               
 PortOrder_B                    openmore        No             - VSDU           -               
 PortOrder_A                    openmore        No             - FLATDU2_WL     -               
 ClockDomain                    openmore        No             - FLATDU2_WL     -               
 AvoidAsync                     openmore        No             - VSDU           -               
 GateResetAtTop                 openmore        No             - FLATDU2_WL     -               
 IntReset                       openmore        No             - FLATDU2_WL     -               
 GateClockAtTop                 openmore        No             - FLATDU2_WL     -               
 IntClock                       openmore        No             - FLATDU2_WL     -               
 GatedClock                     openmore        No             - FLATDU2_WL     -               
 SepClock                       openmore        No             - FLATDU2_WL     -               
 ClockPhase                     openmore        No             - FLATDU2_WL     -               
 AsyncName                      openmore        No             - VSDU           -               
 ResetName                      openmore        No             - VSDU           -               
 ClkHierName                    openmore        No             - FLATDU2_WL     -               
 ClkName                        openmore        No             - FLATDU2_WL     -               
 RegInName                      openmore        No             - VSDU           -               
 RegOutName                     openmore        No             - VSDU           -               
 RegOutputs                     openmore        No             - FLATDU2_WL     -               
 InferFF                        openmore        No             - VSDU           -               
 TriStateName                   openmore        No             - VSDU           -               
 UseMuxBusses                   openmore        No             - VSDU           -               
 Indent               (VHDL   ) openmore        No             - LEXICAL        -               
 Indent               (Verilog) openmore        No             - LEXICAL        -               
 NoMixedSynch                   openmore        No             - VSDU           -               
 NameLength           (VHDL   ) openmore        No             - RTLDULIST      -               
 NameLength           (Verilog) openmore        No             - RTLDULIST      -               
 Uniq8Char            (VHDL   ) openmore        No             - RTLDULIST      -               
 Uniq8Char            (Verilog) openmore        No             - RTLDULIST      -               
 LineLength           (VHDL   ) openmore        No             - LEXICAL        -               
 LineLength           (Verilog) openmore        No             - LEXICAL        -               
 SepFSMLogic          (VHDL   ) openmore        No             - RTLDULIST      -               
 SepFSMLogic          (Verilog) openmore        No             - RTLDULIST      -               
 PortGroups           (VHDL   ) openmore        No             - RTLDULIST      -               
 PortGroups           (Verilog) openmore        No             - RTLDULIST      -               
 ParamName            (VHDL   ) openmore        No             - RTLDULIST      -               
 ParamName            (Verilog) openmore        No             - RTLDULIST      -               
 SigName              (VHDL   ) openmore        No             - RTLDULIST      -               
 SigName              (Verilog) openmore        No             - RTLDULIST      -               
 ActLowName           (VHDL   ) openmore        No             - RTLDULIST      -               
 ActLowName           (Verilog) openmore        No             - RTLDULIST      -               
 InstName             (VHDL   ) openmore        No             - RTLDULIST      -               
 InstName             (Verilog) openmore        No             - RTLDULIST      -               
 NoGates              (VHDL   ) openmore        No             - RTLDULIST      -               
 NoGates              (Verilog) openmore        No             - RTLDULIST      -               
 NoTab                (VHDL   ) openmore        No             - LEXICAL        -               
 NoTab                (Verilog) openmore        No             - LEXICAL        -               
 PortComment          (VHDL   ) openmore        No             - LEXICAL        -               
 PortComment          (Verilog) openmore        No             - LEXICAL        -               
 PortName             (VHDL   ) openmore        No             - RTLDULIST      -               
 PortName             (Verilog) openmore        No             - RTLDULIST      -               
 ArrayIndex           (VHDL   ) openmore        No             - ELABDU         -               
 ArrayIndex           (Verilog) openmore        No             - ELABDU         -               
 FunctionComment      (VHDL   ) openmore        No             - LEXICAL        -               
 FunctionComment      (Verilog) openmore        No             - LEXICAL        -               
 FuncName             (VHDL   ) openmore        No             - RTLDULIST      -               
 FuncName             (Verilog) openmore        No             - RTLDULIST      -               
 VarName              (VHDL   ) openmore        No             - RTLDULIST      -               
 VarName              (Verilog) openmore        No             - RTLDULIST      -               
 OnePortLine          (VHDL   ) openmore        No             - RTLDULIST      -               
 OnePortLine          (Verilog) openmore        No             - RTLDULIST      -               
 NamedAssoc           (VHDL   ) openmore        No             - SETUP          -               
 NamedAssoc           (Verilog) openmore        No             - RTLDULIST      -               
 NoTopLogic           (VHDL   ) openmore        No             - RTLDULIST      -               
 NoTopLogic           (Verilog) openmore        No             - RTLDULIST      -               
 NoTopGates           (VHDL   ) openmore        No             - RTLDULIST      -               
 NoTopGates           (Verilog) openmore        No             - RTLDULIST      -               
 UseDefine            (VHDL   ) openmore        No             - RTLDULIST      -               
 UseDefine            (Verilog) openmore        No             - RTLDULIST      -               
 SepStateMachine      (VHDL   ) openmore        No             - RTLDULIST      -               
 SepStateMachine      (Verilog) openmore        No             - RTLDULIST      -               
 DefaultState         (VHDL   ) openmore        No             - RTLDULIST      -               
 DefaultState         (Verilog) openmore        No             - RTLDULIST      -               
 OneStmtLine          (VHDL   ) openmore        No             - RTLDULIST      -               
 OneStmtLine          (Verilog) openmore        No             - RTLDULIST      -               
 NoScripts            (VHDL   ) openmore        No             - LEXICAL        -               
 ConstantComment      (VHDL   ) openmore        No             - LEXICAL        -               
 VariableComment      (VHDL   ) openmore        No             - LEXICAL        -               
 SignalComment        (VHDL   ) openmore        No             - LEXICAL        -               
 PortGrpComment       (VHDL   ) openmore        No             - LEXICAL        -               
 TypeComment          (VHDL   ) openmore        No             - LEXICAL        -               
 ProcessComment       (VHDL   ) openmore        No             - LEXICAL        -               
 PackHdr              (VHDL   ) openmore        No             - LEXICAL        -               
 ArchHdr              (VHDL   ) openmore        No             - LEXICAL        -               
 EntHdr               (VHDL   ) openmore        No             - LEXICAL        -               
 FileHdr              (VHDL   ) openmore        No             - LEXICAL        -               
 ConsCase             (VHDL   ) openmore        No             - LEXICAL        -               
 CaseOverIf           (VHDL   ) openmore        No             - RTLDULIST      -               
 NoVar                (VHDL   ) openmore        No             - RTLDULIST      -               
 NotReqSens           (VHDL   ) openmore        No             - ELABDU         -               
 NotInSens            (VHDL   ) openmore        No             - ELABDU         -               
 ModConst             (VHDL   ) openmore        No             - RTLDULIST      -               
 NoBlock              (VHDL   ) openmore        No             - RTLDULIST      -               
 NoGenerate           (VHDL   ) openmore        No             - RTLDULIST      -               
 DesgPack             (VHDL   ) openmore        No             - RTLDULIST      -               
 InvSigType           (VHDL   ) openmore        No             - RTLDULIST      -               
 TypeCount            (VHDL   ) openmore        No             - RTLDULIST      -               
 SigType              (VHDL   ) openmore        No             - RTLDULIST      -               
 IEEEType             (VHDL   ) openmore        No             - RTLDULIST      -               
 NoDup                (VHDL   ) openmore        No             - RTLDULIST      -               
 ProcName             (VHDL   ) openmore        No             - RTLDULIST      -               
 OneFile              (VHDL   ) openmore        No             - RTLDULIST      -               
 ArchName             (VHDL   ) openmore        No             - RTLDULIST      -               
 TypeName             (VHDL   ) openmore        No             - RTLDULIST      -               
 ConstName            (VHDL   ) openmore        No             - RTLDULIST      -               
 SigHierName          (VHDL   ) openmore        No             - RTLDULIST      -               
 ReserveName          (VHDL   ) openmore        No             - SETUP          -               
 HardConst            (VHDL   ) openmore        No             - RTLDULIST      -               
 ExprParen            (VHDL   ) openmore        No             - SETUP          -               
 VariableComment      (Verilog) openmore        No             - LEXICAL        -               
 SignalComment        (Verilog) openmore        No             - LEXICAL        -               
 AlwaysComment        (Verilog) openmore        No             - LEXICAL        -               
 TaskComment          (Verilog) openmore        No             - LEXICAL        -               
 FileHdr              (Verilog) openmore        No             - LEXICAL        -               
 NonBlockAssign       (Verilog) openmore        No             - VSDU           -               
 CaseOverIf           (Verilog) openmore        No             - RTLDULIST      -               
 ConsCase             (Verilog) openmore        No             - RTLDULIST      -               
 NotReqSens           (Verilog) openmore        No             - ELABDU         -               
 NotInSens            (Verilog) openmore        No             - ELABDU         -               
 NoDefine             (Verilog) openmore        No             - RTLDULIST      -               
 InstNameLength       (Verilog) openmore        No             - RTLDULIST      -               
 SigHierName          (Verilog) openmore        No             - RTLDULIST      -               
 ConstName            (Verilog) openmore        No             - RTLDULIST      -               
 NoScripts            (Verilog) openmore        No             - SETUP          -               
 ReserveName          (Verilog) openmore        No             - SETUP          -               
 HardConst            (Verilog) openmore        No             - RTLDULIST      -               
 ExprParen            (Verilog) openmore        No             - SETUP          -               
 Ac_svasetup01                  clock-reset     Yes            0 VSDU           -               
 AcOvlRtl             (VHDL   ) clock-reset     Yes            0 ELABDU         -               
 AcOvlRtl             (Verilog) clock-reset     Yes            0 ELABDU         -               
 _meta_delay01                  clock-reset     Yes            0 VSDU           -               
 _vhMeta01            (VHDL   ) clock-reset     Yes            0 VSDU           -               
 SGDC_meta_design_hier01        clock-reset     Yes            0 RTLTOPDU       -               
 Ac_multitop01                  clock-reset     Yes            0 RTLALLDULIST   -               
 _deltaDelay          (Verilog) clock-reset     Yes            0 RTLDULIST      -               
 _deltaDelay          (VHDL   ) clock-reset     Yes            0 RTLDULIST      -               
 _syncResetStyleRTL             clock-reset     Yes            0 VSDU           -               
 Reset_check05                  clock-reset     Yes            0 VSDU           -               
 syncRstReq           (VHDL   ) clock-reset     Yes            0 ELABDU         -               
 syncRstReq           (Verilog) clock-reset     Yes            0 ELABDU         -               
 Pragma_setupa                  clock-reset     Yes            0 RTLDULIST      -               
 _cdc_save_license01            clock-reset     Yes            0 VSDU           -               
 PEMVDD01                       power_est       Yes            0 SETUP          -               
 PECHECK43                      power_est       Yes            0 VSTOPDU        -               
 PECHECK18                      power_est       Yes            0 SETUP          -               
 PECHECK09                      power_est       Yes            0 RTLALLDULIST   -               
 PESVASETUP01                   power_est       Yes            0 VSDU           -               
 PECHECK04                      power_est       Yes            0 SETUP          -               
 SGDC_power_est29               power_est       Yes            0 SETUP          -               
 TxvVhMeta01          (VHDL   ) txv             Yes            0 VSDU           -               
 Txv_SvaSetup01       (Verilog) txv             Yes            0 VSDU           -               
 STARC05-2.5.1.9      (Verilog) starc2005       Yes            0 VSDU           -               
 STARC05-2.1.6.5      (Verilog) starc2005       Yes            0 SETUP          -               
 STARC05-1.2.1.2                starc2005       Yes            0 FLATDU2_WL     -               
 STARC05-2.4.1.5                starc2005       Yes            0 FLATDU2_WL     -               
 STARC05-2.5.1.7      (VHDL   ) starc2005       Yes            0 VSDU           -               
 STARC05-2.5.1.7      (Verilog) starc2005       Yes            0 VSDU           -               
 LogNMuxPrereq                  timing          Yes            0 SETUP          -               
 NoXInCase-ML         (VHDL   ) morelint        Yes            0 ELABDU         -               
 Postreqs_Usage_ML    (Verilog) morelint        Yes            0 ELABDU         -               
 Prereqs_InclFileSetup-ML(Verilog) morelint        Yes            0 RTLDULIST      -               
 CheckDelayTimescale-ML(Verilog) morelint        Yes            1 RTLDULIST      -               
 ParamWidthMismatch-ML(Verilog) morelint        Yes            0 ELABDU         -               
 NoAssignX-ML         (Verilog) morelint        Yes            0 ELABDU         -               
 PragmaComments-ML    (VHDL   ) morelint        Yes            0 RTLDULIST      -               
 PragmaComments-ML    (Verilog) morelint        Yes            0 RTLDULIST      -               
 ReportPortInfo-ML              morelint        Yes            0 ELABDU         -               
 RegInputOutput-ML              morelint        Yes            0 VSDU           -               
 Prereqs_RegInputOutputs        morelint        Yes            0 RTLDULIST      -               
 Prereqs_ConstantInput-ML(VHDL   ) morelint        Yes            0 ELABDU         -               
 Prereqs_ConstantInput-ML(Verilog) morelint        Yes            0 ELABDU         -               
 UndrivenInTerm-ML              morelint        Yes            0 VSTOPDU        -               
 HangingNetPreReq-ML            morelint        Yes            0 SETUP          -               
 Latch_VePreReqRule   (Verilog) latch           Yes            0 RTLDULIST      -               
 W450L                (Verilog) latch           Yes            0 VSDU           -               
 LatchFeedback                  latch           Yes            0 FLATDU2_WL     -               
 Prereqs_RTLSchematic (Verilog) lint            Yes            0 SETUP          -               
 LINT_portReten                 lint            Yes            0 SETUP          -               
 Postreqs_CheckFuncTask(Verilog) lint            Yes            0 ELABDU         -               
 Prereqs_Usage        (Verilog) lint            Yes            0 ELABDU         -               
 W415                           lint            Yes            0 FLATDU2_WL     -               
 W392                           lint            Yes            0 FLATDU2_WL     -               
 W528                 (VHDL   ) lint            Yes            0 ELABDU         -               
 W528                 (Verilog) lint            Yes            4 ELABDU         -               
 W505                 (VHDL   ) lint            Yes            0 ELABDU         -               
 W505                 (Verilog) lint            Yes            0 ELABDU         -               
 W467                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W467                 (Verilog) lint            Yes            0 ELABDU         -               
 W424                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W424                 (Verilog) lint            Yes            0 ELABDU         -               
 W421                 (VHDL   ) lint            Yes            0 SETUP          -               
 W421                 (Verilog) lint            Yes            0 RTLDULIST      -               
 W398                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W398                 (Verilog) lint            Yes            0 ELABDU         -               
 W293                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W293                 (Verilog) lint            Yes            0 ELABDU         -               
 W287b                (VHDL   ) lint            Yes            0 VSDU           -               
 W287b                (Verilog) lint            Yes            0 RTLDULIST      -               
 W287a                (VHDL   ) lint            Yes            0 VSDU           -               
 W287a                (Verilog) lint            Yes            0 ELABDU         -               
 W240                 (VHDL   ) lint            Yes            0 ELABDU         -               
 W240                 (Verilog) lint            Yes            1 ELABDU         -               
 W71                  (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W71                  (Verilog) lint            Yes            0 ELABDU         -               
 W110a                (VHDL   ) lint            Yes            0 RTLDU          -               
 mixedsenselist       (VHDL   ) lint            Yes            0 RTLDU          -               
 W416                 (VHDL   ) lint            Yes            0 RTLDU          -               
 W292                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W156                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W123                 (VHDL   ) lint            Yes            0 ELABDU         -               
 W122                 (VHDL   ) lint            Yes            0 ELABDU         -               
 W116                 (VHDL   ) lint            Yes            0 ELABDU         -               
 BlockHeader          (VHDL   ) lint            Yes            0 SETUP          -               
 W422                 (VHDL   ) lint            Yes            0 RTLDULIST      -               
 W414                 (Verilog) lint            Yes            0 VSDU           -               
 W336                 (Verilog) lint            Yes            0 VSDU           -               
 W502                 (Verilog) lint            Yes            0 ELABDU         -               
 W499                 (Verilog) lint            Yes            0 ELABDU         -               
 W486                 (Verilog) lint            Yes            0 ELABDU         -               
 W481b                (Verilog) lint            Yes            0 RTLDULIST      -               
 W481a                (Verilog) lint            Yes            0 RTLDULIST      -               
 W480                 (Verilog) lint            Yes            0 RTLDULIST      -               
 W426                 (Verilog) lint            Yes            8 RTLDULIST      -               
 W422                 (Verilog) lint            Yes            0 RTLDULIST      -               
 W415a                (Verilog) lint            Yes            0 ELABDU         -               
 W362                 (Verilog) lint            Yes            3 ELABDU         -               
 W352                 (Verilog) lint            Yes            0 ELABDU         -               
 W337                 (Verilog) lint            Yes            0 ELABDU         -               
 W317                 (Verilog) lint            Yes            0 RTLDULIST      -               
 W289                 (Verilog) lint            Yes            0 ELABDU         -               
 W263                 (Verilog) lint            Yes            0 ELABDU         -               
 W224                 (Verilog) lint            Yes            0 ELABDU         -               
 W218                 (Verilog) lint            Yes            0 ELABDU         -               
 W216                 (Verilog) lint            Yes            0 ELABDU         -               
 W215                 (Verilog) lint            Yes            0 ELABDU         -               
 W156                 (Verilog) lint            Yes            0 ELABDU         -               
 W123                 (Verilog) lint            Yes            0 ELABDU         -               
 W116                 (Verilog) lint            Yes            0 ELABDU         -               
 W66                  (Verilog) lint            Yes            0 ELABDU         -               
 W19                  (Verilog) lint            Yes            0 ELABDU         -               
 W496b                (Verilog) lint            Yes            0 RTLDULIST      -               
 W496a                (Verilog) lint            Yes            0 ELABDU         -               
 W122                 (Verilog) lint            Yes            0 ELABDU         -               
 W110                 (Verilog) lint            Yes            0 ELABDU         -               
 bothedges            (Verilog) lint            Yes            0 SETUP          -               
 badimplicitSM4       (Verilog) lint            Yes            0 SETUP          -               
 badimplicitSM2       (Verilog) lint            Yes            0 SETUP          -               
 badimplicitSM1       (Verilog) lint            Yes            0 SETUP          -               
 mixedsenselist       (Verilog) lint            Yes            0 SETUP          -               
 W442f                (Verilog) lint            Yes            0 SETUP          -               
 W442c                (Verilog) lint            Yes            0 SETUP          -               
 W442b                (Verilog) lint            Yes            0 SETUP          -               
 W442a                (Verilog) lint            Yes            0 SETUP          -               
 W339a                (Verilog) lint            Yes            0 RTLDU          -               
 sim_race02           (Verilog) simulation      Yes            0 RTLDU          -               
 checkPinConnectedToSupply      erc             Yes            0 FLATDU2_WL     -               
 FlopEConst                     erc             Yes            0 FLATDU2_WL     -               
 FlopSRConst                    erc             Yes            0 FLATDU2_WL     -               
 FlopClockConstant              erc             Yes            0 FLATDU2_WL     -               
 STARC05-2.3.4.1v     (VHDL   ) starc2005       Yes            0 VSDU           -               
 STARC05-ProcessParamSetup(VHDL   ) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.10.1.4b    (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.10.1.4a    (Verilog) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.3.1.2c     (Verilog) starc2005       Yes            0 SETUP          -               
 STARC05-2.1.3.1      (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-AlwaysParamSetup(Verilog) starc2005       Yes            0 RTLDULIST      -               
 Prereqs_STARC-2.3.6.1          starc           Yes            0 ELABDU         -               
 STARC05-1.4.3.4                starc2005       Yes            0 FLATDU2_WL     -               
 STARC-1.3.2.2_prereq           starc           Yes            0 SETUP          -               
 STARC05-1.3.1.3                starc2005       Yes            0 FLATDU2_WL     -               
 STARC05-2.5.1.2                starc2005       Yes            0 FLATDU2_WL     -               
 preReq_ConsCase      (VHDL   ) starc           Yes            0 RTLDULIST      -               
 STARC05-2.11.3.1     (VHDL   ) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.3.3.1      (VHDL   ) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.11.3.1     (Verilog) starc2005       Yes            1 ELABDU         -               
 STARC05-2.10.3.2a    (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.10.2.3     (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.3.3.1      (Verilog) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.3.1.6      (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.3.1.5b     (Verilog) starc2005       Yes            0 RTLDULIST      -               
 STARC05-2.2.3.3      (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.1.5.3      (Verilog) starc2005       Yes            0 ELABDU         -               
 STARC05-2.1.4.5      (Verilog) starc2005       Yes            0 RTLDULIST      -               
 CombLoop                       openmore        Yes            0 FLATDU2_WL     -               
 BufClock                       openmore        Yes            0 FLATDU2_WL     -               
 Prereqs_RegOutputs             openmore        Yes            0 RTLDULIST      -               
 InferLatch                     openmore        Yes            0 VSTOPDU        -               
 preReq_ConsCase2     (VHDL   ) openmore        Yes            0 RTLDULIST      -               
 SYNTH_196            (Verilog) SpyGlass        Yes            4 SETUP          -               
 SYNTH_106            (Verilog) SpyGlass        Yes            2 SETUP          -               
 ElabSummary                    SpyGlass        Yes            1 SETUP          -               
 ErrorAnalyzeBBox               SpyGlass        Yes            1 SETUP          -               
 DetectTopDesignUnits           SpyGlass        Yes            1 RTLALLDULIST   -               
-------------------------------------------------------------------------------------
Note: VSDU type of rules (as seen in the above table) are not run on
      unsynthesized modules reported by 'ErrorAnalyzeBBox/InfoAnalyzeBBox' messages
      (Please see messages starting with keyword 'UnsynthesizedDU')

##status : SpyGlass Rule Checking Complete.

---------------------------------------------------------------------------------------------
Results Summary:
---------------------------------------------------------------------------------------------
   Goal Run           :      lint/lint_rtl
   Command-line read  :      0 error,      0 warning,      0 information message 
** Design Read        :      6 errors,     0 warning,      2 information messages
      Found 1 top module:
         tb_wchannel   (file: ../tb/tb_wchannel.v)

   Blackbox Resolution:      1 error,      0 warning,      0 information message 
   SGDC Checks        :      0 error,      0 warning,      0 information message 
   Policy lint        :      0 error,     15 warnings,     1 information message 
   Policy morelint    :      0 error,      1 warning,      0 information message 
   Policy starc2005   :      0 error,      1 warning,      0 information message 
   -------------------------------------------------------------------------------------
   Total              :      7 errors,    17 warnings,     3 information messages

  Total Number of Generated Messages     :        27 (7 errors, 17 warnings, 3 Infos)
  Number of Reported Messages            :        27 (7 errors, 17 warnings, 3 Infos)

  NOTE: It is recommended to first fix/reconcile fatals/errors reported on
        lines starting with ** as subsequent issues might be related to it.
        Please re-run SpyGlass once ** prefixed lines are fatal/error clean.

---------------------------------------------------------------------------------------------



SpyGlass Rule Checking Complete.

Generating moresimple report from './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass.vdb' to './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/moresimple.rpt' ....

Generating runsummary report from './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass.vdb' ....

Generating no_msg_reporting_rules report from './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass.vdb' to './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/no_msg_reporting_rules.rpt' ....

Policy specific data (reports) are present in the directory './spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports'.

SpyGlass critical reports for the current run are present in directory './spyglass-1/consolidated_reports/tb_wchannel_lint_lint_rtl/'.


---------------------------------------------------------------------------------------------------
Results Summary:
---------------------------------------------------------------------------------------------------
   Goal Run           :      lint/lint_rtl
   Top Module         :      tb_wchannel
---------------------------------------------------------------------------------------------------
   Reports Directory: 
   /home/ICer/ic_prjs/mc/sim/spyglass-1/consolidated_reports/tb_wchannel_lint_lint_rtl/ 

   SpyGlass LogFile: 
    /home/ICer/ic_prjs/mc/sim/spyglass-1/tb_wchannel/lint/lint_rtl/spyglass.log 

   Standard Reports: 
     moresimple.rpt          no_msg_reporting_rules.rpt       

   HTML report:
    /home/ICer/ic_prjs/mc/sim/spyglass-1/html_reports/goals_summary.html
  

   Technology Reports:  
     <Not Available>
   
   
---------------------------------------------------------------------------------------------------
   Goal Violation Summary:
       Waived   Messages:                      0 Errors,      0 Warnings,      0 Infos
       Reported Messages:         0 Fatals,    7 Errors,     17 Warnings,      3 Infos
---------------------------------------------------------------------------------------------------
   
---------------------------------------------------------------------------------------------------
 
SpyGlass Exit Code 0 (Rule-checking completed with errors)
SpyGlass total run-time is 0:0:9 (9 secs)
SpyGlass run completed at 11:15:47 AM on Aug 05 2025
