264 lines
8.9 KiB
Coq
264 lines
8.9 KiB
Coq
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module array_rd (
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input clk,
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input rst_n,
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input array_rd_frame_valid,
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input [151:0] array_rd_frame_data,
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output array_rd_frame_ready,
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output array_rd_done,
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output reg array_rd_csn,
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output reg [15:0] array_rd_raddr,
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output reg array_caddr_vld_rd,
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output reg [5:0] array_caddr_rd,
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input array_rdata_vld,
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input [127:0] array_rdata,
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input [7:0] array_inner_tras,
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input [7:0] array_inner_trp,
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input [7:0] array_inner_trcd_rd,
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input [7:0] array_inner_trtp,
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output array2axi_rdata_valid,
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output [127:0] array2axi_rdata
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);
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reg [2:0] cur_state,next_state;
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localparam [2:0] ARR_RD_IDLE = 3'b000;
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localparam [2:0] ARR_RD_LOWCS = 3'b001;
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localparam [2:0] ARR_RD_RCD = 3'b010;
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localparam [2:0] ARR_RD_HIGHVLD = 3'b011;
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localparam [2:0] ARR_RD_RADDRLAST = 3'b100;
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localparam [2:0] ARR_RD_RADDR = 3'b101;
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localparam [2:0] ARR_RD_RTP = 3'b110;
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localparam [2:0] ARR_RD_RP = 3'b111;
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wire rsof,reof;
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wire [15:0] rraddr;
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wire [5:0] rcaddr;
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wire [127:0] wdata;
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reg [7:0] rd_ras_cnt;
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reg [7:0] rd_rcd_cnt;
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reg [7:0] rd_rtp_cnt;
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reg [7:0] rd_rp_cnt;
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reg single_flag_rd;
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reg array_raddr_eof;
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wire async_fifo_r_wr_clk;
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wire async_fifo_r_wr_rst_n;
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wire async_fifo_r_wr_en;
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wire [127:0] async_fifo_r_wr_data;
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wire async_fifo_r_full;
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wire async_fifo_r_rd_clk;
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wire async_fifo_r_rd_rst_n;
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wire async_fifo_r_rd_en;
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wire [127:0] async_fifo_r_rd_data;
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wire async_fifo_r_empty;
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async_fifo #(.FIFO_DEPTH(4),
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.DATA_WIDTH(128)
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) async_fifo_r (
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.wr_clk (async_fifo_r_wr_clk),
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.wr_rst_n (async_fifo_r_wr_rst_n),
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.wr_en (async_fifo_r_wr_en),
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.wr_data (async_fifo_r_wr_data),
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.full (async_fifo_r_full),
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.rd_clk (async_fifo_r_rd_clk),
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.rd_rst_n (async_fifo_r_rd_rst_n),
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.rd_en (async_fifo_r_rd_en),
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.rd_data (async_fifo_r_rd_data),
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.empty (async_fifo_r_empty)
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);
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assign {rsof,reof,rraddr,rcaddr,wdata} = array_rd_frame_data;
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assign array_rd_frame_ready = (cur_state == ARR_RD_IDLE || ((cur_state == ARR_RD_RADDR) &&
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!array_caddr_vld_rd));
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assign array_rd_done = (cur_state == ARR_RD_RP) && rd_rp_cnt == 'd0;
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assign array2axi_rdata_valid = !async_fifo_r_empty;
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assign array2axi_rdata = async_fifo_r_rd_data;
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assign async_fifo_r_wr_clk = array_rdata_vld;
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assign async_fifo_r_wr_rst_n = rst_n;
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assign async_fifo_r_wr_en = 1'b1;
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assign async_fifo_r_wr_data = array_rdata;
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assign async_fifo_r_rd_clk = clk;
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assign async_fifo_r_rd_rst_n = rst_n;
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assign async_fifo_r_rd_en = !async_fifo_r_empty;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cur_state <= ARR_RD_IDLE;
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end else begin
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cur_state <= next_state;
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end
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end
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always @(*) begin
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case (cur_state)
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ARR_RD_IDLE : begin
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if (array_rd_frame_valid && rsof) begin
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next_state = ARR_RD_LOWCS;
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end else begin
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next_state = ARR_RD_IDLE;
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end
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end
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ARR_RD_LOWCS : begin
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next_state = ARR_RD_RCD;
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end
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ARR_RD_RCD : begin
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if (rd_rcd_cnt == 'd0) begin
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next_state = ARR_RD_HIGHVLD;
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end else begin
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next_state = ARR_RD_RCD;
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end
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end
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ARR_RD_HIGHVLD : begin
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if (single_flag_rd) begin
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next_state = ARR_RD_RADDRLAST;
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end else begin
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next_state = ARR_RD_RADDR;
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end
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end
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ARR_RD_RADDRLAST : begin
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next_state = ARR_RD_RTP;
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end
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ARR_RD_RADDR : begin
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if (array_raddr_eof) begin
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next_state = ARR_RD_RTP;
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end else begin
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next_state = ARR_RD_RADDR;
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end
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end
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ARR_RD_RTP : begin
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if (rd_ras_cnt == 'd0 && rd_rtp_cnt == 'd0) begin
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next_state = ARR_RD_RP;
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end else begin
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next_state = ARR_RD_RTP;
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end
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end
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ARR_RD_RP : begin
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if (rd_rp_cnt == 'd0) begin
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next_state = ARR_RD_IDLE;
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end else begin
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next_state = ARR_RD_RP;
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end
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end
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default : begin
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next_state = ARR_RD_IDLE;
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end
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endcase
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_rd_csn <= 1'b1;
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end else if (cur_state == ARR_RD_LOWCS) begin
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array_rd_csn <= 1'b0;
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end else if (cur_state == ARR_RD_RTP && next_state == ARR_RD_RP) begin
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array_rd_csn <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_rd_raddr <= 'b0;
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end else if (array_rd_frame_valid && array_rd_frame_ready) begin
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array_rd_raddr <= rraddr;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_caddr_rd <= 'b0;
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end else if (array_rd_frame_valid && array_rd_frame_ready) begin
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array_caddr_rd <= rcaddr;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_caddr_vld_rd <= 'd0;
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end else if (array_caddr_vld_rd == 1'b1) begin
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array_caddr_vld_rd <= 1'b0;
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end else if (cur_state == ARR_RD_HIGHVLD || (cur_state == ARR_RD_RADDR &&
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array_rd_frame_valid && array_rd_frame_ready)) begin
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array_caddr_vld_rd <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_ras_cnt <= 'd0;
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end else if (cur_state == ARR_RD_LOWCS) begin
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rd_ras_cnt <= array_inner_tras - 1'b1;
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end else if (rd_ras_cnt == 'd0) begin
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rd_ras_cnt <= rd_ras_cnt;
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end else begin
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rd_ras_cnt <= rd_ras_cnt - 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_rcd_cnt <= 'd0;
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end else if (cur_state == ARR_RD_LOWCS) begin
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rd_rcd_cnt <= array_inner_trcd_rd - 2'b10;
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end else if (cur_state == ARR_RD_RCD) begin
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if (rd_rcd_cnt == 'd0) begin
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rd_rcd_cnt <= rd_rcd_cnt;
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end else begin
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rd_rcd_cnt <= rd_rcd_cnt - 1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_rtp_cnt <= 'd0;
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end else if (cur_state == ARR_RD_LOWCS) begin
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rd_rtp_cnt <= array_inner_trtp - 1'b1;
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end else if (cur_state == ARR_RD_RTP) begin
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if (rd_rtp_cnt == 'd0) begin
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rd_rtp_cnt <= rd_rtp_cnt;
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end else begin
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rd_rtp_cnt <= rd_rtp_cnt - 1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_rp_cnt <= 'd0;
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end else if (cur_state == ARR_RD_LOWCS) begin
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rd_rp_cnt <= array_inner_trp - 1'b1;
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end else if (cur_state == ARR_RD_RP) begin
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if (rd_rp_cnt == 'd0) begin
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rd_rp_cnt <= rd_rp_cnt;
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end else begin
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rd_rp_cnt <= rd_rp_cnt - 1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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single_flag_rd <= 'd0;
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end else if (cur_state == ARR_RD_IDLE && array_rd_frame_valid && rsof) begin
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single_flag_rd <= reof;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_raddr_eof <= 'd0;
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end else if (array_rd_frame_valid && array_rd_frame_ready) begin
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array_raddr_eof <= reof;
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end else begin
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array_raddr_eof <= 'd0;
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end
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end
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endmodule
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