63 lines
1.6 KiB
Coq
63 lines
1.6 KiB
Coq
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module sync_fifo_128_to_64 #(
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parameter DATA_IN_WIDTH = 128,
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parameter DATA_OUT_WIDTH = 64,
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parameter FIFO_DEPTH = 16,
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parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
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)(
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input clk,
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input rst_n,
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input wr_en,
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input [DATA_IN_WIDTH-1:0] wr_data,
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output full,
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input rd_en,
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output [DATA_OUT_WIDTH-1:0] rd_data,
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output empty
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);
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reg [DATA_OUT_WIDTH-1:0] mem [0 :FIFO_DEPTH -1];
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reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
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wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
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assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
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assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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wr_ptr <= 'd0;
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end else if(wr_en && !full) begin
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wr_ptr <= wr_ptr + 2'd2;
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end else begin
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wr_ptr <= wr_ptr;
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rd_ptr <= 'd0;
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end else if(rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'd1;
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end else begin
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rd_ptr <= rd_ptr;
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end
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end
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integer i;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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for(i=0;i<FIFO_DEPTH;i=i+1) begin
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mem[i] <= 'd0;
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end
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end else if(wr_en && !full) begin
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{mem[wr_addr+1'b1],mem[wr_addr]} <= wr_data;
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end else begin
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mem[wr_addr] <= mem[wr_addr];
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end
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end
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assign rd_data = mem[rd_addr];
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assign full = (wr_ptr - rd_ptr == FIFO_DEPTH) ? 1:0;
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assign empty = (wr_ptr == rd_ptr) ? 1:0;
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endmodule
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