2025-08-06 13:42:13 +08:00
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Chronologic VCS (TM)
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2025-08-06 22:43:11 +08:00
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Version O-2018.09-1_Full64 -- Wed Aug 6 22:32:17 2025
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2025-08-06 13:42:13 +08:00
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Copyright (c) 1991-2018 by Synopsys Inc.
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ALL RIGHTS RESERVED
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This program is proprietary and confidential information of Synopsys Inc.
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and may be used and disclosed only as authorized in a license agreement
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controlling such use and disclosure.
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2025-08-06 22:43:11 +08:00
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Parsing design file '../rtl/sync_fifo_128_to_64.v'
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Parsing design file '../rtl/sync_fifo.v'
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Parsing design file '../rtl/rchannel.v'
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Parsing design file '../tb/tb_rchannel.v'
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Top Level Modules:
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tb_rchannel
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TimeScale is 1 ns / 1 ps
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Starting vcs inline pass...
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1 module and 0 UDP read.
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recompiling module tb_rchannel
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make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
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make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
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make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
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rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
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if [ -x ../simv ]; then chmod -x ../simv; fi
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g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _25796_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
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../simv up to date
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make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
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Chronologic VCS simulator copyright 1991-2018
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Contains Synopsys proprietary information.
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Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
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*Verdi* Loading libsscore_vcs201809.so
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FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
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(C) 1996 - 2019 by Synopsys, Inc.
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*Verdi* : Create FSDB file 'tb.fsdb'
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*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
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*Verdi* : Enable +all dumping.
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*Verdi* : End of traversing.
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$finish called from file "../tb/tb_rchannel.v", line 64.
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$finish at simulation time 365000
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V C S S i m u l a t i o n R e p o r t
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Time: 365000 ps
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CPU Time: 0.480 seconds; Data structure size: 0.0Mb
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Wed Aug 6 22:32:19 2025
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CPU time: .521 seconds to compile + .480 seconds to elab + .391 seconds to link + .525 seconds in simulation
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