115 lines
4.1 KiB
Coq
115 lines
4.1 KiB
Coq
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module frame_arbiter(
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input clk,
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input rst_n,
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input wframe_valid,
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input [159:0] wframe_data,
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output wframe_ready,
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input rframe_valid,
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input [159:0] rframe_data,
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output rframe_ready,
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output axi2array_frame_valid,
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output [152:0] axi2array_frame_data,
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input axi2array_frame_ready,
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input mc_work_en,
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input [1:0] axi_bus_rw_priority
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);
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reg [1:0] cur_state,next_state;
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localparam [1:0] FARB_IDLE = 2'b00;
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localparam [1:0] FARB_WR = 2'b01;
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localparam [1:0] FARB_RD = 2'b10;
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reg rw_round_robin;
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reg [6:0] frame_cnt;
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wire rw_flag;
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wire [151:0] frame;
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wire [7:0] len;
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assign axi2array_frame_valid = (cur_state == FARB_WR) && wframe_valid ||
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(cur_state == FARB_RD) && rframe_valid;
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assign axi2array_frame_data = {rw_frag,frame};
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assign wframe_ready = (cur_state == FARB_WR) && axi2array_frame_ready;
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assign rframe_ready = (cur_state == FARB_RD) && axi2array_frame_ready;
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assign rwflag = (cur_state == FARB_WR);
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assign frame = (cur_state == FARB_WR) ? wframe_data[159:8]:
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rframe_data[159:8];
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assign len = (cur_state == FARB_WR) ? wframe_data[7:0]:
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rframe_data[7:0];
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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cur_state <= 'd0;
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end else begin
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cur_state <= next_state;
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end
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end
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always@(*) begin
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case(cur_state)
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FARB_IDLE : begin
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if(wframe_valid && rframe_valid) begin
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case(axi_bus_rw_priority)
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2'b00: begin
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next_state = FARB_RD;
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end
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2'b01: begin
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next_state = FARB_WR;
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end
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2'b10: begin
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next_state = rw_round_robin ? FARB_WR : FARB_RD;
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end
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endcase
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end else if (wframe_valid) begin
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next_state = FARB_WR;
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end else if (rframe_valid) begin
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next_state = FARB_RD;
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end else begin
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next_state = FARB_IDLE;
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end
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end
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FARB_WR : begin if (axi2array_frame_valid && axi2array_frame_ready &&
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(frame_cnt == (len>>1))) begin
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next_state = FARB_IDLE;
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end else begin
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next_state = FARB_WR;
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end
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end
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FARB_RD :begin if (axi2array_frame_valid && axi2array_frame_ready &&
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(frame_cnt == (len>>1))) begin
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next_state = FARB_IDLE;
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end else begin
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next_state = FARB_RD;
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end
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end
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default : begin
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next_state = FARB_IDLE;
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end
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endcase
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rw_round_robin <= 1'b1;
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end else if(wframe_valid && rframe_valid && (cur_state == FARB_IDLE)) begin
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rw_round_robin <= ~rw_round_robin;
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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frame_cnt <= 'd0;
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end else if (axi2array_frame_valid && axi2array_frame_ready) begin
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if(frame_cnt == (len >> 1)) begin
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frame_cnt <= 'd0;
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end else begin
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frame_cnt <= frame_cnt + 1'b1;
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end
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end
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end
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endmodule
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