93 lines
49 KiB
Plaintext
93 lines
49 KiB
Plaintext
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##spyglass_version: SpyGlass_vL-2016.06
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##date: Tue Aug 5 11:15:45 2025
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##user: ICer
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##cwd: /home/ICer/ic_prjs/mc/sim
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##lang: verilog+vhdl
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##args: -mSpyGlass::Compatibility::v2_7_3 -mSpyGlass::Compatibility::v2_7_3 -mSpyGlass::Compatibility::v2_7_3 -top 'tb_wchannel' -lib WORK ./spyglass-1/tb_wchannel/WORK -nl -policy='openmore,starc,starc2005,erc,simulation,lint,latch,spyglass,morelint,timing' -mixed -batch -rules='badimplicitSM1,badimplicitSM2,badimplicitSM4,BlockHeader,bothedges,STARC05-2.1.6.5,STARC05-2.3.1.2c,W421,W442a,W442b,W442c,W442f,sim_race02,W110a,W416,CheckDelayTimescale-ML,PragmaComments-ML,STARC05-2.10.2.3,STARC05-2.11.3.1,STARC05-2.3.1.5b,W215,W216,W289,W292,W293,W317,W352,W398,W422,W424,W426,W467,W480,W481a,W481b,W496a,W496b,W71,NoAssignX-ML,NoXInCase-ML,ParamWidthMismatch-ML,ReportPortInfo-ML,STARC05-2.1.3.1,STARC05-2.1.5.3,STARC05-2.2.3.3,STARC05-2.3.1.6,W110,W116,W122,W123,W19,W218,W240,W263,W337,W362,W486,W499,W502,W505,W66,InferLatch,RegInputOutput-ML,STARC05-2.3.4.1v,STARC05-2.5.1.7,STARC05-2.5.1.9,STARC05-2.10.3.2a,W336,W414,W450L,UndrivenInTerm-ML,BufClock,checkPinConnectedToSupply,CombLoop,FlopClockConstant,FlopEConst,FlopSRConst,LatchFeedback,STARC05-1.2.1.2,STARC05-1.3.1.3,STARC05-1.4.3.4,STARC05-2.1.4.5,STARC05-2.4.1.5,STARC05-2.5.1.2,W392,W415,STARC05-2.10.1.4a,STARC05-2.10.1.4b,W156,STARC05-2.3.3.1,W415a,W287b,W224,W287a,W528,mixedsenselist,W339a,STARC05-2.10.3.2a' -wdir './spyglass-1/tb_wchannel/lint/lint_rtl' -dbdir './spyglass-1/tb_wchannel/.SG_SaveRestoreDB' -templatedir '/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff' --goal_info 'lint/lint_rtl@' --template_info 'lint/lint_rtl' -overloadrules 'STARC05-2.1.6.5+severity=Warning,STARC05-2.3.1.2c+severity=Error,W421+severity=Error,sim_race02+severity=Warning,W416+severity=Error,PragmaComments-ML+severity=Data,STARC05-2.10.2.3+severity=Warning,STARC05-2.11.3.1+severity=Warning,STARC05-2.3.1.5b+severity=Error,W289+severity=Error,W293+severity=Error,W352+severity=Error,W398+severity=Error,W422+severity=Error,W71+severity=Error,ParamWidthMismatch-ML+severity=Warning,ReportPortInfo-ML+severity=Data,STARC05-2.1.3.1+severity=Warning,STARC05-2.1.5.3+severity=Warning,STARC05-2.2.3.3+severity=Warning,STARC05-2.3.1.6+severity=Warning,W110+severity=Error,W122+severity=Error,W123+severity=Error,W19+severity=Error,W218+severity=Error,W505+severity=Error,W66+severity=Error,InferLatch+severity=Error,RegInputOutput-ML+severity=Data,STARC05-2.3.4.1v+severity=Warning,STARC05-2.5.1.7+severity=Warning,STARC05-2.5.1.9+severity=Warning,W336+severity=Error,W414+severity=Error,W450L+severity=Warning,UndrivenInTerm-ML+severity=Error,BufClock+severity=Warning,checkPinConnectedToSupply+severity=Error,CombLoop+msgLabel=CombLoop+severity=Error,FlopClockConstant+msgLabel=FlopClockConstant+severity=Error,LatchFeedback+severity=Error,STARC05-1.2.1.2+severity=Error,STARC05-1.3.1.3+severity=Warning,STARC05-1.4.3.4+severity=Warning,STARC05-2.1.4.5+severity=Warning,STARC05-2.4.1.5+severity=Error,W415+msgLabel=W415+severity=Error' -projectwdir './spyglass-1' -enable_save_restore -enable_fast_traversal -enable_save_restore_builtin 'true' -assume_driver_load=yes -checkInHierarchy=yes -checkRTLCInst=yes -checkalldimension=yes -checkconstassign=yes -checkfullbus=yes -checkfullrecord=yes -chkTopModule=yes -enableE2Q=yes -ignoreModuleInstance=yes -new_flow_width=yes -nocheckoverflow=yes -report_inferred_cell=yes -reportundrivenout=no -strict=W342,W343 -treat_latch_as_combinational=yes -64bit
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##spysch_dirname: ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_spysch
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##vdb_delimiter: @@
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##run_mode: SINGLE_WORKSPACE
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##rules: txv Txv_SvaSetup01 TxvVhMeta01
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##rules: power_est SGDC_power_est29 PECHECK04 PESVASETUP01 PECHECK09 PECHECK18 PECHECK43 PEMVDD01
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##rules: clock-reset _cdc_save_license01 Pragma_setupa syncRstReq syncRstReq Reset_check05 _syncResetStyleRTL _deltaDelay _deltaDelay Ac_multitop01 SGDC_meta_design_hier01 _vhMeta01 _meta_delay01 AcOvlRtl AcOvlRtl Ac_svasetup01
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##rules: openmore preReq_ConsCase2 InferLatch Prereqs_RegOutputs BufClock CombLoop
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##rules: starc preReq_ConsCase Prereqs_STARC-2.3.6.1 Prereqs_STARC-1.6.2.1 STARC-1.3.2.2_prereq
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##rules: starc2005 STARC05-AlwaysParamSetup STARC05-ProcessParamSetup STARC05-2.1.4.5 STARC05-2.1.5.3 STARC05-2.2.3.3 STARC05-2.3.1.5b STARC05-2.3.1.6 STARC05-2.3.3.1 STARC05-2.10.2.3 STARC05-2.10.3.2a STARC05-2.11.3.1 STARC05-2.3.3.1 STARC05-2.11.3.1 Prereqs_STARC05-1.6.2.1 STARC05-2.5.1.2 STARC05-1.3.1.3 STARC05-1.4.3.4 STARC05-2.1.3.1 STARC05-2.3.1.2c STARC05-2.10.1.4a STARC05-2.10.1.4b STARC05-2.3.4.1v STARC05-2.5.1.7 STARC05-2.5.1.7 STARC05-2.4.1.5 STARC05-1.2.1.2 STARC05-2.1.6.5 STARC05-2.5.1.9
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##rules: lint LINT_portReten Prereqs_RTLSchematic W339a W442a W442b W442c W442f mixedsenselist badimplicitSM1 badimplicitSM2 badimplicitSM4 bothedges W110 W122 W496a W496b W19 W66 W116 W123 W156 W215 W216 W218 W224 W263 W289 W317 W337 W352 W362 W415a W422 W426 W480 W481a W481b W486 W499 W502 W336 W414 W422 BlockHeader W116 W122 W123 W156 W292 W416 mixedsenselist W110a W71 W71 W240 W240 W287a W287a W287b W287b W293 W293 W398 W398 W421 W421 W424 W424 W467 W467 W505 W505 W528 W528 W392 W415 Prereqs_Usage Postreqs_CheckFuncTask
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##rules: latch Latch_VePreReqRule LatchFeedback W450L
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##rules: timing LogNMuxPrereq
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##rules: SpyGlass DetectTopDesignUnits InferBlackBox InfoAnalyzeBBox WarnAnalyzeBBox ErrorAnalyzeBBox FatalAnalyzeBBox AnalyzeBBox GenTopLevelBlocksForAutoSoc PrecompileLibCheck01 PrecompileLibCheck02 PrecompileLibCheck03 PrecompileLibCheck04 ReportStopSummary ReportIgnoreSummary SortVhdlFiles SimonRunSummary IgnoredLibCells ReportCheckDataSummary ElabSummary ReportObsoletePragmas InfoSglibVersionSummary FatalSglibVersionSummary ReportMissingLibCell ReportMissingMacro ReportUnusedMacroPin ReportMissingMacroPin ReportDuplicateMacro InvalidLefBusPinIndex ReportDuplicateLibrary GenerateOptData CheckCelldefine ReportSpyGlassOperatingMode ReportAbortReason ReportUngroup IgnoreGenBlockOpt IgnoreHboOption ReportDuplicateIpdbdir ReportBadIpdbdir ReportGenBlockOptError AutoGenerateSglib RuleTerminatedAbnormally SGDCSTX_001 SGDCSTX_002 SGDCSTX_003 SGDCSTX_004 SGDCSTX_005 SGDCSTX_006 SGDCSTX_007 SGDCSTX_008 SGDCSTX_009 SGDCSTX_010 SGDCSTX_011 SGDCSTX_012 SGDCSTX_013 SGDCSTX_014 SGDCSTX_015 SGDCSTX_016 SGDCWRN_111 SGDCSTX_018 SGDCSTX_019 SGDCSTX_020 SGDCSTX_021 SGDCSTX_022 SGDCSTX_023 SGDCSTX_024 SGDCSTX_025 SGDCSTX_026 SGDCSTX_027 SGDCSTX_028 SGDCSTX_029 SGDCSTX_030 SGDCSTX_031 SGDCSTX_032 SGDCSTX_033 SGDCSTX_034 SGDCSTX_035 SGDCSTX_036 SGDCSTX_037 SGDCSTX_038 SGDCSTX_039 SGDCSTX_040 SGDCSTX_041 SGDCSTX_042 SGDCSTX_043 SGDCSTX_044 SGDCSTX_045 SGDCWRN_101 SGDCWRN_102 SGDCWRN_103 SGDCWRN_104 SGDCWRN_105 SGDCWRN_107 SGDCWRN_108 SGDCWRN_109 SGDCWRN_110 SGDCWRN_112 SGDCWRN_113 SGDCWRN_114 SGDCWRN_115 SGDCWRN_117 SGDCWRN_118 SGDCWRN_119 SGDCWRN_120 SGDCWRN_121 SGDCWRN_122 SGDCWRN_123 SGDCWRN_124 SGDCWRN_125 SGDCINFO_201 SGDCINFO_202 SGDC_pgcell01 SGDCERR_302 checkSGDC_existence checkSGDC_value checkSGDC_wildCardMatch checkSGDC_fileSanityCheck checkSGDC_FileReadError checkSGDC_nottogether checkSGDC_nottogether01 checkSGDC_nottogether02 checkSGDC_nottogether03 checkSGDC_nottogether04 checkSGDC_together checkSGDC_together01 checkSGDC_together02 checkSGDC_together03 checkSGDC_together04 checkSGDC_01 checkSGDC_03 checkSGDC_04 checkSGDC_05 checkSGDC_06 checkSGDC_07 checkSGDC_08 GenerateConfMap SGDC_asyncdisable01 SGDC_asyncdisable02 SGDC_assume_path01 SGDC_assume_path02 SGDC_assume_path03 SGDC_assume_path04 SGDC_assume_connection01 SGDC_assume_connection02 SGDC_assume_connection03 SGDC_assume_connection04 SGDC_sdcschema02 SGDC_balancedClock01 SGDC_blackBox01 SGDC_bypass01 SGDC_clock01 SGDC_clock02 SGDC_clock03 SGDC_clock04 SGDC_clock05 SGDC_clock08 SGDC_clock09 SGDC_clock_pin01 SGDC_clock_pin02 SGDC_define_tag01 SGDC_define_tag02 SGDC_force_ta01 SGDC_force_ta02 SGDC_force_ta03 SGDC_force_ta04 SGDC_force_ta05 SGDC_initForBist01 SGDC_initForBist02 SGDC_keeper01 SGDC_keeper02 SGDC_keeper03 SGDC_memorytype01 SGDC_memoryforce01 SGDC_memoryforce02 SGDC_memoryreadpin01 SGDC_memoryreadpin02 SGDC_memoryreadpin03 SGDC_memorywritedisable01 SGDC_memorywritedisable02 SGDC_memorywritepin01 SGDC_memorywritepin02 SGDC_memorywritepin04 SGDC_memorywritepin03 SGDC_memory3s01 SGDC_memory3s02 SGDC_memory3s03 SGDC_nofault01 SGDC_noScan01 SGDC_noScan02 SGDC_scan01 SGDC_scan02 SGDC_pullDown01 SGDC_pullDown02 SGDC_pullDown03 SGDC_pullUp01 SGDC_pullUp02 SGDC_pullUp03 SGDC_allowedPath01 SGDC_allowedPath02 SGDC_allowedPath03 SGDC_require_path01 SGDC_require_path02 SGDC_require_path03 SGDC_require_value01 SGDC_require_value02 SGDC_require_value03 SGDC_reset01 SGDC_reset02 SGDC_reset03 SGDC_reset04 SGDC_reset_pin01 SGDC_reset_pin02 SGDC_scanchain01 SGDC_scanchain02 SGDC_scanchain03 SGDC_scanenable01 SGDC_scanin01 SGDC_scanin02 SGDC_scanin03 SGDC_scanin04 SGDC_scanout01 SGDC_scanout02 SGDC_scanout03 SGDC_scanout04 SGDC_scanratio01 SGDC_scanwrap01 SGDC_scanwrap03 SGDC_scanwrap02 SGDC_scanwrap04 SGDC_set01 SGDC_set02 SGDC_set_pin01 SGDC_set_pin02 SGDC_shiftmode01 SGDC_shiftmode02 SGDC_shiftmode03 SGDC_shiftmode04 SGDC_testmode01 SGDC_testmode02 SGDC_testmode03 SGDC_testpoint01 SGDC_testpoint02 SGDC_testpoint03 SGDC_set_case_analysis01 SGDC_set_case_analysis02 SGDC_block01 SGDC_syncclock01 SGDC_syncclock02 SGDC_clockgating01 SGDC_clockgating02 SGDC_clockgating03 SGDC_domain_o
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##rules: erc FlopClockConstant FlopSRConst FlopEConst checkPinConnectedToSupply
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##rules: simulation sim_race02
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##rules: morelint HangingNetPreReq-ML UndrivenInTerm-ML Prereqs_ConstantInput-ML Prereqs_ConstantInput-ML Prereqs_RegInputOutputs RegInputOutput-ML ReportPortInfo-ML PragmaComments-ML PragmaComments-ML NoAssignX-ML ParamWidthMismatch-ML CheckDelayTimescale-ML Prereqs_InclFileSetup-ML Postreqs_Usage_ML NoXInCase-ML
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##sde_property: rule Sanity_Rule -policy const_intern1 -highProfile
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##sde_property: rule Const_Prelim_SDCCHECK -policy const_intern1 -highProfile
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##sde_property: rule DetectTopDesignUnits -policy SpyGlass -highProfile
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##sde_property: rule AnalyzeBBox -policy SpyGlass -highProfile
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##MESSAGESORT -rule Ac_abstract_validation01 -language Verilog+VHDL -arg1 STRING:ASCENDING -message
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##MESSAGESORT -rule Reset_info01 -language Verilog+VHDL -arg2 STRING:ASCENDING -message Candidate %3: %1 of type %2 %3
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##MESSAGESORT -rule Clock_info01 -language Verilog+VHDL -arg2 STRING:ASCENDING -message Candidate clock: %1 of type: %2 Clock
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##MESSAGESORT -rule Soc_05 -language Verilog+VHDL -NOSORT -message %1
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##MESSAGESORT -rule TA_09 -language Verilog+VHDL -NOSORT -message Net '%1' %2[Fault Improvement = '%3'[%%Increase %4]]
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##MESSAGESORT -rule Topology_09 -language Verilog+VHDL -NOSORT -message [Reconvergence Depth %3]Logic path from '%1' re-converges at or near '%2'
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##MESSAGESORT -rule TA_02 -language Verilog+VHDL -NOSORT -message Net '%1' %2[Observability Improvement = '%3']
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##MESSAGESORT -rule TA_01 -language Verilog+VHDL -NOSORT -message Net '%1' %2[Controllability Improvement = '%3']
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##MESSAGESORT -rule Info_scanwrap -language Verilog+VHDL -NOSORT -message DUMMY
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##MESSAGESORT -rule Clock_11_capture -language Verilog+VHDL -NOSORT -message %2 '%1' [in '%3'] is not controlled %4 %5%6
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##MESSAGESORT -rule Clock_11 -language Verilog+VHDL -NOSORT -message %2 '%1' [in '%3'] is not controlled %4 %5%6
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##MESSAGESORT -rule Async_13 -language Verilog+VHDL -NOSORT -message The source net '%1' feeding '%2' pin of '%3' is not controllable to inactive state in capture mode%4
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##MESSAGESORT -rule Async_09 -language Verilog+VHDL -NOSORT -message The source net '%1' feeding '%2' pin of '%3' is not fully controllable in capture mode%4
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##MESSAGESORT -rule Async_07 -language Verilog+VHDL -NOSORT -message %2[in '%3'] '%1' is not disabled for %5 in test-mode[stops at '%4']%6
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##MESSAGESORT -rule Atspeed_11 -language Verilog+VHDL -arg4 NUMBER:DESCENDING -message Clock domain '%1' [in '%2'] is not controlled by %3 in capture-atspeed mode (%4 flipflop(s) affected). %5.%6
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##MESSAGESORT -rule Atspeed_09 -language Verilog+VHDL -arg3 NUMBER:DESCENDING -message Net %1 is root cause of uncontrollability [%2], %3 scan flip-flop(s) affected
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##MESSAGESORT -rule Atspeed_01 -language Verilog+VHDL -NOSORT -message Clock source '%s' does not get atspeed clock through a PLL (%d flip-flops affected)
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##MESSAGESORT -rule PECHECK11 -language Verilog+VHDL -arg1 STRING:ASCENDING -message %1 %2
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##MESSAGESORT -rule PEPWR02 -language Verilog+VHDL -arg1 STRING:DESCENDING -message %1 %2
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##MESSAGESORT -rule PEPWR01 -language Verilog+VHDL -arg1 STRING:DESCENDING -message %1 %2
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##MESSAGESORT -rule PRFIFOS01 -language Verilog+VHDL -NOSORT -message FIFO(s) have been reported in the spreadsheet
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##MESSAGESORT -rule PRARITH01 -language Verilog+VHDL -NOSORT -message Arithmetic operator(s) have been reported in the spreadsheet
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##MESSAGESORT -rule PEPWR14 -language Verilog+VHDL -NOSORT -message
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##MESSAGESORT -rule PESTR05 -language Verilog+VHDL -NOSORT -message
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##MESSAGESORT -rule PEPWR05 -language Verilog+VHDL -NOSORT -message Clock gated path for register(s) '%1' has been highlighted
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##MESSAGESORT -rule PESTR03 -language Verilog+VHDL -NOSORT -message Clock Gated Path for register(s): '%1' highlighted
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##MESSAGESORT -rule PEPWR03 -language Verilog+VHDL -NOSORT -message Clock gated path for register(s) '%1' has been highlighted
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##MESSAGESORT -rule PESAE02 -language Verilog+VHDL -NOSORT -message [Simulation file : %1, Start time : %2, End time : %3] The net(s) %4.%5 do not attain a fixed value for a duration %6 units as detected from the activity data
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##MESSAGESORT -rule PEPWR13 -language Verilog+VHDL -NOSORT -message Non-gated register(s) '%s' for clock '%s' have been highlighted
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##MESSAGESORT -rule PESTR13 -language Verilog+VHDL -NOSORT -message Non gated register(s) '%s' for clock '%s' have been highlighted
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##MESSAGESORT -rule LogicDepth -language Verilog+VHDL -arg6 NUMBER:DESCENDING -message %1Logic delay from %2 %3 to %4 %5 (%6 levels) exceeds allowed max (%7)
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##file_label: Modulecombloop_report -file ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/openmore/CombLoopReport.rpt -policy openmore -external
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##file_label: multidim_array_data -file ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/lint/SignalUsageReport.rpt -policy lint -external
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##file_label: multidim_array_data -file ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/lint/SignalUsageReport.rpt -policy lint -external
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##file_label: morelint_ReportPortInfo -file ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/morelint/ReportPortInfo -policy morelint -external
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##file_label: SPG_ELAB_SUMMARY_FILE -file ./spyglass-1/tb_wchannel/lint/lint_rtl/spyglass_reports/SpyGlass/elab_summary.rpt -policy SpyGlass -external
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##files_verilog: ../tb/tb_wchannel.v ../rtl/wchannel.v ../rtl/sync_fifo.v ../rtl/sync_fifo_64_to_128.v
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##sde_property: file /home/ICer/ic_prjs/mc/rtl/sync_fifo_64_to_128.v -id 1
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##sde_property: file /home/ICer/ic_prjs/mc/rtl/sync_fifo.v -id 2
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##sde_property: file /home/ICer/ic_prjs/mc/rtl/wchannel.v -id 3
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##sde_property: file /home/ICer/ic_prjs/mc/tb/tb_wchannel.v -id 4
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#span tb_wchannel ../tb/tb_wchannel.v 1 110
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#rtl_idmap tb_wchannel 1 -lang 1
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#span wchannel ../rtl/wchannel.v 1 169
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#rtl_idmap wchannel 2 -lang 1
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#span sync_fifo ../rtl/sync_fifo.v 1 62
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#rtl_idmap sync_fifo 3 -lang 1
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#span sync_fifo_64_to_128 ../rtl/sync_fifo_64_to_128.v 1 62
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#rtl_idmap sync_fifo_64_to_128 4 -lang 1
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#greybox tb_wchannel 15
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#greybox wchannel 15
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#greybox sync_fifo 15
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#greybox sync_fifo_64_to_128 15
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#rtl_top_modules tb_wchannel
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#childElab tb_wchannel tb_wchannel -elabDuId 1 u_wchannel wchannel
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#child sync_fifo_64_to_128 sync_fifo_64_to_128 sync_fifo_64_to_128 -elabDuId 4
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#child sync_fifo sync_fifo sync_fifo -elabDuId 3
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#child wchannel wchannel wchannel -elabDuId 2 sync_fifo_aw sync_fifo sync_fifo_w sync_fifo_64_to_128
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#top_modules
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#bbox_modules
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##totalGeneratedCount: 27
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##totalWaivedViolationCount: 0
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##totalReportCount: 27
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##totalDataSeverityCount: 1
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##totalSuppressedCount: 0
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##Active_Rules BlockHeader BufClock CheckDelayTimescale-ML CombLoop FlopClockConstant FlopEConst FlopSRConst InferLatch LatchFeedback NoAssignX-ML NoXInCase-ML ParamWidthMismatch-ML STARC05-1.2.1.2 STARC05-1.3.1.3 STARC05-1.4.3.4 STARC05-2.1.3.1 STARC05-2.1.4.5 STARC05-2.1.5.3 STARC05-2.1.6.5 STARC05-2.10.1.4a STARC05-2.10.1.4b STARC05-2.10.2.3 STARC05-2.10.3.2a STARC05-2.11.3.1 STARC05-2.2.3.3 STARC05-2.3.1.2c STARC05-2.3.1.5b STARC05-2.3.1.6 STARC05-2.3.3.1 STARC05-2.3.4.1v STARC05-2.4.1.5 STARC05-2.5.1.2 STARC05-2.5.1.7 STARC05-2.5.1.9 UndrivenInTerm-ML W110 W110a W116 W122 W123 W156 W19 W215 W216 W218 W224 W240 W263 W287a W287b W289 W292 W293 W317 W336 W337 W339a W352 W362 W392 W398 W414 W415 W415a W416 W421 W422 W424 W426 W442a W442b W442c W442f W450L W467 W480 W481a W481b W486 W496a W496b W499 W502 W505 W528 W66 W71 badimplicitSM1 badimplicitSM2 badimplicitSM4 bothedges checkPinConnectedToSupply mixedsenselist sim_race02
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