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IC_PRJ/tb/tb_apb_cfg.v

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module tb_apb_cfg;
reg apb_pclk;
reg apb_prstn;
//from apb master
reg apb_psel;
reg apb_penable;
reg apb_pwrite;
reg [7:0] apb_paddr;
reg [31:0] apb_wdata;
//to apb master
wire [31:0] apb_rdata;
wire apb_pready;
//cfg
//mode ctrl
wire mc_work_en;
wire [1:0] axi_rw_priority;
//
wire [7:0] array_ras_cfg;
wire [7:0] array_rp_cfg;
wire [7:0] array_rc_cfg;
//
wire [7:0] array_rcd_wr_cfg;
wire [7:0] array_wr_cfg;
//
wire [7:0] array_rcd_rd_cfg;
wire [7:0] array_rtp_cfg;
//
wire [25:0] array_ref_period0;
wire [25:0] array_ref_period1;
wire array_ref_sel;
apb_cfg u_apb_cfg(
.apb_pclk(apb_pclk),
.apb_prstn(apb_prstn),
.apb_psel(apb_psel),
.apb_penable(apb_penable),
.apb_pwrite(apb_pwrite),
.apb_paddr(apb_paddr),
.apb_wdata(apb_wdata),
.apb_rdata(apb_rdata),
.apb_pready(apb_pready),
.mc_work_en(mc_work_en),
.axi_rw_priority(axi_rw_priority),
.array_ras_cfg(array_ras_cfg),
.array_rp_cfg(array_rp_cfg),
.array_rc_cfg(array_rc_cfg),
.array_rcd_wr_cfg(array_rcd_wr_cfg),
.array_wr_cfg(array_wr_cfg),
.array_rcd_rd_cfg(array_rcd_rd_cfg),
.array_rtp_cfg(array_rtp_cfg),
.array_ref_period0(array_ref_period0),
.array_ref_period1(array_ref_period1),
.array_ref_sel(array_ref_sel)
);
initial begin
apb_pclk = 1'b0;
apb_prstn = 1'b0;
#20
apb_prstn = 1'b1;
end
always #10 apb_pclk = ~apb_pclk;
initial begin
apb_psel = 1'b0;
apb_penable = 1'b0;
apb_pwrite = 1'b0;
apb_paddr = 'b0;
apb_wdata = 'b0;
end
//task wr
task apb_wr;
input apb_paddr_temp;
input apb_wdata_temp;
begin
wait(apb_pready);
@(negedge apb_pclk);
apb_paddr = apb_paddr_temp;
apb_wdata = apb_wdata_temp;
apb_psel = 1'b1;
apb_pwrite = 1'b1;
apb_penable = 1'b0;
@(posedge apb_pclk);
#0.7
apb_penable = 1'b1;
wait(apb_pready);
@(posedge apb_pclk);
apb_psel = 1'b0;
apb_pwrite = 1'b0;
apb_penable = 1'b0;
end
endtask
initial begin
#50
apb_wr(8'h00,{31'b0,1'b1});
$finish;
end
endmodule