86 lines
2.3 KiB
Coq
86 lines
2.3 KiB
Coq
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module async_fifo #(
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parameter DATA_WIDTH = 8,
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parameter FIFO_DEPTH = 16
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)(
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input wr_clk,
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input wr_rst_n,
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input wr_en,
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input [DATA_WIDTH-1:0] wr_data,
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output full,
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input rd_clk,
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input rd_rst_n,
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input rd_en,
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output [DATA_WIDTH-1:0] rd_data,
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output empty
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);
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reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
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reg [$clog2(FIFO_DEPTH) : 0] wr_ptr, rd_ptr;
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integer i;
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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wr_ptr <= 'd0;
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for(i=0;i<FIFO_DEPTH;i=i+1) begin
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mem[i] <= 'd0;
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end
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end else if(wr_en && !full) begin
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mem[wr_ptr[$clog2(FIFO_DEPTH)-1:0]] <= wr_data;
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wr_ptr <= wr_ptr + 1'b1;
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end else begin
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wr_ptr <= wr_ptr;
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end
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end
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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rd_ptr <= 'd0;
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end else if(rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'b1;
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end else begin
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rd_ptr <= rd_ptr;
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end
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end
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wire [$clog2(FIFO_DEPTH):0] wr_ptr_g , rd_ptr_g;
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assign wr_ptr_g = wr_ptr ^(wr_ptr >>1);
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assign rd_ptr_g = rd_ptr ^(rd_ptr >>1);
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reg [$clog2(FIFO_DEPTH):0] wr_ptr_gr , wr_ptr_grr;
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reg [$clog2(FIFO_DEPTH):0] rd_ptr_gr , rd_ptr_grr;
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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wr_ptr_gr <= 0;
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wr_ptr_grr <=0;
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end else begin
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wr_ptr_gr <= wr_ptr_g;
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wr_ptr_grr <= wr_ptr_gr;
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end
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end
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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rd_ptr_gr <= 0;
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rd_ptr_grr <=0;
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end else begin
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rd_ptr_gr <= rd_ptr_g;
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rd_ptr_grr <= rd_ptr_gr;
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end
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end
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assign rd_data = mem[rd_ptr[$clog2(FIFO_DEPTH)-1:0]];
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assign full = ((wr_ptr_g[$clog2(FIFO_DEPTH)] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]) && (wr_ptr_g[$clog2(FIFO_DEPTH)-1] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]-1) && (wr_ptr_g[$clog2(FIFO_DEPTH)-2:0] ==
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rd_ptr_grr[$clog2(FIFO_DEPTH)-2 : 0])) ? 1:0;
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assign empty = (rd_ptr_g[$clog2(FIFO_DEPTH) : 0] ==
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wr_ptr_grr[$clog2(FIFO_DEPTH) :0]) ? 1:0;
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endmodule
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