v1.0
This commit is contained in:
Core_kingdom
202
sim/verdiLog/sim.log
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202
sim/verdiLog/sim.log
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Command: /home/ICer/ic_prjs/mc/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
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Chronologic VCS simulator copyright 1991-2018
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Contains Synopsys proprietary information.
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Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
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ucli% synUtils::getArch
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linux64
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ucli% loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd
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LoadFSDBDumpCmd success
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ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/sim/inter.fsdb} ;fsdbDumpflush ;
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*Verdi* Loading libsscore_vcs201809.so
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FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
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(C) 1996 - 2019 by Synopsys, Inc.
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*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
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*Verdi* : Flush all FSDB Files at 0 ps.
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ucli% sps_interactive
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*Verdi* : Enable RPC Server(12621)
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ucli% ucliCore::getToolPID
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12621
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ucli% ucliCore::getToolPID
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12621
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% puts $ucliCore::nativeUcliMode
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0
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ucli% ucliCore::getToolTopPID
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12621
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ucli% pid
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12635
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ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.12621 }
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ucli% if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024}
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1024
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ucli% info command stateVerdiChangeCB
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ucli% proc stateVerdiChangeCB args { if {$ucliGUI::state eq "terminated"} {puts "\nVERDI_SIM_Terminated\n";catch {setVerdiSimTerminated}}}
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ucli% trace variable ucliGUI::state wu stateVerdiChangeCB
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ucli% if {[catch {rename synopsys::restore verdiHack::restore} ]} {puts "0"}
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ucli% proc synopsys::restore {args} { verdiHack::restore $args; puts "\nVERDI_SIM_RESTORE\n"}
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ucli% if {[catch {rename quit verdiHack::quit} ]} {puts "0"}
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ucli% proc quit {args} { if {[string length $args] == 0} { verdiHack::quit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n quit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::quit $args; } }
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ucli% if {[catch {rename exit verdiHack::exit} ]} {puts "0"}
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ucli% proc exit {args} { if {[string length $args] == 0} { verdiHack::exit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n exit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::exit $args; } }
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ucli% proc checkpoint::beforeRecreate {} { sps_interactive }
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% save::getUserdefinedProcs
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::stateVerdiChangeCB ::LoadFSDBDumpCmd
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ucli% info procs
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ipi_get_str fsdbDumpMDAByFile fsdbDumpMDA echo fsdbDumpMemNow fsdbAutoSwitchDumpfile unknown sps_interactive auto_import stat fsdbDumpfile setenv auto_execok pkg_mkIndex stateVerdiChangeCB fsdbDumpSingle proc_body ipi_begin fsdbDumpoff getenv fsdbDumplimit fsdbDumpPattern ipi_handle fsdbDumpvarsByFile fsdbDumpMDAInScope lminus ipi_sim_get interp ls auto_load_index proc_args fsdbAddRuntimeSignal fsdbDumpSC print_message_info ridbDump fsdbDumpSVAoff fsdbSuppress fsdbDumpvars help fsdbDumpMDAOnChange ipi_control auto_qualify fsdbDumpMem tclPkgUnknown printenv ipi_handle_by_name helpdoc fsdbDumpMemInScope fsdbDumpFinish is_true fsdbDumpon sh fsdbQueryInfo puts LoadFSDBDumpCmd fsdbDumpPSL fsdbDumpSVA ipi_end wrapperSpecmanSn fsdbDumpSVAon fsdbDumpClassObjectByFile is_false auto_load fsdbDumpPSLon ipi_get_int64 fsdbSubstituteHier ipi_get_value ipi_iterate exit fsdbDumpMemInFile tclLog fsdbDumpflush get_unix_variable mem_debug ipi_scan fsdbDumpPSLoff fsdbDumpClassObject fsdbDumpvarsToFile set_unix_variable bgerror fsdbDumpStrength clock add_group fsdbSwitchDumpfile source add_wave unsetenv fsdbDumpvarsES readline fsdbDisplay ipi_handle_free set_group ipi_get quit define_proc_attributes tclPkgSetup fsdbDumpMDANow ipi_init_play_tcl fsdbDumpIO
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ucli% lappend ucliCore::resultTagsForVerdi <?special_verdi_begin?> <?special_verdi_end?>
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<?special_verdi_begin?> <?special_verdi_end?>
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
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*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
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*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
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*Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
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*Verdi* : Dumping the signal (tb_rchannel.clk).
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*Verdi* : Dumping the signal (tb_rchannel.rframe_data).
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*Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
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*Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
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*Verdi* : Dumping the signal (tb_rchannel.rst_n).
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ucli% fsdbDumpflush
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*Verdi* : Flush all FSDB Files at 0 ps.
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% fsdbDumpflush
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*Verdi* : Flush all FSDB Files at 0 ps.
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ucli% senv
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activeDomain: Verilog
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activeFile: ../tb/tb_rchannel.v
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activeFrame:
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activeLine: 1
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activeScope: tb_rchannel
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activeThread:
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endCol: 0
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file: ../tb/tb_rchannel.v
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frame:
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fsdbFilename:
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hasTB: 0
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inputFilename:
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keyFilename: ucli.key
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line: 1
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logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
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macroIndex: -1
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macroOffset: -1
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pid: 12621
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scope: tb_rchannel
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startCol: 0
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state: stopped
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thread:
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time: 0
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timePrecision: 1 ps
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vcdFilename:
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vpdFilename:
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ucli% synUtils::resolveSourceFilename ../tb/tb_rchannel.v
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../tb/tb_rchannel.v
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ucli% puts $::ucliCore::cbug_active
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0
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% checkpoint -list -all
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There are no checkpoints present.
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% stop
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No stop points are set
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% run
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*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
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*Verdi* : Enable +all dumping.
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*Verdi* : End of traversing.
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$finish called from file "../tb/tb_rchannel.v", line 64.
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$finish at simulation time 365000
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Simulation complete, time is 365000 ps.
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tb_rchannel.v, 1 : module tb_rchannel;
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ucli% synEnv::hasFataled
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0
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ucli% ucliCore::getToolPID
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12621
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ucli% save::getUserdefinedProcs
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::stateVerdiChangeCB ::LoadFSDBDumpCmd
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% fsdbDumpflush
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*Verdi* : Flush all FSDB Files at 365,000 ps.
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ucli% senv
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activeDomain: Verilog
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activeFile: ../tb/tb_rchannel.v
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activeFrame:
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activeLine: 1
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activeScope: tb_rchannel
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activeThread:
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endCol: 0
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file: ../tb/tb_rchannel.v
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frame:
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fsdbFilename:
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hasTB: 0
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inputFilename:
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keyFilename: ucli.key
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line: 1
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logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
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macroIndex: -1
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macroOffset: -1
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pid: 12621
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scope: tb_rchannel
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startCol: 0
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state: stopped
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thread:
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time: 365000
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timePrecision: 1 ps
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vcdFilename:
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vpdFilename:
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ucli% synUtils::resolveSourceFilename ../tb/tb_rchannel.v
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../tb/tb_rchannel.v
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ucli% puts $::ucliCore::cbug_active
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0
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% checkpoint -list -all
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There are no checkpoints present.
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% stop
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No stop points are set
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ucli% if {[catch {ucliCore::setFocus tool}]} {}
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ucli% finish; quit
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V C S S i m u l a t i o n R e p o r t
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Time: 365000 ps
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CPU Time: 0.200 seconds; Data structure size: 0.0Mb
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Tue Aug 5 22:01:50 2025
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VERDI_SIM_Terminated
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