v1.0

tb/tb_async_fifo.v

@@ -0,0 +1,114 @@
+`timescale 1ns/1ps
+module tb_async_fifo;
+parameter DATA_WIDTH = 8;
+parameter FIFO_DEPTH = 16;
+
+reg wr_clk;
+reg rd_clk;
+reg wr_rst_n;
+reg rd_rst_n;
+reg wr_en;
+reg [DATA_WIDTH -1:0] wr_data;
+wire full;
+reg rd_en;
+wire [DATA_WIDTH -1:0] rd_data;
+wire empty;
+
+async_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .FIFO_DEPTH(FIFO_DEPTH)
+) u_async_fifo(
+    .wr_clk(wr_clk),
+    .wr_rst_n(wr_rst_n),
+    .rd_clk(rd_clk),
+    .rd_rst_n(rd_rst_n),
+    .wr_en(wr_en),
+    .wr_data(wr_data),
+    .full(full),
+    .rd_en(rd_en),
+    .rd_data(rd_data),
+    .empty(empty)
+);
+
+initial begin
+    wr_clk = 0;
+    rd_clk = 0;
+    forever begin
+        #20;
+        wr_clk = ~wr_clk;
+    end
+end
+
+initial begin
+    forever begin
+        #10;
+        rd_clk = ~rd_clk;
+    end
+end
+initial begin
+init;
+push;
+pop;
+$fsdbDumpfile("tb.fsdb");
+$fsdbDumpvars(0,tb_async_fifo,"+all");
+#100;
+$finish;
+end
+
+task init;
+begin
+    wr_rst_n = 0;
+    rd_rst_n = 0;
+    @(posedge wr_clk);
+    @(posedge rd_clk);
+    #1;
+    wr_rst_n = 1'b1;
+    rd_rst_n = 1'b1;
+
+    wr_en = 'b0;
+    wr_data = 'd0;
+    rd_en = 'b0;
+end
+endtask
+
+integer i;
+task push;
+begin
+for(i=0;i<=20;i=i+1) begin
+@(posedge wr_clk) begin
+    wr_data <= {$random}%DATA_WIDTH  + 5'd20;
+    wr_en <= 1;
+    if(!full) begin
+    $display("write data is %0d",wr_data);
+    end else begin
+    $display("fifo is full!");
+    end
+end
+end
+wr_en <= 0;
+end
+endtask
+
+task pop;
+begin
+for(i=0;i<=20;i=i+1) begin
+    @(posedge rd_clk) begin
+        rd_en <= 1;
+        if(!empty) begin
+        $display("read data is %0d",rd_data);
+        end else begin
+        $display("fifo is empty!");
+        end
+    end
+end
+rd_en = 0;
+end
+endtask
+
+
+
+
+endmodule
+
+
+