v1.0

rtl/async_fifo.v

@@ -0,0 +1,85 @@
+module async_fifo #(
+    parameter DATA_WIDTH = 8,
+    parameter FIFO_DEPTH  = 16
+)(
+    input wr_clk,
+    input wr_rst_n,
+    input wr_en,
+    input [DATA_WIDTH-1:0] wr_data,
+    output full,
+
+    input rd_clk,
+    input rd_rst_n,
+    input rd_en,
+    output [DATA_WIDTH-1:0] rd_data,
+    output empty
+);
+
+    reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
+    reg [$clog2(FIFO_DEPTH) : 0] wr_ptr, rd_ptr;
+    
+    integer i;
+    always@(posedge wr_clk or negedge wr_rst_n) begin
+        if(!wr_rst_n) begin
+            wr_ptr <= 'd0;
+            for(i=0;i<FIFO_DEPTH;i=i+1) begin
+                    mem[i] <= 'd0;
+                end
+        end else if(wr_en && !full) begin
+            mem[wr_ptr[$clog2(FIFO_DEPTH)-1:0]] <= wr_data;
+            wr_ptr <= wr_ptr + 1'b1;
+        end else begin
+            wr_ptr <= wr_ptr;
+        end
+    end
+
+    always@(posedge rd_clk or negedge rd_rst_n) begin
+        if(!rd_rst_n) begin
+            rd_ptr <= 'd0;
+        end else if(rd_en && !empty) begin
+              rd_ptr <= rd_ptr + 1'b1;
+        end else begin
+            rd_ptr <= rd_ptr;
+        end
+    end
+
+    wire [$clog2(FIFO_DEPTH):0] wr_ptr_g , rd_ptr_g;
+
+    assign wr_ptr_g = wr_ptr ^(wr_ptr >>1);
+    assign rd_ptr_g = rd_ptr ^(rd_ptr >>1);
+
+    reg [$clog2(FIFO_DEPTH):0] wr_ptr_gr , wr_ptr_grr;
+    reg [$clog2(FIFO_DEPTH):0] rd_ptr_gr , rd_ptr_grr;
+
+    always@(posedge rd_clk or negedge rd_rst_n) begin
+        if(!rd_rst_n) begin
+            wr_ptr_gr <= 0;
+            wr_ptr_grr <=0;
+        end else begin
+            wr_ptr_gr <= wr_ptr_g;
+            wr_ptr_grr <= wr_ptr_gr;
+        end
+    end
+
+    always@(posedge wr_clk or negedge wr_rst_n) begin
+        if(!wr_rst_n) begin
+            rd_ptr_gr <= 0;
+            rd_ptr_grr <=0;
+        end else begin
+            rd_ptr_gr <= rd_ptr_g;
+            rd_ptr_grr <= rd_ptr_gr;
+        end
+    end
+    
+    assign rd_data = mem[rd_ptr[$clog2(FIFO_DEPTH)-1:0]];
+
+
+    assign full = ((wr_ptr_g[$clog2(FIFO_DEPTH)] != 
+        rd_ptr_grr[$clog2(FIFO_DEPTH)]) && (wr_ptr_g[$clog2(FIFO_DEPTH)-1] !=
+        rd_ptr_grr[$clog2(FIFO_DEPTH)]-1) && (wr_ptr_g[$clog2(FIFO_DEPTH)-2:0] ==
+        rd_ptr_grr[$clog2(FIFO_DEPTH)-2 : 0])) ? 1:0;
+
+    assign empty = (rd_ptr_g[$clog2(FIFO_DEPTH) : 0] == 
+        wr_ptr_grr[$clog2(FIFO_DEPTH) :0]) ? 1:0;
+
+endmodule

rtl/rchannel.v

@@ -0,0 +1,214 @@
+module rchannel (
+    input           clk,
+    input           rst_n,
+    input           axi_s_arvalid,
+    input   [7:0]   axi_s_arlen,
+    input   [25:0]  axi_s_araddr,
+    output          axi_s_arready,
+    output          axi_s_rvalid,
+    output          axi_s_rlast,
+    output  [63:0]  axi_s_rdata,
+    output          rframe_valid,
+    output  [159:0] rframe_data,
+    input           rframe_ready,
+    input           array2axi_rdata_valid,
+    input   [127:0] array2axi_rdata
+);
+    
+    wire        rsof,reof;
+    reg [15:0]  rraddr;
+    reg [5:0]   rcaddr;
+    wire [127:0] wdata;
+    wire [7:0]  arlen;
+
+    wire [15:0] arraddr;
+    wire [5:0]  arcaddr;
+    
+    reg [6:0]  rframe_cnt;
+    reg [7:0]  rdata_cnt;
+
+        
+    reg [1:0] cur_state,next_state;
+    localparam [1:0] RCH_IDLE      = 2'b00;
+    localparam [1:0] RCH_GET_RADDR = 2'b01;
+    localparam [1:0] RCH_SD_RADDR  = 2'b10;
+
+
+
+
+    wire        sync_fifo_ar_wr_en;
+    wire        sync_fifo_ar_rd_en;
+    wire        sync_fifo_ar_full;
+    wire        sync_fifo_ar_empty;
+    wire [29:0] sync_fifo_ar_wr_data;
+    wire [29:0] sync_fifo_ar_rd_data;
+
+
+    sync_fifo #(.DATA_WIDTH(30),
+                .FIFO_DEPTH(4)
+    ) sync_fifo_ar (
+                .clk        (clk),
+                .rst_n      (rst_n),
+                .wr_en      (sync_fifo_ar_wr_en),
+                .wr_data    (sync_fifo_ar_wr_data),
+                .full       (sync_fifo_ar_full),
+                .rd_en      (sync_fifo_ar_rd_en),
+                .rd_data    (sync_fifo_ar_rd_data),
+                .empty      (sync_fifo_ar_empty)
+    );
+
+    wire        sync_fifo_arlen_wr_en;
+    wire        sync_fifo_arlen_rd_en;
+    wire        sync_fifo_arlen_full;
+    wire        sync_fifo_arlen_empty;
+    wire [7:0] sync_fifo_arlen_wr_data;
+    wire [7:0] sync_fifo_arlen_rd_data;
+
+
+    sync_fifo #(.DATA_WIDTH(8),
+                .FIFO_DEPTH(4)
+    ) sync_fifo_arlen (
+                .clk        (clk),
+                .rst_n      (rst_n),
+                .wr_en      (sync_fifo_arlen_wr_en),
+                .wr_data    (sync_fifo_arlen_wr_data),
+                .full       (sync_fifo_arlen_full),
+                .rd_en      (sync_fifo_arlen_rd_en),
+                .rd_data    (sync_fifo_arlen_rd_data),
+                .empty      (sync_fifo_arlen_empty)
+    );
+
+    wire        sync_fifo_r_wr_en;
+    wire        sync_fifo_r_rd_en;
+    wire        sync_fifo_r_full;
+    wire        sync_fifo_r_empty;
+    wire [127:0]sync_fifo_r_wr_data;
+    wire [63:0] sync_fifo_r_rd_data;
+
+
+    sync_fifo_128_to_64 #(.DATA_IN_WIDTH(128),
+                          .FIFO_DEPTH(8),
+                          .DATA_OUT_WIDTH(64)
+    ) sync_fifo_r (
+                .clk        (clk),
+                .rst_n      (rst_n),
+                .wr_en      (sync_fifo_r_wr_en),
+                .wr_data    (sync_fifo_r_wr_data),
+                .full       (sync_fifo_r_full),
+                .rd_en      (sync_fifo_r_rd_en),
+                .rd_data    (sync_fifo_r_rd_data),
+                .empty      (sync_fifo_r_empty)
+    );
+    
+
+    assign  axi_s_arready = !sync_fifo_ar_full;
+    assign  rframe_valid  = (cur_state == RCH_SD_RADDR);
+    assign  rframe_data   = {rsof,reof,rraddr,rcaddr,128'b0,arlen};
+    assign  axi_s_rvalid  = !sync_fifo_r_empty;
+    assign  axi_s_rdata   = sync_fifo_r_rd_data;
+    assign  axi_s_rlast   = axi_s_rvalid && (rdata_cnt == sync_fifo_arlen_rd_data);
+
+    assign sync_fifo_ar_wr_en = axi_s_arvalid && axi_s_arready;
+    assign sync_fifo_ar_wr_data = {axi_s_araddr[25:4],axi_s_arlen};
+    assign sync_fifo_ar_rd_en = rframe_ready && rframe_valid && 
+                                rframe_cnt == arlen>>1'b1 && !sync_fifo_ar_empty;
+    
+    assign {arraddr , arcaddr, arlen} = sync_fifo_ar_rd_data;
+    assign sync_fifo_arlen_wr_en = rframe_valid && rframe_ready && 
+                                rframe_cnt == arlen >> 1'b1;
+    assign sync_fifo_arlen_wr_data = arlen;
+    assign sync_fifo_arlen_rd_en   = axi_s_rlast && axi_s_rvalid;
+    assign rsof = rframe_valid && (rframe_cnt == 7'b0 || rcaddr == 6'd0);
+    assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1 || rcaddr == 6'h3f);
+
+
+    assign sync_fifo_r_wr_en = array2axi_rdata_valid && !sync_fifo_r_full;
+    assign sync_fifo_r_wr_data = array2axi_rdata;
+    assign sync_fifo_r_rd_en = !sync_fifo_r_empty;
+
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            cur_state <= RCH_IDLE;
+        end else begin
+            cur_state <= next_state;
+        end
+    end
+
+    always@(*) begin
+        case(cur_state)
+            RCH_IDLE: begin
+                if(sync_fifo_ar_wr_en) begin
+                    next_state <= RCH_GET_RADDR;
+                end else begin
+                    next_state <=  RCH_IDLE;
+                end
+            end
+            RCH_GET_RADDR: begin
+                    next_state <= RCH_SD_RADDR;
+            end
+            RCH_SD_RADDR:  begin
+                    if(rframe_ready && rframe_valid && rframe_cnt == arlen >>1) begin
+                        next_state <= RCH_IDLE;
+                    end else begin
+                        next_state <= RCH_SD_RADDR;
+                    end
+            end
+        endcase
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rraddr <= 'd0;
+        end else if(cur_state == RCH_GET_RADDR) begin
+            rraddr <= arraddr;
+            if(rframe_valid && rframe_ready) begin
+                if(rcaddr == 6'b111111) begin
+                    rraddr <= rraddr + 1'b1;
+                end else begin
+                    rraddr <= rraddr;
+                end
+            end
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rcaddr <= 'd0;
+        end else if (cur_state == RCH_GET_RADDR) begin
+            rcaddr <= arcaddr;
+            if(rframe_valid && rframe_ready) begin
+                if(rcaddr == 6'b111111) begin
+                    rcaddr <= 'd0;
+                end else begin
+                    rcaddr <= rcaddr + 1;
+                end
+            end
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rframe_cnt <= 'd0;
+        end else if (rframe_valid && rframe_ready) begin
+            if(rframe_cnt == arlen>>1'b1) begin
+                rframe_cnt <= 'd0;
+            end else begin
+                rframe_cnt <= rframe_cnt + 1'b1;
+            end
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rdata_cnt <= 'd0;
+        end else if(axi_s_rvalid) begin
+            if(rdata_cnt == sync_fifo_arlen_rd_data) begin
+                rdata_cnt <= 'd0;
+            end else begin
+                rdata_cnt <= rdata_cnt + 1'b1;
+            end
+        end
+    end
+
+endmodule

rtl/sync_fifo.v

@@ -0,0 +1,76 @@
+module sync_fifo #(
+    parameter DATA_WIDTH = 8,
+    parameter FIFO_DEPTH  = 16
+)(
+    input clk,
+    input rst_n,
+    input wr_en,
+    input [DATA_WIDTH-1:0] wr_data,
+    output full,
+    input rd_en,
+    output [DATA_WIDTH-1:0] rd_data,
+    output empty
+);
+    localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
+    reg [DATA_WIDTH-1:0] mem [0 : FIFO_DEPTH -1];
+    reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr ,rd_ptrr;
+    wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
+    
+    assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
+    assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wr_ptr <= 'd0;    
+        end else if(wr_en && !full) begin
+            wr_ptr <= wr_ptr + 1'b1;
+        end else begin
+            wr_ptr <= wr_ptr;
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rd_ptr <= 'd0;
+            rd_ptrr <= 'd0;
+        end else if(rd_en && !empty) begin
+ 
+            rd_ptr <= rd_ptr + 1'b1;
+            rd_ptrr <= rd_ptr;
+        end else begin
+            rd_ptr <= rd_ptr;
+            rd_ptrr <= rd_ptr;
+        end
+    end
+
+    integer i;
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            for(i=0;i<FIFO_DEPTH;i=i+1) begin
+                mem[i] <= 'd0;
+            end
+        end else if(wr_en && !full) begin
+                mem[wr_addr] <= wr_data;
+        end else begin
+                mem[wr_addr] <= mem[wr_addr];
+        end
+    end
+
+    /*always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+                 r_rd_data <= 'd0;
+        end else if(rd_en && !empty) begin
+                 r_rd_data <= mem[rd_addr];
+        end else begin
+                 r_rd_data <= r_rd_data;
+        end
+    end*/
+
+    assign rd_data = mem[rd_addr];
+
+
+    assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
+                (wr_ptr[ADDR_WIDTH -1:0] == rd_ptr[ADDR_WIDTH -1:0])) ? 1:0;
+    assign empty = (wr_ptr == rd_ptr) ? 1:0;
+
+endmodule

rtl/sync_fifo_128_to_64.v

@@ -0,0 +1,62 @@
+module sync_fifo_128_to_64 #(
+    parameter DATA_IN_WIDTH = 128,
+    parameter DATA_OUT_WIDTH = 64,
+    parameter FIFO_DEPTH  = 16,
+    parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
+)(
+    input clk,
+    input rst_n,
+    input wr_en,
+    input [DATA_IN_WIDTH-1:0] wr_data,
+    output full,
+    input rd_en,
+    output [DATA_OUT_WIDTH-1:0] rd_data,
+    output empty
+);
+
+    reg [DATA_OUT_WIDTH-1:0] mem [0 :FIFO_DEPTH -1];
+    reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
+    wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
+    
+    assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
+    assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wr_ptr <= 'd0;    
+        end else if(wr_en && !full) begin
+                wr_ptr <= wr_ptr + 2'd2;
+        end else begin
+            wr_ptr <= wr_ptr;
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rd_ptr <= 'd0;
+        end else if(rd_en && !empty) begin
+                rd_ptr <= rd_ptr + 1'd1;
+        end else begin
+            rd_ptr <= rd_ptr;
+        end
+    end
+
+    integer i;
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            for(i=0;i<FIFO_DEPTH;i=i+1) begin
+                mem[i] <= 'd0;
+            end
+        end else if(wr_en && !full) begin
+                {mem[wr_addr+1'b1],mem[wr_addr]} <= wr_data;
+        end else begin
+                mem[wr_addr] <= mem[wr_addr];
+        end
+    end
+
+    assign rd_data = mem[rd_addr];
+
+    assign full = (wr_ptr - rd_ptr  == FIFO_DEPTH) ? 1:0;
+    assign empty = (wr_ptr == rd_ptr) ? 1:0;
+
+endmodule

rtl/sync_fifo_64_to_128.v

@@ -0,0 +1,62 @@
+module sync_fifo_64_to_128 #(
+    parameter DATA_IN_WIDTH = 64,
+    parameter DATA_OUT_WIDTH = 128,
+    parameter FIFO_DEPTH  = 16,
+    parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
+)(
+    input clk,
+    input rst_n,
+    input wr_en,
+    input [DATA_IN_WIDTH-1:0] wr_data,
+    output full,
+    input rd_en,
+    output [DATA_OUT_WIDTH-1:0] rd_data,
+    output empty
+);
+
+    reg [DATA_IN_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
+    reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
+    wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
+    
+    assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
+    assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wr_ptr <= 'd0;    
+        end else if(wr_en && !full) begin
+                wr_ptr <= wr_ptr + 1'b1;
+        end else begin
+            wr_ptr <= wr_ptr;
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rd_ptr <= 'd0;
+        end else if(rd_en && !empty) begin
+                rd_ptr <= rd_ptr + 2'd2;
+        end else begin
+            rd_ptr <= rd_ptr;
+        end
+    end
+
+    integer i;
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            for(i=0;i<FIFO_DEPTH;i=i+1) begin
+                mem[i] <= 'd0;
+            end
+        end else if(wr_en && !full) begin
+                mem[wr_addr] <= wr_data;
+        end else begin
+                mem[wr_addr] <= mem[wr_addr];
+        end
+    end
+
+    assign rd_data = {mem[rd_addr+1],mem[rd_addr]};
+
+    assign full = (wr_ptr - rd_ptr  == FIFO_DEPTH) ? 1:0;
+    assign empty = (wr_ptr - rd_ptr <=1) ? 1:0;
+
+endmodule

rtl/wchannel.v

@@ -0,0 +1,168 @@
+module wchannel(
+    input clk,
+    input rst_n,
+
+    input           axi_s_awvalid,
+    input [7:0]     axi_s_awlen,
+    input [25:0]    axi_s_awaddr,
+    output          axi_s_awready,
+
+    input           axi_s_wvalid,
+    input           axi_s_wlast,
+    input [63:0]    axi_s_wdata,
+    output          axi_s_wready,
+
+    output          wframe_valid,
+    output [159:0]  wframe_data,
+    input           wframe_ready
+);
+    wire            wsof,weof;
+    reg [15:0]      wraddr;
+    reg [5:0]       wcaddr;
+    wire [127:0]    wdata;
+
+    wire [7:0]      awlen;
+    wire [15:0]     awraddr;
+    wire [5:0]      awcaddr;
+
+    reg [6:0]       wframe_cnt;
+
+    reg [1:0]       cur_state,next_state;
+    localparam [1:0] WCH_IDLE     = 2'b01;
+    localparam [1:0] WCH_SD_WADDR = 2'b10;
+    localparam [1:0] WCH_SD_WDATA = 2'b11;
+    
+    wire            sync_fifo_aw_wr_en;
+    wire [29:0]     sync_fifo_aw_wr_data;
+    wire            sync_fifo_aw_rd_en;
+    wire [29:0]     sync_fifo_aw_rd_data;
+    wire            sync_fifo_aw_full;
+    wire            sync_fifo_aw_empty;
+
+    wire            sync_fifo_w_wr_en;
+    wire [63:0]     sync_fifo_w_wr_data;
+    wire            sync_fifo_w_rd_en;
+    wire [127:0]    sync_fifo_w_rd_data;
+    wire            sync_fifo_w_full;
+    wire            sync_fifo_w_empty;
+
+    assign  sync_fifo_aw_wr_en = axi_s_awvalid && axi_s_awready;
+    assign  sync_fifo_aw_wr_data = {axi_s_awaddr[25:4],axi_s_awlen};
+    assign  sync_fifo_aw_rd_en = wframe_ready && weof && !sync_fifo_aw_empty;
+    assign  {awraddr,awcaddr,awlen} = sync_fifo_aw_rd_data;
+    assign  axi_s_awready = !sync_fifo_aw_full;
+
+        
+
+    assign  sync_fifo_w_wr_en = axi_s_wvalid && axi_s_wready;
+    assign  sync_fifo_w_wr_data = axi_s_wdata;
+    assign  sync_fifo_w_rd_en = wframe_valid && wframe_ready;
+    assign  wdata = sync_fifo_w_rd_data;
+    assign  axi_s_wready = !sync_fifo_w_full;
+
+    assign wsof = wframe_valid && (wframe_cnt == 7'd0);
+    assign weof = wframe_valid && ((wframe_cnt == awlen >> 1'b1));
+
+    assign wframe_data = {wsof,weof,wraddr,wcaddr,wdata,awlen};
+    assign wframe_valid = !sync_fifo_w_empty && (cur_state == WCH_SD_WDATA);
+
+    sync_fifo #(.DATA_WIDTH(30),
+                .FIFO_DEPTH(4)
+    ) sync_fifo_aw (.clk        (clk),
+                    .rst_n      (rst_n),
+                    .wr_en      (sync_fifo_aw_wr_en),
+                    .wr_data    (sync_fifo_aw_wr_data),
+                    .rd_en      (sync_fifo_aw_rd_en),
+                    .rd_data    (sync_fifo_aw_rd_data),
+                    .full       (sync_fifo_aw_full),
+                    .empty      (sync_fifo_aw_empty)
+    );
+
+    sync_fifo_64_to_128 #(
+                .DATA_IN_WIDTH(64),
+                .DATA_OUT_WIDTH(128),
+                .FIFO_DEPTH(8)
+    ) sync_fifo_w (.clk         (clk),
+                   .rst_n       (rst_n),
+                   .wr_en       (sync_fifo_w_wr_en),
+                   .wr_data     (sync_fifo_w_wr_data),
+                   .rd_en       (sync_fifo_w_rd_en),
+                   .rd_data     (sync_fifo_w_rd_data),
+                   .full        (sync_fifo_w_full),
+                   .empty       (sync_fifo_w_empty)
+    );
+    
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wframe_cnt <= 'd0;
+        end else if (sync_fifo_w_rd_en) begin
+            if (wframe_cnt == (awlen >> 1'b1)) begin
+                wframe_cnt <= 'd0;
+            end else begin
+                wframe_cnt <= wframe_cnt + 1'b1;
+            end
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            cur_state <= WCH_IDLE;
+        end else begin
+            cur_state <= next_state;
+        end
+    end
+
+    always@(*) begin
+        case(cur_state)
+            WCH_IDLE: begin
+                if(sync_fifo_aw_wr_en) begin
+                    next_state <= WCH_SD_WADDR;
+                end else begin
+                    next_state <= WCH_IDLE;
+                end
+            end
+
+            WCH_SD_WADDR: begin
+                    next_state <= WCH_SD_WDATA;
+            end
+
+            WCH_SD_WDATA: begin
+                    if(sync_fifo_w_rd_en && (wframe_cnt == (awlen >> 1))) begin
+                        next_state <= WCH_IDLE;
+                    end else begin
+                        next_state <= WCH_SD_WDATA;
+                    end
+            end
+
+            default : begin
+                    next_state <= WCH_IDLE;
+            end 
+        endcase
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wcaddr <= 'd0;
+        end else if (cur_state == WCH_SD_WADDR) begin
+            wcaddr <= awcaddr;
+        end else if (sync_fifo_w_rd_en) begin
+            if (wcaddr  == 6'h3f) begin
+                wcaddr <= 'd0;
+            end else begin
+                wcaddr <= wcaddr + 1'b1;
+            end
+        end
+    end
+
+    always@(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            wraddr <= 'd0;
+        end else if (cur_state == WCH_SD_WADDR) begin
+        if (sync_fifo_w_rd_en && (wcaddr == 6'h3f)) begin
+            wraddr <= wraddr + 1'b1;
+        end else begin 
+            wraddr <= wraddr;
+        end
+    end
+    end
+endmodule

sim/Makefile

@@ -0,0 +1,20 @@
+#-------------------------------------------------------------------------------------------------------
+comp  : clean vcs
+#-------------------------------------------------------------------------------------------------------
+find  :
+	find ../{rtl,tb} -name "*.v" > filelist.f
+#---------------------------------------------------------------------------------------
+vcs   :
+	vcs  \
+		-f filelist.f  \
+		-timescale=1ns/1ps \
+		-debug -o simv\
+		-full64  -R  +vc  +v2k  -sverilog -debug_access+all\
+		|  tee  vcs.log 
+#-------------------------------------------------------------------------------------------------------
+verdi  :
+	verdi -f filelist.f -ssf tb.fsdb &
+#-------------------------------------------------------------------------------------------------------
+clean  :
+	 rm  -rf  *~  core  csrc  simv*  vc_hdrs.h  ucli.key  urg* *.log  novas.* *.fsdb* verdiLog  64* DVEfiles *.vpd
+#-------------------------------------------------------------------------------------------------------

sim/csrc/Makefile

@@ -0,0 +1,116 @@
+# Makefile generated by VCS to build your model
+# This file may be modified; VCS will not overwrite it unless -Mupdate is used
+
+# define default verilog source directory 
+VSRC=..
+
+# Override TARGET_ARCH
+TARGET_ARCH=
+
+# Choose name of executable 
+PRODUCTBASE=$(VSRC)/simv
+
+PRODUCT=$(PRODUCTBASE)
+
+# Product timestamp file. If product is newer than this one,
+# we will also re-link the product.
+PRODUCT_TIMESTAMP=product_timestamp
+
+# Path to runtime library
+DEPLIBS=
+VCSUCLI=-lvcsucli
+RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o $(DEPLIBS) 
+
+VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
+
+# Select your favorite compiler
+
+# Linux:
+VCS_CC=gcc
+
+# Internal CC for gen_c flow:
+CC_CG=gcc
+# User overrode default CC: 
+VCS_CC=gcc
+# Loader
+LD=g++
+
+# Strip Flags for target product
+STRIPFLAGS= 
+
+PRE_LDFLAGS= # Loader Flags
+LDFLAGS= -rdynamic  -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib 
+# Picarchive Flags
+PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir 
+
+# C run time startup
+CRT0=
+# C run time startup
+CRTN=
+# Machine specific libraries
+SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl
+
+# Default defines
+SHELL=/bin/sh
+
+VCSTMPSPECARG=
+VCSTMPSPECENV=
+# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
+#and you are using gcc, uncomment the next line
+#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
+
+TMPSPECARG=$(VCSTMPSPECARG)
+TMPSPECENV=$(VCSTMPSPECENV)
+CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
+
+# C flags for compilation
+CFLAGS=-w  -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include   
+
+CFLAGS_O0=-w  -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O0  -fno-strict-aliasing   
+
+CFLAGS_CG=-w  -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O  -fno-strict-aliasing   
+
+LD_PARTIAL_LOADER=ld
+# Partial linking
+LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
+ASFLAGS=
+LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs 
+# Note: if make gives you errors about include, either get gmake, or
+# replace the following line with the contents of the file filelist,
+# EACH TIME IT CHANGES
+# included file defines OBJS, and is automatically generated by vcs
+include filelist
+
+OBJS=$(VLOG_OBJS)  $(SYSC_OBJS)   $(VHDL_OBJS) 
+
+product : $(PRODUCT_TIMESTAMP)
+	@echo $(PRODUCT) up to date
+
+objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) 
+
+clean   :
+	rm -f $(VCS_OBJS) $(CU_OBJS)
+
+clobber : clean
+	rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) 
+
+picclean : 
+	rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
+	@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
+
+product_clean_order : 
+	@$(MAKE) -f Makefile --no-print-directory picclean
+	@$(MAKE) -f Makefile --no-print-directory product_order
+
+product_order : $(PRODUCT)
+
+$(PRODUCT_TIMESTAMP) : product_clean_order
+	-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
+	$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS)  $(LIBS)   $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive     $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)   $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
+	@rm -f csrc[0-9]*.o
+	@touch $(PRODUCT_TIMESTAMP)
+	@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
+
+$(PRODUCT) :  $(LD_VERSION_CHECK)  $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsnew.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsimprofile.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libuclinative.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsucli.so  $(VCS_SAVE_RESTORE_OBJ) 
+	@touch $(PRODUCT)
+

sim/csrc/Makefile.hsopt

@@ -0,0 +1,47 @@
+# Makefile generated by VCS to build rmapats.so for your model
+VSRC=..
+
+# Override TARGET_ARCH
+TARGET_ARCH=
+
+# Select your favorite compiler
+
+# Linux:
+VCS_CC=gcc
+
+# Internal CC for gen_c flow:
+CC_CG=gcc
+
+# User overrode default CC: 
+VCS_CC=gcc
+# Loader
+LD=g++
+# Loader Flags
+LDFLAGS=
+
+# Default defines
+SHELL=/bin/sh
+
+VCSTMPSPECARG=
+VCSTMPSPECENV=
+# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
+#and you are using gcc, uncomment the next line
+#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
+
+TMPSPECARG=$(VCSTMPSPECARG)
+TMPSPECENV=$(VCSTMPSPECENV)
+CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
+
+# C flags for compilation
+CFLAGS=-w  -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include    
+
+CFLAGS_CG=-w  -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O  -fno-strict-aliasing   
+
+ASFLAGS=
+LIBS=
+
+include filelist.hsopt
+
+
+rmapats.so: $(HSOPT_OBJS)
+	@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)

sim/csrc/_10313_archive_1.so

@@ -0,0 +1 @@
+.//../simv.daidir//_10313_archive_1.so

sim/csrc/_12247_archive_1.so

@@ -0,0 +1 @@
+.//../simv.daidir//_12247_archive_1.so

sim/csrc/_csrc0.so

@@ -0,0 +1 @@
+.//../simv.daidir//_csrc0.so

sim/csrc/_prev_archive_1.so

@@ -0,0 +1 @@
+.//../simv.daidir//_prev_archive_1.so

sim/csrc/_prev_cginfo.json

@@ -0,0 +1,350 @@
+{
+    "CompileStrategy": "fullobj",
+    "LVLData": [
+        "SIM"
+    ],
+    "cycles_program_begin": 2758955874976,
+    "PrevCompiledModules": {},
+    "cpu_cycles_pass2_start": 2759502395101,
+    "perf": [
+        {
+            "stat": [
+                "main",
+                "entry",
+                0.05781102180480957,
+                0.046817999999999999,
+                0.14147199999999999,
+                211404,
+                211404,
+                0.0,
+                0.0,
+                1754401752.8100059,
+                2758956108996
+            ],
+            "sub": [
+                {
+                    "stat": [
+                        "doParsingAndDesignResolution",
+                        "entry",
+                        0.089916229248046875,
+                        0.052483000000000002,
+                        0.15539,
+                        267312,
+                        268112,
+                        0.0,
+                        0.0,
+                        1754401752.8421111,
+                        2759013911703
+                    ],
+                    "sub": []
+                },
+                {
+                    "stat": [
+                        "doParsingAndDesignResolution",
+                        "exit",
+                        0.10485506057739258,
+                        0.06361,
+                        0.156974,
+                        268348,
+                        268996,
+                        0.0,
+                        0.0,
+                        1754401752.8570499,
+                        2759040791443
+                    ],
+                    "sub": []
+                },
+                {
+                    "stat": [
+                        "doPostDesignResolutionToVir2Vcs",
+                        "entry",
+                        0.10614323616027832,
+                        0.063685000000000005,
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+                        268996,
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+                        0.0,
+                        1754401752.8583381,
+                        2759043081309
+                    ],
+                    "sub": [
+                        {
+                            "stat": [
+                                "doUptoVir2VcsNoSepCleanup",
+                                "entry",
+                                0.11371612548828125,
+                                0.071035000000000001,
+                                0.15840899999999999,
+                                273532,
+                                273536,
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+                                0.0,
+                                1754401752.865911,
+                                2759056694656
+                            ],
+                            "sub": []
+                        },
+                        {
+                            "stat": [
+                                "doUptoVir2VcsNoSepCleanup",
+                                "exit",
+                                0.18745708465576172,
+                                0.11164200000000001,
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+                                0.0080300000000000007,
+                                0.016379000000000001,
+                                1754401752.939652,
+                                2759189424742
+                            ],
+                            "sub": []
+                        },
+                        {
+                            "stat": [
+                                "doRadify_vir2vcsAll",
+                                "entry",
+                                0.18754220008850098,
+                                0.111677,
+                                0.166993,
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+                                0.0080300000000000007,
+                                0.016379000000000001,
+                                1754401752.9397371,
+                                2759189537465
+                            ],
+                            "sub": []
+                        },
+                        {
+                            "stat": [
+                                "doRadify_vir2vcsAll",
+                                "exit",
+                                0.19117116928100586,
+                                0.11530600000000001,
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+                                0.0080300000000000007,
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+                                1754401752.9433661,
+                                2759196093769
+                            ],
+                            "sub": []
+                        }
+                    ]
+                },
+                {
+                    "stat": [
+                        "doPostDesignResolutionToVir2Vcs",
+                        "exit",
+                        0.19121718406677246,
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+                        0.0080300000000000007,
+                        0.016379000000000001,
+                        1754401752.9434121,
+                        2759196143242
+                    ],
+                    "sub": []
+                },
+                {
+                    "stat": [
+                        "doGAToPass2",
+                        "entry",
+                        0.19124317169189453,
+                        0.115379,
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+                        1754401752.9434381,
+                        2759196186493
+                    ],
+                    "sub": [
+                        {
+                            "stat": [
+                                "DoPass2",
+                                "entry",
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+                                2759502382558
+                            ],
+                            "sub": []
+                        },
+                        {
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+                                "DoPass2",
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+                                2759665071204
+                            ],
+                            "sub": []
+                        }
+                    ]
+                },
+                {
+                    "stat": [
+                        "doGAToPass2",
+                        "exit",
+                        0.45728802680969238,
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+                        1754401753.2094829,
+                        2759675101864
+                    ],
+                    "sub": []
+                }
+            ]
+        },
+        {
+            "stat": [
+                "main",
+                "exit",
+                0.45755314826965332,
+                0.18868099999999999,
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+                283488,
+                0.022948,
+                0.096718999999999999,
+                1754401753.209748,
+                2759675555357
+            ],
+            "sub": []
+        }
+    ],
+    "MlibObjs": {},
+    "NameTable": {
+        "...MASTER...": [
+            "SIM",
+            "amcQw",
+            "module",
+            3
+        ],
+        "std": [
+            "std",
+            "reYIK",
+            "module",
+            1
+        ],
+        "tb_rchannel": [
+            "tb_rchannel",
+            "TJvMf",
+            "module",
+            2
+        ]
+    },
+    "stat": {
+        "nQuads": 2574,
+        "ru_self_cgstart": {
+            "ru_utime_sec": 0.11758299999999999,
+            "ru_nivcsw": 3,
+            "ru_stime_sec": 0.16753000000000001,
+            "ru_maxrss_kb": 79476,
+            "ru_minflt": 26915,
+            "ru_majflt": 52,
+            "ru_nvcsw": 117
+        },
+        "cpu_cycles_end": 2759675599424,
+        "ru_childs_cgstart": {
+            "ru_utime_sec": 0.022948,
+            "ru_nivcsw": 25,
+            "ru_stime_sec": 0.096718999999999999,
+            "ru_maxrss_kb": 30348,
+            "ru_minflt": 10704,
+            "ru_majflt": 8,
+            "ru_nvcsw": 92
+        },
+        "realTime": 0.45762920379638672,
+        "Frontend(%)": 66.396885468195578,
+        "cpu_cycles_cgstart": 2759502442197,
+        "ru_childs_end": {
+            "ru_utime_sec": 0.022948,
+            "ru_nivcsw": 25,
+            "ru_stime_sec": 0.096718999999999999,
+            "ru_maxrss_kb": 30348,
+            "ru_minflt": 10704,
+            "ru_majflt": 8,
+            "ru_nvcsw": 92
+        },
+        "mop/quad": 2.7610722610722611,
+        "nMops": 7107,
+        "quadSpeed": 36191.333202103422,
+        "totalObjSize": 263716,
+        "ru_self_end": {
+            "ru_utime_sec": 0.18870500000000001,
+            "ru_nivcsw": 3,
+            "ru_stime_sec": 0.19076699999999999,
+            "ru_maxrss_kb": 88492,
+            "ru_minflt": 30909,
+            "ru_majflt": 52,
+            "ru_nvcsw": 122
+        },
+        "cpu_cycles_total": 719724448,
+        "mopSpeed": 99926.886195551284,
+        "outputSizePerQuad": 102.45376845376845,
+        "CodeGen(%)": 33.603114531804422,
+        "peak_mem_kb": 283488
+    },
+    "CurCompileUdps": {},
+    "SIMBData": {
+        "out": "amcQwB.o",
+        "bytes": 117946,
+        "text": 0,
+        "archive": "archive.0/_10313_archive_1.a"
+    },
+    "incremental": "on",
+    "CurCompileModules": [
+        "...MASTER...",
+        "...MASTER...",
+        "std",
+        "std",
+        "tb_rchannel",
+        "tb_rchannel"
+    ],
+    "PEModules": [],
+    "CompileProcesses": [
+        "cgproc.10313.json"
+    ],
+    "Misc": {
+        "vcs_version": "O-2018.09-1_Full64",
+        "csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
+        "vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
+        "csrc": "csrc",
+        "master_pid": 10313,
+        "default_output_dir": "csrc",
+        "VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
+        "hostname": "IC_EDA",
+        "cwd": "/home/ICer/ic_prjs/mc/sim",
+        "daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
+        "daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
+        "archive_dir": "archive.0"
+    },
+    "rlimit": {
+        "data": -1,
+        "stack": -1
+    },
+    "CompileStatus": "Successful"
+}

sim/csrc/_vcs_pli_stub_.c

@@ -0,0 +1,964 @@
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+#include <stdio.h>
+#include <dlfcn.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void* VCS_dlsymLookup(const char *);
+extern void vcsMsgReportNoSource1(const char *, const char*);
+
+/* PLI routine: $fsdbDumpvars:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
+#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
+extern void novas_call_fsdbDumpvars(int data, int reason);
+#pragma weak novas_call_fsdbDumpvars
+void novas_call_fsdbDumpvars(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
+
+/* PLI routine: $fsdbDumpvars:misc */
+#ifndef __VCS_PLI_STUB_novas_misc
+#define __VCS_PLI_STUB_novas_misc
+extern void novas_misc(int data, int reason, int iparam );
+#pragma weak novas_misc
+void novas_misc(int data, int reason, int iparam )
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason, iparam );
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
+#endif /* __VCS_PLI_STUB_novas_misc */
+
+/* PLI routine: $fsdbDumpvarsByFile:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
+#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
+extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
+#pragma weak novas_call_fsdbDumpvarsByFile
+void novas_call_fsdbDumpvarsByFile(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
+
+/* PLI routine: $fsdbAddRuntimeSignal:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
+#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
+extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
+#pragma weak novas_call_fsdbAddRuntimeSignal
+void novas_call_fsdbAddRuntimeSignal(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
+
+/* PLI routine: $sps_create_transaction_stream:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
+#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
+extern void novas_call_sps_create_transaction_stream(int data, int reason);
+#pragma weak novas_call_sps_create_transaction_stream
+void novas_call_sps_create_transaction_stream(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
+#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
+
+/* PLI routine: $sps_begin_transaction:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
+#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
+extern void novas_call_sps_begin_transaction(int data, int reason);
+#pragma weak novas_call_sps_begin_transaction
+void novas_call_sps_begin_transaction(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
+#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
+
+/* PLI routine: $sps_end_transaction:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
+#define __VCS_PLI_STUB_novas_call_sps_end_transaction
+extern void novas_call_sps_end_transaction(int data, int reason);
+#pragma weak novas_call_sps_end_transaction
+void novas_call_sps_end_transaction(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
+#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
+
+/* PLI routine: $sps_free_transaction:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
+#define __VCS_PLI_STUB_novas_call_sps_free_transaction
+extern void novas_call_sps_free_transaction(int data, int reason);
+#pragma weak novas_call_sps_free_transaction
+void novas_call_sps_free_transaction(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
+#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
+
+/* PLI routine: $sps_add_attribute:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
+#define __VCS_PLI_STUB_novas_call_sps_add_attribute
+extern void novas_call_sps_add_attribute(int data, int reason);
+#pragma weak novas_call_sps_add_attribute
+void novas_call_sps_add_attribute(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
+#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
+
+/* PLI routine: $sps_update_label:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
+#define __VCS_PLI_STUB_novas_call_sps_update_label
+extern void novas_call_sps_update_label(int data, int reason);
+#pragma weak novas_call_sps_update_label
+void novas_call_sps_update_label(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
+#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
+
+/* PLI routine: $sps_add_relation:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
+#define __VCS_PLI_STUB_novas_call_sps_add_relation
+extern void novas_call_sps_add_relation(int data, int reason);
+#pragma weak novas_call_sps_add_relation
+void novas_call_sps_add_relation(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
+#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
+
+/* PLI routine: $fsdbWhatif:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
+#define __VCS_PLI_STUB_novas_call_fsdbWhatif
+extern void novas_call_fsdbWhatif(int data, int reason);
+#pragma weak novas_call_fsdbWhatif
+void novas_call_fsdbWhatif(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
+
+/* PLI routine: $paa_init:call */
+#ifndef __VCS_PLI_STUB_novas_call_paa_init
+#define __VCS_PLI_STUB_novas_call_paa_init
+extern void novas_call_paa_init(int data, int reason);
+#pragma weak novas_call_paa_init
+void novas_call_paa_init(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
+#endif /* __VCS_PLI_STUB_novas_call_paa_init */
+
+/* PLI routine: $paa_sync:call */
+#ifndef __VCS_PLI_STUB_novas_call_paa_sync
+#define __VCS_PLI_STUB_novas_call_paa_sync
+extern void novas_call_paa_sync(int data, int reason);
+#pragma weak novas_call_paa_sync
+void novas_call_paa_sync(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
+#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
+
+/* PLI routine: $fsdbDumpClassMethod:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
+#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
+extern void novas_call_fsdbDumpClassMethod(int data, int reason);
+#pragma weak novas_call_fsdbDumpClassMethod
+void novas_call_fsdbDumpClassMethod(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
+
+/* PLI routine: $fsdbSuppressClassMethod:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
+#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
+extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
+#pragma weak novas_call_fsdbSuppressClassMethod
+void novas_call_fsdbSuppressClassMethod(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
+
+/* PLI routine: $fsdbSuppressClassProp:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
+#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
+extern void novas_call_fsdbSuppressClassProp(int data, int reason);
+#pragma weak novas_call_fsdbSuppressClassProp
+void novas_call_fsdbSuppressClassProp(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
+
+/* PLI routine: $fsdbDumpMDAByFile:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
+#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
+extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
+#pragma weak novas_call_fsdbDumpMDAByFile
+void novas_call_fsdbDumpMDAByFile(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
+
+/* PLI routine: $fsdbTrans_create_stream_begin:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
+extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
+#pragma weak novas_call_fsdbEvent_create_stream_begin
+void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
+
+/* PLI routine: $fsdbTrans_define_attribute:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
+extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
+#pragma weak novas_call_fsdbEvent_add_stream_attribute
+void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
+
+/* PLI routine: $fsdbTrans_create_stream_end:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
+extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
+#pragma weak novas_call_fsdbEvent_create_stream_end
+void novas_call_fsdbEvent_create_stream_end(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
+
+/* PLI routine: $fsdbTrans_begin:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
+extern void novas_call_fsdbEvent_begin(int data, int reason);
+#pragma weak novas_call_fsdbEvent_begin
+void novas_call_fsdbEvent_begin(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
+
+/* PLI routine: $fsdbTrans_set_label:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
+extern void novas_call_fsdbEvent_set_label(int data, int reason);
+#pragma weak novas_call_fsdbEvent_set_label
+void novas_call_fsdbEvent_set_label(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
+
+/* PLI routine: $fsdbTrans_add_attribute:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
+extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
+#pragma weak novas_call_fsdbEvent_add_attribute
+void novas_call_fsdbEvent_add_attribute(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
+
+/* PLI routine: $fsdbTrans_add_tag:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
+extern void novas_call_fsdbEvent_add_tag(int data, int reason);
+#pragma weak novas_call_fsdbEvent_add_tag
+void novas_call_fsdbEvent_add_tag(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
+
+/* PLI routine: $fsdbTrans_end:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
+extern void novas_call_fsdbEvent_end(int data, int reason);
+#pragma weak novas_call_fsdbEvent_end
+void novas_call_fsdbEvent_end(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
+
+/* PLI routine: $fsdbTrans_add_relation:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
+extern void novas_call_fsdbEvent_add_relation(int data, int reason);
+#pragma weak novas_call_fsdbEvent_add_relation
+void novas_call_fsdbEvent_add_relation(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
+
+/* PLI routine: $fsdbTrans_get_error_code:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
+#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
+extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
+#pragma weak novas_call_fsdbEvent_get_error_code
+void novas_call_fsdbEvent_get_error_code(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
+
+/* PLI routine: $fsdbTrans_add_stream_attribute:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
+#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
+extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
+#pragma weak novas_call_fsdbTrans_add_stream_attribute
+void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
+
+/* PLI routine: $fsdbTrans_add_scope_attribute:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
+#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
+extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
+#pragma weak novas_call_fsdbTrans_add_scope_attribute
+void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
+
+/* PLI routine: $sps_interactive:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
+#define __VCS_PLI_STUB_novas_call_sps_interactive
+extern void novas_call_sps_interactive(int data, int reason);
+#pragma weak novas_call_sps_interactive
+void novas_call_sps_interactive(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
+#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
+
+/* PLI routine: $sps_test:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_test
+#define __VCS_PLI_STUB_novas_call_sps_test
+extern void novas_call_sps_test(int data, int reason);
+#pragma weak novas_call_sps_test
+void novas_call_sps_test(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
+#endif /* __VCS_PLI_STUB_novas_call_sps_test */
+
+/* PLI routine: $fsdbDumpClassObject:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
+#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
+extern void novas_call_fsdbDumpClassObject(int data, int reason);
+#pragma weak novas_call_fsdbDumpClassObject
+void novas_call_fsdbDumpClassObject(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
+
+/* PLI routine: $fsdbDumpClassObjectByFile:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
+#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
+extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
+#pragma weak novas_call_fsdbDumpClassObjectByFile
+void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
+
+/* PLI routine: $ridbDump:call */
+#ifndef __VCS_PLI_STUB_novas_call_ridbDump
+#define __VCS_PLI_STUB_novas_call_ridbDump
+extern void novas_call_ridbDump(int data, int reason);
+#pragma weak novas_call_ridbDump
+void novas_call_ridbDump(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
+#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
+
+/* PLI routine: $sps_flush_file:call */
+#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
+#define __VCS_PLI_STUB_novas_call_sps_flush_file
+extern void novas_call_sps_flush_file(int data, int reason);
+#pragma weak novas_call_sps_flush_file
+void novas_call_sps_flush_file(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
+#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
+
+/* PLI routine: $fsdbDumpSingle:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
+#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
+extern void novas_call_fsdbDumpSingle(int data, int reason);
+#pragma weak novas_call_fsdbDumpSingle
+void novas_call_fsdbDumpSingle(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
+
+/* PLI routine: $fsdbDumpIO:call */
+#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
+#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
+extern void novas_call_fsdbDumpIO(int data, int reason);
+#pragma weak novas_call_fsdbDumpIO
+void novas_call_fsdbDumpIO(int data, int reason)
+{
+    static int _vcs_pli_stub_initialized_ = 0;
+    static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
+    if (!_vcs_pli_stub_initialized_) {
+        _vcs_pli_stub_initialized_ = 1;
+        _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
+        if (_vcs_pli_fp_ == NULL) {
+            _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
+        }
+    }
+    if (_vcs_pli_fp_) {
+        _vcs_pli_fp_(data, reason);
+    } else {
+        vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
+    }
+}
+void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
+#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
+
+#ifdef __cplusplus
+}
+#endif

sim/csrc/archive.1/_12247_archive_1.a.info

@@ -0,0 +1 @@
+amcQwB.o

sim/csrc/archive.1/_prev_archive_1.a.info

@@ -0,0 +1,2 @@
+reYIK_d.o
+TJvMf_d.o

sim/csrc/cginfo.json

@@ -0,0 +1,377 @@
+{
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+    "cycles_program_begin": 3307152958815,
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+                1754402057.5751581,
+                3307534766369
+            ],
+            "sub": []
+        }
+    ],
+    "CurCompileUdps": {},
+    "CompileProcesses": [
+        "cgproc.12247.json"
+    ],
+    "CurCompileModules": [
+        "...MASTER...",
+        "std",
+        "tb_rchannel"
+    ],
+    "PrevCompiledModules": {
+        "std": {
+            "reYIK_d": {
+                "bytes": 43078,
+                "mod": "std",
+                "out": "reYIK_d.o",
+                "mode": 4,
+                "checksum": 0,
+                "archive": "archive.1/_prev_archive_1.a"
+            }
+        },
+        "tb_rchannel": {
+            "TJvMf_d": {
+                "bytes": 94788,
+                "mod": "tb_rchannel",
+                "out": "TJvMf_d.o",
+                "mode": 4,
+                "checksum": 0,
+                "archive": "archive.1/_prev_archive_1.a"
+            }
+        },
+        "...MASTER...": {
+            "amcQw_d": {
+                "bytes": 7904,
+                "mod": "...MASTER...",
+                "out": "objs/amcQw_d.o",
+                "mode": 4,
+                "checksum": 0
+            }
+        }
+    },
+    "NameTable": {
+        "std": [
+            "std",
+            "reYIK",
+            "module",
+            1
+        ],
+        "tb_rchannel": [
+            "tb_rchannel",
+            "TJvMf",
+            "module",
+            2
+        ],
+        "...MASTER...": [
+            "SIM",
+            "amcQw",
+            "module",
+            3
+        ]
+    },
+    "SIMBData": {
+        "out": "amcQwB.o",
+        "bytes": 117070,
+        "archive": "archive.1/_12247_archive_1.a",
+        "text": 0
+    },
+    "cpu_cycles_pass2_start": 3307450168560,
+    "LVLData": [
+        "SIM"
+    ],
+    "stat": {
+        "ru_self_cgstart": {
+            "ru_maxrss_kb": 80808,
+            "ru_utime_sec": 0.090082999999999996,
+            "ru_stime_sec": 0.080764000000000002,
+            "ru_minflt": 25946,
+            "ru_majflt": 0,
+            "ru_nvcsw": 27,
+            "ru_nivcsw": 9
+        },
+        "ru_self_end": {
+            "ru_maxrss_kb": 90168,
+            "ru_utime_sec": 0.126638,
+            "ru_stime_sec": 0.086485000000000006,
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+        },
+        "ru_childs_cgstart": {
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+            "ru_stime_sec": 0.028851000000000002,
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+            "ru_nvcsw": 26,
+            "ru_nivcsw": 22
+        },
+        "cpu_cycles_total": 381884822,
+        "cpu_cycles_cgstart": 3307450206879,
+        "nMops": 7107,
+        "Frontend(%)": 77.115222086580886,
+        "ru_childs_end": {
+            "ru_maxrss_kb": 29668,
+            "ru_utime_sec": 0.033097000000000001,
+            "ru_stime_sec": 0.032874,
+            "ru_minflt": 10742,
+            "ru_majflt": 0,
+            "ru_nvcsw": 27,
+            "ru_nivcsw": 24
+        },
+        "cpu_cycles_end": 3307534843637,
+        "nQuads": 2574,
+        "totalObjSize": 117070,
+        "mopSpeed": 194419.36807550257,
+        "CodeGen(%)": 22.884777913419111,
+        "quadSpeed": 70414.443988510422,
+        "mop/quad": 2.7610722610722611,
+        "outputSizePerQuad": 45.481740481740481,
+        "peak_mem_kb": 284132,
+        "realTime": 0.23830199241638184
+    },
+    "incremental": "on",
+    "PEModules": [],
+    "Misc": {
+        "vcs_version": "O-2018.09-1_Full64",
+        "csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
+        "vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
+        "cwd": "/home/ICer/ic_prjs/mc/sim",
+        "VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
+        "hostname": "IC_EDA",
+        "master_pid": 12247,
+        "csrc": "csrc",
+        "daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
+        "daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
+        "default_output_dir": "csrc",
+        "archive_dir": "archive.1"
+    },
+    "rlimit": {
+        "data": -1,
+        "stack": -1
+    },
+    "CompileStatus": "Successful"
+}

sim/csrc/cgproc.12247.json

@@ -0,0 +1,170 @@
+{
+    "Modules": {
+        "...MASTER...": {
+            "nRouts": 5,
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+            "child_modules": {},
+            "Compiled Times": 2,
+            "nMops": 528,
+            "Compiled": "Yes",
+            "end_perf": [
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+            "Compiled": "Yes",
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+    },
+    "CompUnits": {},
+    "reusePaths": {
+        "reYIK_d": {
+            "icPath": "csrc"
+        },
+        "amcQw_d": {
+            "icPath": "csrc"
+        },
+        "TJvMf_d": {
+            "icPath": "csrc"
+        }
+    },
+    "ObjArchives": [
+        {
+            "archive": "archive.1/_12247_archive_1.a",
+            "objects": [
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+            "ru_majflt": 0,
+            "ru_nvcsw": 29,
+            "ru_nivcsw": 9
+        },
+        "cpu_cycles_end": 3307534115943,
+        "ru_childs_end": {
+            "ru_maxrss_kb": 29668,
+            "ru_utime_sec": 0.033097000000000001,
+            "ru_stime_sec": 0.032874,
+            "ru_minflt": 10742,
+            "ru_majflt": 0,
+            "ru_nvcsw": 27,
+            "ru_nivcsw": 24
+        },
+        "peak_mem_kb": 284132
+    }
+}

sim/csrc/filelist

@@ -0,0 +1,31 @@
+
+
+AR=ar
+DOTLIBS=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so 
+
+# This file is automatically generated by VCS. Any changes you make to it
+# will be overwritten the next time VCS is run
+VCS_LIBEXT=
+XTRN_OBJS=
+
+DPI_WRAPPER_OBJS = 
+DPI_STUB_OBJS = 
+# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
+include filelist.dpi
+PLI_STUB_OBJS = 
+include filelist.pli
+
+include filelist.hsopt
+
+include filelist.cu
+
+VCS_INCR_OBJS=
+
+
+AUGDIR=
+AUG_LDFLAGS=
+SHARED_OBJ_SO=
+
+
+
+VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)  

sim/csrc/filelist.cu

@@ -0,0 +1,50 @@
+PIC_LD=ld
+
+ARCHIVE_OBJS=
+ARCHIVE_OBJS += _12247_archive_1.so
+_12247_archive_1.so : archive.1/_12247_archive_1.a
+	@$(AR) -s $<
+	@$(PIC_LD) -shared  -Bsymbolic  -o .//../simv.daidir//_12247_archive_1.so --whole-archive $< --no-whole-archive
+	@rm -f $@
+	@ln -sf .//../simv.daidir//_12247_archive_1.so $@
+
+
+ARCHIVE_OBJS += _prev_archive_1.so
+_prev_archive_1.so : archive.1/_prev_archive_1.a
+	@$(AR) -s $<
+	@$(PIC_LD) -shared  -Bsymbolic  -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
+	@rm -f $@
+	@ln -sf .//../simv.daidir//_prev_archive_1.so $@
+
+
+
+VCS_ARC0 =_csrc0.so
+
+VCS_OBJS0 =objs/amcQw_d.o 
+
+
+O0_OBJS =
+
+$(O0_OBJS) : %.o: %.c
+	$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
+ 
+
+%.o: %.c
+	$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
+
+$(VCS_ARC0) : $(VCS_OBJS0)
+	$(PIC_LD) -shared  -Bsymbolic  -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
+	rm -f $(VCS_ARC0)
+	@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
+
+CU_UDP_OBJS = \
+
+
+CU_LVL_OBJS = \
+SIM_l.o 
+
+MAIN_OBJS = \
+
+
+CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
+

sim/csrc/filelist.hsopt

@@ -0,0 +1,13 @@
+rmapats_mop.o: rmapats.m
+	@/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/cgmop1  -tls_initexe  -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
+
+rmapats.o: rmapats.c
+	@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
+rmapats%.o: rmapats%.c
+	@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
+rmar.o: rmar.c
+	@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
+rmar%.o: rmar%.c
+	@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
+
+include filelist.hsopt.objs

sim/csrc/filelist.hsopt.llvm2_0.objs

@@ -0,0 +1 @@
+LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o

sim/csrc/filelist.hsopt.objs

@@ -0,0 +1,7 @@
+HSOPT_OBJS +=rmapats_mop.o  \
+    rmapats.o  \
+    rmar.o rmar_nd.o 
+
+include filelist.hsopt.llvm2_0.objs
+HSOPT_OBJS += $(LLVM_OBJS)
+

sim/csrc/filelist.pli

@@ -0,0 +1,4 @@
+PLI_STUB_OBJS += _vcs_pli_stub_.o
+_vcs_pli_stub_.o: _vcs_pli_stub_.c
+	@$(CC) -I/home/synopsys/vcs-mx/O-2018.09-1/include  -pipe -fPIC    -I/home/synopsys/vcs-mx/O-2018.09-1/include  -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
+	@strip -g _vcs_pli_stub_.o

sim/csrc/rmapats.c

@@ -0,0 +1,43 @@
+// file = 0; split type = patterns; threshold = 100000; total count = 0.
+#include <stdio.h>
+#include <stdlib.h>
+#include <strings.h>
+#include "rmapats.h"
+
+void  hsG_0__0 (struct dummyq_struct * I1288, EBLK  * I1282, U  I685);
+void  hsG_0__0 (struct dummyq_struct * I1288, EBLK  * I1282, U  I685)
+{
+    U  I1546;
+    U  I1547;
+    U  I1548;
+    struct futq * I1549;
+    struct dummyq_struct * pQ = I1288;
+    I1546 = ((U )vcs_clocks) + I685;
+    I1548 = I1546 & ((1 << fHashTableSize) - 1);
+    I1282->I727 = (EBLK  *)(-1);
+    I1282->I731 = I1546;
+    if (I1546 < (U )vcs_clocks) {
+        I1547 = ((U  *)&vcs_clocks)[1];
+        sched_millenium(pQ, I1282, I1547 + 1, I1546);
+    }
+    else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
+        I1282->I733 = (struct eblk *)peblkFutQ1Tail;
+        peblkFutQ1Tail->I727 = I1282;
+        peblkFutQ1Tail = I1282;
+    }
+    else if ((I1549 = pQ->I1189[I1548].I745)) {
+        I1282->I733 = (struct eblk *)I1549->I744;
+        I1549->I744->I727 = (RP )I1282;
+        I1549->I744 = (RmaEblk  *)I1282;
+    }
+    else {
+        sched_hsopt(pQ, I1282, I1546);
+    }
+}
+#ifdef __cplusplus
+extern "C" {
+#endif
+void SinitHsimPats(void);
+#ifdef __cplusplus
+}
+#endif

sim/csrc/rmar.c

@@ -0,0 +1,13 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "rmar0.h"
+
+// stubs for Hil functions
+#ifdef __cplusplus
+extern "C" {
+#endif
+void __Hil__Static_Init_Func__(void) {} 
+#ifdef __cplusplus
+}
+#endif
+

sim/csrc/rmar.h

@@ -0,0 +1,18 @@
+#ifndef _RMAR1_H_
+#define _RMAR1_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __DO_RMAHDR_
+#include "rmar0.h"
+#endif /*__DO_RMAHDR_*/
+
+extern UP rmaFunctionRtlArray[];
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sim/csrc/rmar0.h

@@ -0,0 +1,13 @@
+#ifndef _RMAR0_H_
+#define _RMAR0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sim/filelist.f

@@ -0,0 +1,12 @@
+../rtl/sync_fifo_128_to_64.v
+#../rtl/sync_fifo_64_to_128.v
+#../rtl/async_fifo.v
+#../rtl/wchannel.v
+../rtl/sync_fifo.v
+../rtl/rchannel.v
+#../tb/tb_sync_fifo_128_to_64.v
+#../tb/tb_async_fifo.v
+#../tb/tb_sync_fifo_64_to_128.v
+#../tb/tb_sync_fifo.v
+#../tb/tb_wchannel.v
+../tb/tb_rchannel.v

sim/novas_dump.log

@@ -0,0 +1,790 @@
+#######################################################################################
+# log primitive debug message of FSDB dumping                                         #
+# This is for R&D to analyze when there are issues happening when FSDB dump           #
+#######################################################################################
+ANF: vcsd_get_serial_mode_status('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_serial_mode_status')
+ANF: vcsd_enable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_enable_sva_success_callback')
+ANF: vcsd_disable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_disable_sva_success_callback')
+ANF: vcsd_get_thread_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_thread_id')
+ANF: vcsd_get_power_scope_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_power_scope_name')
+ANF: vcsd_begin_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_begin_no_value_var_info')
+ANF: vcsd_end_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_end_no_value_var_info')
+ANF: vcsd_remove_xprop_merge_mode_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
+ANF: vcsd_node_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_check_native_callback')
+ANF: vcsd_node_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_add_native_callback')
+ANF: vcsdIsNativeVc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsdIsNativeVc')
+ANF: vhpi_get_cb_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_get_cb_info')
+ANF: vhpi_free_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_free_handle')
+ANF: vhpi_fetch_vcsd_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vcsd_handle')
+ANF: vhpi_fetch_vpi_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vpi_handle')
+ANF: vhpi_has_verilog_parent('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_has_verilog_parent')
+ANF: vhpi_is_verilog_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_is_verilog_scope')
+ANF: scsd_xprop_is_enabled('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_is_enabled')
+ANF: scsd_xprop_sig_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_sig_is_promoted')
+ANF: scsd_xprop_int_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_int_xvalue')
+ANF: scsd_xprop_bool_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_bool_xvalue')
+ANF: scsd_xprop_enum_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_enum_xvalue')
+ANF: scsd_xprop_register_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
+ANF: scsd_xprop_delete_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
+ANF: scsd_xprop_get_merge_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_get_merge_mode')
+ANF: scsd_thread_get_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_get_info')
+ANF: scsd_thread_vc_init('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_vc_init')
+ANF: scsd_master_set_delta_sync_cbk('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_master_set_delta_sync_cbk')
+ANF: scsd_fgp_get_fsdb_cores('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_fgp_get_fsdb_cores')
+ANF: msvEnableDumpingMode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvEnableDumpingMode')
+ANF: msvGetVersion('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetVersion')
+ANF: msvGetInstProp('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstProp')
+ANF: msvIsSpiceEngineReady('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIsSpiceEngineReady')
+ANF: msvSetAddProbeCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAddProbeCallback')
+ANF: msvGetInstHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstHandle')
+ANF: msvGetProbeByInst('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeByInst')
+ANF: msvGetSigHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetSigHandle')
+ANF: msvGetProbeBySig('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeBySig')
+ANF: msvGetProbeInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeInfo')
+ANF: msvRelease('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRelease')
+ANF: msvSetVcCallbackFunc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetVcCallbackFunc')
+ANF: msvCheckVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvCheckVcCallback')
+ANF: msvAddVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvAddVcCallback')
+ANF: msvRemoveVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRemoveVcCallback')
+ANF: msvGetLatestValue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetLatestValue')
+ANF: msvSetEndofSimCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetEndofSimCallback')
+ANF: msvIgnoredProbe('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIgnoredProbe')
+ANF: msvGetThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetThruNetInfo')
+ANF: msvFreeThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvFreeThruNetInfo')
+ANF: PI_ace_get_output_time_unit('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_get_output_time_unit')
+ANF: PI_ace_sim_sync('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_sim_sync')
+ANF: msvGetRereadInitFile('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetRereadInitFile')
+ANF: msvSetBeforeRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetBeforeRereadCallback')
+ANF: msvSetAfterRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAfterRereadCallback')
+ANF: msvSetForceCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetForceCallback')
+ANF: msvSetReleaseCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetReleaseCallback')
+ANF: msvGetForceStatus('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetForceStatus')
+ANF: vdi_fn_trigger_native_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_trigger_native_init_force')
+ANF: vdi_set_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_set_native_callback')
+ANF: vdi_fn_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_check_native_callback')
+ANF: vdi_fn_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_add_native_callback')
+ANF: vhdi_dt_get_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_type')
+ANF: vhdi_dt_get_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_key')
+ANF: vhdi_dt_get_vhdl_enum_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
+ANF: vhdi_dt_get_vhdl_physical_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
+ANF: vhdi_dt_get_vhdl_array_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
+ANF: vhdi_dt_get_vhdl_record_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
+ANF: vhdi_def_traverse_module('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_module')
+ANF: vhdi_def_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_scope')
+ANF: vhdi_def_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_variable')
+ANF: vhdi_def_get_module_id_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
+ANF: vhdi_def_get_handle_by_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_handle_by_module_id')
+ANF: vhdi_def_get_variable_info_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
+ANF: vhdi_def_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_free')
+ANF: vhdi_ist_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_scope')
+ANF: vhdi_ist_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_variable')
+ANF: vhdi_ist_convert_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_convert_by_vhpi')
+ANF: vhdi_ist_clone('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_clone')
+ANF: vhdi_ist_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_free')
+ANF: vhdi_ist_hash_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_hash_key')
+ANF: vhdi_ist_compare('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_compare')
+ANF: vhdi_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_value_addr')
+ANF: vhdi_set_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_scsd_callback')
+ANF: vhdi_cbk_set_force_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_cbk_set_force_callback')
+ANF: vhdi_trigger_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_trigger_init_force')
+ANF: vhdi_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_check_scsd_callback')
+ANF: vhdi_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_add_scsd_callback')
+ANF: vhdi_ist_remove_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_remove_scsd_callback')
+ANF: vhdi_ist_get_scsd_user_data('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_scsd_user_data')
+ANF: vhdi_add_time_change_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_add_time_change_callback')
+ANF: vhdi_get_real_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_real_value_by_value_addr')
+ANF: vhdi_get_64_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_64_value_by_value_addr')
+ANF: vhdi_xprop_inst_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_xprop_inst_is_promoted')
+ANF: vdi_ist_convert_by_vhdi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_ist_convert_by_vhdi')
+ANF: vhdi_ist_get_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_module_id')
+ANF: vhdi_refine_foreign_scope_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_refine_foreign_scope_type')
+ANF: vhdi_flush_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_flush_callback')
+ANF: vhdi_set_orig_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_orig_name')
+ANF: vhdi_set_dump_pt('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_dump_pt')
+ANF: vhdi_get_fsdb_option('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_fsdb_option')
+ANF: vhdi_fgp_get_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_fgp_get_mode')
+ANF: vhdi_node_register_composite_var('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_register_composite_var')
+ANF: vhdi_node_analysis('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_analysis')
+ANF: vhdi_node_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_id')
+ANF: vhdi_node_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
+ANF: vhdi_node_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
+ANF: vhdi_node_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_get_value_addr')
+VCS compile option:
+ option[0]: /home/ICer/ic_prjs/mc/sim/simv
+ option[1]: -sml=verdi
+ option[2]: +fsdb+gate=off
+ option[3]: -ucli2Proc
+ option[4]: -ucli
+ option[5]: -l
+ option[6]: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
+ option[7]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
+ option[8]: -Mcc=gcc
+ option[9]: -Mcplusplus=g++
+ option[10]: -Masflags=
+ option[11]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include 
+ option[12]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
+ option[13]: -Mldflags= -rdynamic 
+ option[14]: -Mout=simv
+ option[15]: -Mamsrun=
+ option[16]: -Mvcsaceobjs=
+ option[17]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so 
+ option[18]: -Mexternalobj=
+ option[19]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
+ option[20]: -Mcrt0=
+ option[21]: -Mcrtn=
+ option[22]: -Mcsrc=
+ option[23]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl 
+ option[24]: -Xvcs_run_simv=1
+ option[25]: -timescale=1ns/1ps
+ option[26]: -Xcbug=0x1
+ option[27]: -o
+ option[28]: simv
+ option[29]: -full64
+ option[30]: +vc
+ option[31]: +v2k
+ option[32]: -debug_access+all
+ option[33]: +vpi
+ option[34]: +vcsd1
+ option[35]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
+ option[36]: -picarchive
+ option[37]: +cli+4
+ option[38]: -debug=3
+ option[39]: +memcbk
+ option[40]: -P
+ option[41]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+ option[42]: -fsdb
+ option[43]: -sverilog
+ option[44]: +vpi
+ option[45]: -gen_obj
+ option[46]: -f
+ option[47]: filelist.f
+ option[48]: -load
+ option[49]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
+ option[50]: timescale=1ns/1ps
+Chronologic Simulation VCS Release O-2018.09-1_Full64
+Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
+CPU cores: 8
+Limit information:
+======================================
+cputime		unlimited
+filesize		unlimited
+datasize		unlimited
+stacksize		unlimited
+coredumpsize		0 kbytes
+memoryuse		unlimited
+vmemoryuse		unlimited
+descriptors		4096
+memorylocked		64 kbytes
+maxproc		4096
+======================================
+(Special)Runtime environment variables:
+
+Runtime environment variables:
+XDG_VTNR=1
+LC_PAPER=zh_CN.UTF-8
+SSH_AGENT_PID=3332
+XDG_SESSION_ID=1
+HOSTNAME=IC_EDA
+LC_MONETARY=zh_CN.UTF-8
+DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
+NOVAS_SYNC_MOTIF_DISP=
+IMSETTINGS_INTEGRATE_DESKTOP=yes
+SHELL=/bin/bash
+VTE_VERSION=5204
+XDG_MENU_PREFIX=gnome-
+TERM=xterm-256color
+MAKEFLAGS=
+HISTSIZE=1000
+SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font
+QUESTASIM_HOME=/home/mentor/questasim
+GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
+LC_NUMERIC=zh_CN.UTF-8
+SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont
+QTDIR=/usr/lib/qt-3.3
+QTINC=/usr/lib/qt-3.3/include
+LC_ALL=C
+QT_GRAPHICSSYSTEM_CHECKED=1
+IMSETTINGS_MODULE=none
+USER=ICer
+LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
+LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
+GNOME_TERMINAL_SERVICE=:1.106
+XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls
+MAKE_TERMOUT=/dev/pts/1
+SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
+DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
+SNPSLMD_LICENSE_FILE=27000@IC_EDA
+USERNAME=ICer
+SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3198,unix/unix:/tmp/.ICE-unix/3198
+MAKELEVEL=1
+MFLAGS=
+MMSIMHOME=/home/cadence/MMSIM151
+GNOME_SHELL_SESSION_MODE=classic
+DESKTOP_SESSION=gnome-classic
+PATH=/bin:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
+MAIL=/var/spool/mail/ICer
+PT_HOME=/home/synopsys/pts/O-2018.06-SP1
+QT_IM_MODULE=ibus
+CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
+VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
+XDG_SESSION_TYPE=x11
+MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
+PWD=/home/ICer/ic_prjs/mc/sim
+XMODIFIERS=@im=none
+VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
+SYS_PROG_NAME=verdi
+MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
+LANG=C
+GDM_LANG=zh_CN.UTF-8
+KDEDIRS=/usr
+VCS_ARCH_OVERRIDE=linux
+LC_MEASUREMENT=zh_CN.UTF-8
+CDSHOME=/home/cadence/IC617
+SYS_INST_DIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2
+GDMSESSION=gnome-classic
+XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
+QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
+HISTCONTROL=ignoredups
+SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
+DBUS_STARTER_BUS_TYPE=session
+HOME=/home/ICer
+XDG_SEAT=seat0
+RISCV=/home/Riscv_Tools
+SHLVL=3
+MGC_HOME=/home/mentor/
+ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
+VERDI_ORIGNAL_LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
+MGC_LICENSE_FILE=/home/mentor//license/license.dat
+GNOME_DESKTOP_SESSION_ID=this-is-deprecated
+CADHOME=/home/cadence
+XDG_SESSION_DESKTOP=gnome-classic
+LOGNAME=ICer
+DC_HOME=/home/synopsys/syn/O-2018.06-SP1
+MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
+QTLIB=/usr/lib/qt-3.3/lib
+SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
+MAKE_TERMERR=/dev/pts/1
+XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
+DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
+NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc
+SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb
+CDS_LIC_FILE=/home/cadence/license/cadence.dat
+SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
+LESSOPEN=||/usr/bin/lesspipe.sh %s
+SCL_HOME=/home/synopsys/scl/2018.06
+WINDOWPATH=1
+LD_NOVERSION=1
+XDG_RUNTIME_DIR=/run/user/1000
+SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
+DISPLAY=:0
+QT_PLUGIN_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/plugins
+LC_HOME=/home/synopsys/lc/O-2018.06-SP1
+XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
+INCISIVE_HOME=/home/cadence/INCISIVE152
+LC_TIME=zh_CN.UTF-8
+XAUTHORITY=/run/gdm/auth-for-ICer-JizYR8/database
+COLORTERM=truecolor
+PS_HWPC=OFF
+NOVAS_LC_ALL=C
+NOVAS_SIGNAL_BASE_EXTRACTION=1
+SIGNAL_BASE_EXTRACTION=1
+NOVAS_VERDI_SVTB_BETA=1
+VERDI_SVTB_BETA=1
+NOVAS_VERDI_SVTB_ALPHA=1
+VERDI_SVTB_ALPHA=1
+NOVAS_VERDI_TB_HT=1
+VERDI_TB_HT=1
+NOVAS_WAVE_REDRAW_ALLVC=1
+WAVE_REDRAW_ALLVC=1
+NOVAS_TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
+TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
+XKEYSYMDB=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/XKeysymDB2.1
+XLOCALEDIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/locale
+NOVAS_SIGNAL_BASED_BA=0
+SIGNAL_BASED_BA=0
+SYNOPSYS_SIM=/home/synopsys/vcs-mx/O-2018.09-1
+DISABLE_LIBRARY_MAP_CHECK=1
+SNPS_SIM_DEFAULT_GUI=verdi
+FSDB_FILE=/home/ICer/ic_prjs/mc/sim/inter.fsdb
+VCS_UCLI_STDIN_BLOCKING=1
+FSDB_VHDL_PROTECTED=1
+FSDB_RD_IR_ENABLE=1
+FSDB_SVA_STATUS=1
+VCS_HEAP_EXEC=true
+VCS_PATHMAP_PRELOAD_DONE=1
+VCS_STACK_EXEC=true
+VCS_EXEC_DONE=1
+VCS_STOP_SAFE=1
+DVE_SIM_SELECT_LOOP=on
+Runtime command line arguments:
+argv[0]=/home/ICer/ic_prjs/mc/sim/simv
+argv[1]=-sml=verdi
+argv[2]=+fsdb+gate=off
+argv[3]=-ucli2Proc
+argv[4]=-ucli
+argv[5]=-l
+argv[6]=/home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
+326 profile - 100
+          CPU/Mem usage: 0.000 sys,  0.050 user,  236.30M mem
+327 Tue Aug  5 21:54:29 2025
+328 pliAppInit
+329 ndpGetenv(FSDB_FILE): /home/ICer/ic_prjs/mc/sim/inter.fsdb
+330 ndpGetenv(FSDB_SVA_STATUS): 1
+331 ndpGetenv(FSDB_VHDL_PROTECTED): 1
+332 FSDB_GATE & FSDB_RTL is disabled.
+333 Enable Parallel Dumping.
+334 pliAppMiscSet: New Sim Round
+335 pliEntryInit
+336 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
+337 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
+338 (C) 1996 - 2019 by Synopsys, Inc.
+339 sps_tcl_fsdbDumpfile_main at 0
+340 argv[0]: /home/ICer/ic_prjs/mc/sim/inter.fsdb
+341 *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
+342 compile option from '/home/ICer/ic_prjs/mc/sim/simv.daidir/vcs_rebuild'.
+343   "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
+344 sps_tcl_fsdbDumpflush_vd_main
+345 *Verdi* : Flush all FSDB Files at 0 ps.
+346 FSDB_VCS_ENABLE_FAST_VC is enable
+347 sps_tcl_fsdbDumpvars_vd_main
+348 argv[0]: 0
+349 argv[1]: tb_rchannel.array2axi_rdata
+350 argv[2]: +all
+351 argv[3]: +trace_process
+352 [spi_vcs_vd_ppi_create_root]: no upf option
+353 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
+354 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
+355 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  329.37M mem
+                   incr: 0.000 sys,  0.000 user,  2.20M mem
+                   accu: 0.000 sys,  0.000 user,  2.20M mem
+              accu incr: 0.000 sys,  0.000 user,  2.20M mem
+
+          Count usage: 1 var,  1 idcode,  1 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+356 Tue Aug  5 21:54:30 2025
+357 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  1.05M mem
+                   accu: 0.000 sys,  0.000 user,  3.26M mem
+              accu incr: 0.000 sys,  0.000 user,  1.05M mem
+
+          Count usage: 1 var,  1 idcode,  1 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+358 Tue Aug  5 21:54:30 2025
+359 sps_tcl_fsdbDumpvars_vd_main
+360 argv[0]: 0
+361 argv[1]: tb_rchannel.array2axi_rdata_valid
+362 argv[2]: +all
+363 argv[3]: +trace_process
+364 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
+365 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 2 var,  2 idcode,  2 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+366 Tue Aug  5 21:54:30 2025
+367 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 2 var,  2 idcode,  2 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+368 Tue Aug  5 21:54:30 2025
+369 sps_tcl_fsdbDumpvars_vd_main
+370 argv[0]: 0
+371 argv[1]: tb_rchannel.axi_s_araddr
+372 argv[2]: +all
+373 argv[3]: +trace_process
+374 *Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
+375 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 3 var,  3 idcode,  3 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+376 Tue Aug  5 21:54:30 2025
+377 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 3 var,  3 idcode,  3 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+378 Tue Aug  5 21:54:30 2025
+379 sps_tcl_fsdbDumpvars_vd_main
+380 argv[0]: 0
+381 argv[1]: tb_rchannel.axi_s_arlen
+382 argv[2]: +all
+383 argv[3]: +trace_process
+384 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
+385 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 4 var,  4 idcode,  4 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+386 Tue Aug  5 21:54:30 2025
+387 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 4 var,  4 idcode,  4 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+388 Tue Aug  5 21:54:30 2025
+389 sps_tcl_fsdbDumpvars_vd_main
+390 argv[0]: 0
+391 argv[1]: tb_rchannel.axi_s_arready
+392 argv[2]: +all
+393 argv[3]: +trace_process
+394 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
+395 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 5 var,  5 idcode,  5 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+396 Tue Aug  5 21:54:30 2025
+397 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 5 var,  5 idcode,  5 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+398 Tue Aug  5 21:54:30 2025
+399 sps_tcl_fsdbDumpvars_vd_main
+400 argv[0]: 0
+401 argv[1]: tb_rchannel.axi_s_arvalid
+402 argv[2]: +all
+403 argv[3]: +trace_process
+404 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
+405 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 6 var,  6 idcode,  6 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+406 Tue Aug  5 21:54:30 2025
+407 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.060 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 6 var,  6 idcode,  6 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+408 Tue Aug  5 21:54:30 2025
+409 sps_tcl_fsdbDumpvars_vd_main
+410 argv[0]: 0
+411 argv[1]: tb_rchannel.axi_s_rdata
+412 argv[2]: +all
+413 argv[3]: +trace_process
+414 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
+415 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.010 user,  0.00M mem
+                   accu: 0.000 sys,  0.010 user,  0.00M mem
+              accu incr: 0.000 sys,  0.010 user,  0.00M mem
+
+          Count usage: 7 var,  7 idcode,  7 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+416 Tue Aug  5 21:54:30 2025
+417 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.010 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 7 var,  7 idcode,  7 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+418 Tue Aug  5 21:54:30 2025
+419 sps_tcl_fsdbDumpvars_vd_main
+420 argv[0]: 0
+421 argv[1]: tb_rchannel.axi_s_rlast
+422 argv[2]: +all
+423 argv[3]: +trace_process
+424 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
+425 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.100 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 8 var,  8 idcode,  8 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+426 Tue Aug  5 21:54:30 2025
+427 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.100 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 8 var,  8 idcode,  8 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+428 Tue Aug  5 21:54:30 2025
+429 sps_tcl_fsdbDumpvars_vd_main
+430 argv[0]: 0
+431 argv[1]: tb_rchannel.axi_s_rvalid
+432 argv[2]: +all
+433 argv[3]: +trace_process
+434 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
+435 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.010 sys,  0.000 user,  0.00M mem
+                   accu: 0.010 sys,  0.000 user,  0.00M mem
+              accu incr: 0.010 sys,  0.000 user,  0.00M mem
+
+          Count usage: 9 var,  9 idcode,  9 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+436 Tue Aug  5 21:54:30 2025
+437 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.010 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 9 var,  9 idcode,  9 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+438 Tue Aug  5 21:54:30 2025
+439 sps_tcl_fsdbDumpvars_vd_main
+440 argv[0]: 0
+441 argv[1]: tb_rchannel.clk
+442 argv[2]: +all
+443 argv[3]: +trace_process
+444 *Verdi* : Dumping the signal (tb_rchannel.clk).
+445 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 10 var,  10 idcode,  10 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+446 Tue Aug  5 21:54:30 2025
+447 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 10 var,  10 idcode,  10 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+448 Tue Aug  5 21:54:30 2025
+449 sps_tcl_fsdbDumpvars_vd_main
+450 argv[0]: 0
+451 argv[1]: tb_rchannel.rframe_data
+452 argv[2]: +all
+453 argv[3]: +trace_process
+454 *Verdi* : Dumping the signal (tb_rchannel.rframe_data).
+455 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 11 var,  11 idcode,  11 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+456 Tue Aug  5 21:54:30 2025
+457 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 11 var,  11 idcode,  11 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+458 Tue Aug  5 21:54:30 2025
+459 sps_tcl_fsdbDumpvars_vd_main
+460 argv[0]: 0
+461 argv[1]: tb_rchannel.rframe_ready
+462 argv[2]: +all
+463 argv[3]: +trace_process
+464 *Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
+465 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 12 var,  12 idcode,  12 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+466 Tue Aug  5 21:54:30 2025
+467 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 12 var,  12 idcode,  12 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+468 Tue Aug  5 21:54:30 2025
+469 sps_tcl_fsdbDumpvars_vd_main
+470 argv[0]: 0
+471 argv[1]: tb_rchannel.rframe_valid
+472 argv[2]: +all
+473 argv[3]: +trace_process
+474 *Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
+475 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 13 var,  13 idcode,  13 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+476 Tue Aug  5 21:54:30 2025
+477 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 13 var,  13 idcode,  13 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+478 Tue Aug  5 21:54:30 2025
+479 sps_tcl_fsdbDumpvars_vd_main
+480 argv[0]: 0
+481 argv[1]: tb_rchannel.rst_n
+482 argv[2]: +all
+483 argv[3]: +trace_process
+484 *Verdi* : Dumping the signal (tb_rchannel.rst_n).
+485 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 14 var,  14 idcode,  14 callback
+                 incr: 1 var,  1 idcode,  1 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 1 var,  1 idcode,  1 callback
+486 Tue Aug  5 21:54:30 2025
+487 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.110 sys,  0.070 user,  330.42M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  0.00M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 14 var,  14 idcode,  14 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 1 var,  1 idcode,  1 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+488 Tue Aug  5 21:54:30 2025
+489 sps_tcl_fsdbDumpflush_vd_main
+490 *Verdi* : Flush all FSDB Files at 0 ps.
+491 sps_tcl_fsdbDumpflush_vd_main
+492 *Verdi* : Flush all FSDB Files at 0 ps.
+493 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_rchannel.v(98)
+494 argv[0]: (tb.fsdb)
+495 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_rchannel.v(99)
+496 argv[0]: (0)
+497 argv[1]: (handle) tb_rchannel
+498 argv[2]: (+all)
+499 *Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
+500 *Verdi* : Enable +all dumping.
+501 *Verdi* : End of traversing.
+502 pliAppHDL_DumpVarComplete traverse var: profile - 
+          CPU/Mem usage: 0.120 sys,  0.070 user,  333.21M mem
+                   incr: 0.000 sys,  0.000 user,  1.06M mem
+                   accu: 0.000 sys,  0.000 user,  1.06M mem
+              accu incr: 0.000 sys,  0.000 user,  1.06M mem
+
+          Count usage: 129 var,  85 idcode,  72 callback
+                 incr: 115 var,  71 idcode,  58 callback
+                 accu: 115 var,  71 idcode,  58 callback
+            accu incr: 115 var,  71 idcode,  58 callback
+503 Tue Aug  5 21:54:32 2025
+504 pliAppHDL_DumpVarComplete: profile - 
+          CPU/Mem usage: 0.120 sys,  0.070 user,  333.21M mem
+                   incr: 0.000 sys,  0.000 user,  0.00M mem
+                   accu: 0.000 sys,  0.000 user,  1.06M mem
+              accu incr: 0.000 sys,  0.000 user,  0.00M mem
+
+          Count usage: 129 var,  85 idcode,  72 callback
+                 incr: 0 var,  0 idcode,  0 callback
+                 accu: 115 var,  71 idcode,  58 callback
+            accu incr: 0 var,  0 idcode,  0 callback
+505 Tue Aug  5 21:54:32 2025
+506 sps_tcl_fsdbDumpflush_vd_main
+507 *Verdi* : Flush all FSDB Files at 365,000 ps.
+508 End of simulation at 365000
+509 Tue Aug  5 22:01:50 2025
+510 Begin FSDB profile info:
+511 FSDB Writer : bc1(186) bcn(270) mtf/stf(0/4)
+FSDB Writer elapsed time : flush(0.010457) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
+FSDB Writer cpu time : MT Compression : 0
+512 End FSDB profile info
+513 Parallel profile    -  Flush:22 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
+514                        ProduceTime:0.212615372 ConsumerTime:0.000000000 Buffer:64MB
+515 SimExit
+516 Sim process exit

sim/simv.daidir/.vcs.timestamp

@@ -0,0 +1,148 @@
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+39
++cli+4
++itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
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++vpi
++vpi
+-Mamsrun=
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+-Mcc=gcc
+-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
+-Mcplusplus=g++
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+-Mcrtn=
+-Mcsrc=
+-Mexternalobj=
+-Mldflags= -rdynamic
+-Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
+-Mout=simv
+-Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
+-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
+-Mvcsaceobjs=
+-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
+-P
+-Xcbug=0x1
+-Xvcs_run_simv=1
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+-f filelist.f
+-fsdb
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+-o simv
+-picarchive
+-sverilog
+-timescale=1ns/1ps
+/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
+/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+90
+sysc_uni_pwd=/home/ICer/ic_prjs/mc/sim
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+WINDOWPATH=1
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+VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
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+TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
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+SSH_AGENT_PID=3332
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+GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
+GNOME_SHELL_SESSION_MODE=classic
+GNOME_DESKTOP_SESSION_ID=this-is-deprecated
+GDM_LANG=zh_CN.UTF-8
+GDMSESSION=gnome-classic
+DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
+DESKTOP_SESSION=gnome-classic
+DC_HOME=/home/synopsys/syn/O-2018.06-SP1
+DBUS_STARTER_BUS_TYPE=session
+DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
+DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
+COLORTERM=truecolor
+CDS_LIC_FILE=/home/cadence/license/cadence.dat
+CDSHOME=/home/cadence/IC617
+CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
+CADHOME=/home/cadence
+0
+7
+1754401710 ../tb/tb_rchannel.v
+1754402050 ../rtl/rchannel.v
+1754372349 ../rtl/sync_fifo.v
+1754381818 ../rtl/sync_fifo_128_to_64.v
+1754401741 filelist.f
+1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
+4
+1539402341 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so
+1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
+1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
+1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
+1754402058 simv.daidir
+-1 partitionlib

sim/simv.daidir/build_db

@@ -0,0 +1,4 @@
+#!/bin/sh -e
+# This file is automatically generated by VCS.  Any changes you make
+# to it will be overwritten the next time VCS is run.
+vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all'  -static_dbgen_only -daidir=$1 2>&1

sim/simv.daidir/cc/cc_bcode.db

@@ -0,0 +1,11 @@
+sid tb_rchannel
+bcid 0 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET
+bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET
+bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU CALL_ARG_VAL,6,0 NOT AND AND RET
+bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND AND RET
+bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_EQU OR AND RET
+bcid 5 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,5,0 OPT_CONST,63 WIDTH,1 M_EQU OR AND RET
+bcid 6 6 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 XOR WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,1 M_EQU AND RET
+bcid 7 7 WIDTH,3 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
+bcid 8 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 PAD SUBTRACT OPT_CONST,8 WIDTH,1 M_EQU RET
+bcid 9 9 WIDTH,4 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET

sim/simv.daidir/cc/cc_dummy_file

@@ -0,0 +1,2 @@
+Dummy_file
+Missing line/file info

sim/simv.daidir/cgname.json

@@ -0,0 +1,20 @@
+{
+    "std": [
+        "std",
+        "reYIK",
+        "module",
+        1
+    ],
+    "tb_rchannel": [
+        "tb_rchannel",
+        "TJvMf",
+        "module",
+        2
+    ],
+    "...MASTER...": [
+        "SIM",
+        "amcQw",
+        "module",
+        3
+    ]
+}

sim/simv.daidir/debug_dump/.version

@@ -0,0 +1,4 @@
+O-2018.09-1_Full64
+Build Date = Oct 12 2018 20:38:10
+RedHat
+Compile Location: /home/ICer/ic_prjs/mc/sim

sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db

@@ -0,0 +1,9 @@
+#!/bin/sh -h 
+PYTHONHOME=/home/synopsys/vcs-mx/O-2018.09-1/etc/search/pyh
+export PYTHONHOME
+PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
+export PYTHONPATH
+LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
+export LD_LIBRARY_PATH
+/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe  -z  "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_h3ehMU.xml.gz" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
+\mv "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db"

sim/simv.daidir/debug_dump/fsearch/check_fsearch_db

@@ -0,0 +1,57 @@
+#!/bin/sh -h 
+
+FILE_PATH="/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch"
+lockfile="${FILE_PATH}"/lock
+
+FSearch_lock_release() {
+   echo "" > /dev/null
+}
+create_fsearch_db_ctrl() {
+    if [ -s "${FILE_PATH}"/fsearch.stat ]; then
+        if [ -s "${FILE_PATH}"/fsearch.log ]; then
+            echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
+        else
+            cat "${FILE_PATH}"/fsearch.stat
+        fi
+        return
+    fi
+    nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
+    MY_PID=`echo $!`
+    BUILDER="pid ${MY_PID} ${USER}@${hostname}"
+    echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
+    echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
+    return
+}
+
+dir_name=`/bin/dirname "$0"`
+if [ "${dir_name}" = "." ]; then
+    cd $dir_name
+    dir_name=`/bin/pwd`
+fi
+if [ -d "$dir_name"/../../../../../../../.. ]; then
+    cd "$dir_name"/../../../../../../../..
+fi
+
+if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
+    if [ ! -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
+        if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
+            trap FSearch_lock_release EXIT
+            (
+                flock 193
+                create_fsearch_db_ctrl "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
+                exit 193
+            ) 193> "$lockfile"
+            rstat=$?
+            if [ "${rstat}"x != "193x" ]; then
+                exit $rstat
+            fi
+        else
+            "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
+            if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
+               rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
+            fi
+        fi
+    elif [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
+       rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
+    fi
+fi

sim/simv.daidir/debug_dump/src_files_verilog

@@ -0,0 +1,4 @@
+/home/ICer/ic_prjs/mc/rtl/rchannel.v
+/home/ICer/ic_prjs/mc/rtl/sync_fifo.v
+/home/ICer/ic_prjs/mc/rtl/sync_fifo_128_to_64.v
+/home/ICer/ic_prjs/mc/tb/tb_rchannel.v

sim/simv.daidir/debug_dump/topmodules

@@ -0,0 +1 @@
+~<7E>

sim/simv.daidir/external_functions

@@ -0,0 +1,78 @@
+pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
+pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC 
+pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC 
+pli $dumpportson DumpPortsOnCALL - DumpPortsMISC 
+pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC 
+pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC 
+pli $simlearn simLearnCall simLearnCheck simLearnMisc 
+pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC 
+pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC 
+pli $countdrivers CountDriversCALL - - 
+pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC 

sim/simv.daidir/saifNetInfo.db

@@ -0,0 +1 @@
+0

sim/simv.daidir/simv.kdb

@@ -0,0 +1,16 @@
+rc file Version 1.0
+
+[Design]
+COMPILE_PATH=/home/ICer/ic_prjs/mc/sim
+SystemC=FALSE
+UUM=FALSE
+KDB=FALSE
+USE_NOVAS_HOME=FALSE
+COSIM=FALSE
+TOP=tb_rchannel 
+OPTION=-ssz -ssv -ssy 
+ELAB_OPTION=-ssz -ssv -ssy 
+
+[Value]
+WREALX=ffff534e50535f58
+WREALZ=ffff534e50535f5a

sim/simv.daidir/vcs_rebuild

@@ -0,0 +1,4 @@
+#!/bin/sh -e
+# This file is automatically generated by VCS.  Any changes you make
+# to it will be overwritten the next time VCS is run.
+vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1

sim/simv.daidir/vcselab_master_hsim_elabout.db

@@ -0,0 +1,673 @@
+hsDirType                          	1
+fHsimDesignHasDebugNodes           	61
+fNSParam                           	1024
+fLargeSizeSdfTest                  	0
+fHsimDelayGateMbme                 	0
+fNoMergeDelays                     	0
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+hsimLevelizeDone                   	1
+fHsimCompressDiag                  	1
+fHsimPowerOpt                      	0
+fLoopReportElab                    	0
+fHsimRtl                           	0
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+fHsimDynamicCcnHeur                	1
+fHsimPvcs                          	0
+fHsimPvcsCcn                       	0
+fHsimOldLdr                        	0
+fHsimSingleDB                      	1
+uVfsGcLimit                        	50
+fHsimCompatSched                   	0
+fHsimCompatOrder                   	0
+fHsimTransUsingdoMpd32             	0
+fHsimDynamicElabForGates           	1
+fHsimDynamicElabForVectors         	0
+fHsimDynamicElabForVectorsAlways   	0
+fHsimDynamicElabForVectorsMinputs  	0
+fHsimDeferForceSelTillReElab       	0
+fHsimModByModElab                  	1
+fSvNettRealResType                 	0
+fHsimExprID                        	1
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+fHsimExprPrune                     	0
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+fHsimNewChangeCheckFrankch         	1
+fHsimNoSched0Front                 	0
+fHsimNoSched0FrontForMd            	1
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+fHsimNtbVl                         	0
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+fHsimICDiag                        	0
+fHsimNewCSDF                       	1
+vcselabIncrMode                    	2
+fHsimMPPackDelay                   	0
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+fHsimPartTest                      	0
+fHsimTestChangeCheck               	0
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+fHsimTestNState                    	0
+fHsimPartDebug                     	0
+fHsimPartFlags                     	0
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+fHsimDisableRootSigModeOpt         	0
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+fHsimUnifInterfaceFlowXmrDiag      	0
+fHsimUnifInterfaceMultiDrvChk      	1
+fHsimXVirForGenerateScope          	0
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+fHsimCongruencyFFDbsFix            	0
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+fHsimDeraceClockDataUdp            	0
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+fHsimCongruencyPCInl               	0
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+fHsimCongruencyEveBus              	0
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+fHsimCcnOpt                        	1
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+fHsimSmdSimProf                    	0
+fHsimSgdDiag                       	0
+fHsimRtDiagLite                    	0
+fHsimRtDiagLiteCevent              	100
+fHsimRtDiag                        	0
+fHsimSkRtDiag                      	0
+fHsimDDBSRtdiag                    	0
+fHsimDbg                           	0
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+fHsimMdbDebugOptP1                 	0
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+fHsimMdbMemOpt                     	0
+hsimRandValue                      	0
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+fHsimSimTimeProfile                	0
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+fHsimElabMemNodesProfile           	0
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+fHsimFileProfile                   	0
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+fHsimAllTaskFuncXmrs               	0
+fHsimPageArray                     	16383
+fHsimPageControls                  	16383
+hsDfsNodePageElems                 	0
+hsNodePageElems                    	0
+hsFlatNodePageElems                	0
+hsGateMapPageElems                 	0
+hsGateOffsetPageElems              	0
+hsGateInputOffsetPageElems         	0
+hsDbsOffsetPageElems               	0
+hsMinPulseWidthPageElems           	0
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+hsNodeDownPatternPageElems         	0
+hsNodeUpOffsetPageElems            	0
+hsNodeEblkOffsetPageElems          	0
+hsNodeDownOffsetPageElems          	0
+hsNodeUpdateOffsetPageElems        	0
+hsSdfOffsetPageElems               	0
+fHsimPageAllLevelData              	0
+fHsimAggrCg                        	0
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+fHsimAmsTunneling                  	0
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+fHsimVcsInterface                  	1
+fHsimVcsInterfaceAlias             	1
+fHsimSVTypesIntf                   	1
+fUnifiedAssertCtrlDiag             	0
+fHsimEnable2StateScal              	0
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+fHsimModInlineDbg                  	0
+fHsimPCDrvLoadDbg                  	0
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+fHsimRtlProcessingNeeded           	0
+fHsimGrpByGrpElab                  	0
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+fHsimNoParentSplitPC               	0
+fHsimNusymMode                     	0
+fHsimOneIntfPart                   	0
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+fHsimCompressFlatDb                	0
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+fHsimMdbVectorizeInstances         	0
+fHsimMdbSplitGates                 	0
+fHsimDeleteInstances               	0
+fHsimUserDeleteInstances           	0
+fHsimDeleteGdb                     	0
+fHsimDeleteInstancesMdb            	0
+fHsimShortInstMap                  	0
+fHsimMdbVectorizationDump          	0
+fHsimScanVectorize                 	0
+fHsimParallelScanVectorize         	0
+noInstsInVectorization             	0
+cHsimNonReplicatedInstances        	0
+fHsimScanRaptor                    	0
+fHsimConfigFileCount               	0
+fHsimVectorConstProp               	0
+fHsimPromoteParam                  	0
+fHsimNoVecInRaptor                 	0
+fRaptorDumpVal                     	0
+fRaptorVecNodes                    	0
+fRaptorVecNodes2                   	0
+fRaptorNonVecNodes                 	0
+fRaptorBdrNodes                    	0
+fRaptorVecGates                    	0
+fRaptorNonVecGates                 	0
+fRaptorTotalNodesBeforeVect        	0
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+fHsimCountRaptorBits               	0
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+fHsimNewEvcdMX                     	0
+fHsimNewEvcdVecRoot                	1
+fHsimNewEvcdForce                  	1
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+fHsimNewEvcdObnDrv                 	1
+fHsimNewEvcdW                      	1
+fHsimNewEvcdWTest                  	0
+fHsimEvcdDbgFlags                  	0
+fHsimDumpOffsetData                	1
+fFlopGlitchDetect                  	0
+fHsimClkGlitch                     	0
+fHsimGlitchDumpOnce                	0
+fHsimDynamicElab                   	1
+fHsimCgVectors2Debug               	0
+fHsimOdeDynElab                    	0
+fHsimOdeDynElabDiag                	0
+fHsimOdeSeqUdp                     	0
+fHsimOdeSeqUdpXEdge                	0
+fHsimOdeSeqUdpDbg                  	0
+fHsimOdeRmvSched0                  	0
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+fHsimRtlDbsList                    	0
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+fHsimPeXmr                         	0
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+fHsimUdpDbs                        	0
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+fFsdbGateOnepassTraverse           	0
+fHsimAllowVecGateInVpd             	1
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+fHsimAllowAlwaysCombCmpDvcSimv     	0
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+fHsimMakeAllP2SPrimary             	0
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+fHsimNoCcnDump                     	0
+fHsimFsdbProfDiag                  	0
+fVpdSeqGate                        	0
+fVpdHsIntVecGate                   	0
+fVpdHsCmplxVecGate                 	0
+fVpdHsVecGateDiags                 	0
+fSeqGateCodePatch                  	0
+fVpdLongFaninOpt                   	0
+fVpdSeqLongFaninOpt                	0
+fVpdNoLoopDetect                   	0
+fVpdNoSeqLoopDetect                	0
+fVpdOptAllowConstDriver            	0
+fVpdAllowCellReconstruction        	0
+fVpdRtlForSharedLib                	0
+fHsimVpdOptGate                    	1
+fHsimVpdOptDelay                   	0
+fHsimVpdOptMPDelay                 	0
+fHsimCbkOptDiag                    	0
+fHsimSK                            	0
+fHsimSharedKernel                  	1
+fHsimOnepass                       	0
+fHsimStitchNew                     	0
+fHsimParallelLevelize              	0
+fHsimParallelLevelizeDbg           	0
+fHsimSeqUdpDbsByteArray            	0
+fHsimCoLocate                      	0
+fHsimSeqUdpEblkOpt                 	0
+fHsimSeqUdpEblkOptDiag             	0
+fHsimGateInputAndDbsOffsetsOpt     	1
+fHsimUdpDynElab                    	0
+fHsimCompressData                  	4
+fHsimIgnoreZForDfuse               	1
+fHsimIgnoreDifferentCaps           	0
+fHandleGlitchQC                    	1
+fGlitchDetectForAllRtlLoads        	0
+fHsimFuseConstDriversOpt           	1
+fHsimIgnoreReElab                  	0
+fHsimFuseMultiDrivers              	0
+fHsimNoSched0Reg                   	0
+fHsimAmsFusionEnabled              	0
+fHsimRtlDbs                        	0
+fHsimWakeupId                      	0
+fHsimPassiveIbn                    	0
+fHsimBcOpt                         	1
+fHsimCertitude                     	0
+fHsimCertRapAutoTest               	0
+fHsimRaceDetect                    	0
+fCheckTcCond                       	0
+fHsimScanOptRelaxDbg               	0
+fHsimScanOptRelaxDbgDynamic        	0
+fHsimScanOptRelaxDbgDynamicPli     	0
+fHsimScanOptRelaxDbgDiag           	0
+fHsimScanOptRelaxDbgDiagHi         	0
+fHsimScanOptNoErrorOnPliAccess     	0
+fHsimScanOptTiming                 	0
+fRelaxIbnSchedCheck                	0
+fHsimScanOptNoDumpCombo            	0
+fHsimScanOptPrintSwitchState       	0
+fHsimScanOptSelectiveSwitchOn      	0
+fHsimScanOptSingleSEPliOpt         	1
+fHsimScanOptDesignHasDebugAccessOnly	0
+fHsimScanOptPrintPcode             	0
+fHsimScanDbgPerf                   	0
+fHsimNoStitchMap                   	0
+fHsimUnifiedModName                	0
+fHsimCbkMemOptDebug                	0
+fHsimMasterModuleOnly              	0
+fHsimMdbOptimizeSelects            	0
+fHsimMdbScalarizePorts             	0
+fHsimMdbOptimizeSelectsHeuristic   	1
+fHsimMdb1006Partition              	0
+fHsimVectorPgate                   	0
+fHsimNoHs                          	0
+fHsimXmrPartition                  	0
+fHsimNewPartition                  	0
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+fHsimNewPartTHold                  	0
+fHsimParitionCellInstNum           	1000
+fHsimParitionCellNodeNum           	1000
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+fHsimNewPartCutSingleInstLimit     	268435455
+fHsimElabModDistNum                	0
+fHsimNewPartAutoUpperLimit         	0
+fHsimPCPortPartition               	0
+fHsimPortPartition                 	0
+fHsimDumpMdb                       	0
+fHsimElabDiag                      	0
+fHsimSimpCollect                   	0
+fHsimPcodeDiag                     	0
+fHsimFastelab                      	0
+fHsimMacroOpt                      	0
+fHsimSkipOpt                       	0
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+fHsimSkipOptRootlimit              	0
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+fFusempchainsFanoutlimit           	0
+fFusempchainsDiagCount             	0
+fHsimCgVectorGates                 	0
+fHsimCgVectorGates1                	0
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+fHsimCgScalarGates                 	0
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+fHsimCgRtl                         	1
+fHsimCgRtlFilter                   	0
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+fHsimCgRtlSize                     	15
+fHsimNewCgRt                       	0
+fHsimNewCgMPRt                     	0
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+fHsimGlueOpt                       	0
+fHsimPGatePatchOpt                 	0
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+fHsimElabModCg                     	0
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+fScaleTimeValue                    	0
+fDebugTimeScale                    	0
+fPartCompSDF                       	0
+fHsimNbaGate                       	1
+fDumpSDFBasedMod                   	1
+fOptimisticNtcSolver               	0
+fHsimAllMtm                        	0
+fHsimAllMtmPat                     	0
+fHsimSdgOptEnable                  	0
+fHsimSVTypesRefPorts               	0
+fHsimGrpByGrpElabIncr              	0
+fHsimMarkRefereeInVcsElab          	0
+fHsimStreamOpFix                   	1
+fHsimInterface                     	0
+fHsimMxWrapOpt                     	0
+fHsimMxTopBdryOpt                  	0
+fHsimClasses                       	0
+fHsimAggressiveDce                 	0
+fHsimDceDebug                      	1
+fHsimDceDebugUseHeuristics         	1
+fHsimMdbNewDebugOpt                	0
+fHsimMdbNewDebugOptExitOnError     	1
+fHsimNewDebugOptMemDiag            	0
+hsGlobalVerboseLevel               	0
+fHsimMdbVectorConstProp            	1
+fHsimEnableSeqUdpWrite             	1
+fHsimDumpMDBOnlyForSeqUdp          	0
+fHsimInitRegRandom                 	0
+fHsimInitRegRandomVcs              	1
+fEnableNewFinalStrHash             	0
+fEnableNewAssert                   	1
+fRunDbgDmma                        	0
+fAssrtCtrlSigChk                   	1
+fCheckSigValidity                  	0
+fUniqPriToAstRewrite               	0
+fUniqPriToAstCtrl                  	0
+fAssertcontrolUniqPriNewImpl       	0
+fRTLoopDectEna                     	0
+fCmplLoopDectEna                   	0
+fHsimMopFlow                       	1
+fUCaseLabelCtrl                    	0
+fUniSolRtSvaEna                    	1
+fUniSolSvaEna                      	1
+fXpropRtCtrlCallerOnly             	0
+fHsimRaptorPart                    	0
+fHsimEnableDbsMemOpt               	1
+fHsimDebugDbsMemOpt                	0
+fHsimRenPart                       	0
+fHsimShortElabInsts                	0
+fHsimXmrAllWires                   	0
+fHsimXmrDiag                       	0
+fHsimXmrPort                       	0
+fHsimFalcon                        	1
+fHsimGenForProfile                 	0
+fCompressSDF                       	0
+fDlpSvtbExclElab                   	0
+fHsimGates1209                     	0
+fHsimCgRtlNoShareSmd               	0
+fHsimGenForErSum                   	0
+fVpdOpt                            	1
+fHsimMdbCell                       	0
+fHsimCellDebug                     	0
+fHsimNoPeekInMdbCell               	0
+igetOpcodeSmdPtrLayoutId           	-1
+igetFieldSmdPtr                    	-1
+fDebugDump                         	1
+fHsimOrigNodeNames                 	0
+fHsimCgVectors2VOnly               	0
+fHsimMdbDeltaGate                  	0
+fHsimMdbVecDeltaGate               	1
+fHsimVpdOptVfsDB                   	1
+fHsimMdbPruneVpdGates              	1
+fHsimPcPe                          	0
+fHsimVpdGateOnlyFlag               	1
+fHsimMxConnFrc                     	0
+fHsimNewForceCbkVec                	0
+fHsimNewForceCbkVecDiag            	0
+fHsimMdbReplaceVpdHighConn         	1
+fHsimVpdOptSVTypes                 	1
+fHsHasPeUpXmr                      	0
+fHsimCompactVpdFn                  	1
+fHsimPIP                           	0
+fHsimRTLoopDectOrgName             	0
+fHsimVpdOptPC                      	0
+fHsimFusePeXmrFo                   	0
+fHsimXmrSched                      	0
+fHsimNoMdg                         	0
+fHsimVectorGates                   	0
+fHsimRtlLite                       	0
+fHsimMdbcgLut                      	0
+fHsimMdbcgSelective                	0
+fHsimVcselabGates                  	0
+fHsimMdbcgLevelize                 	0
+fHsimParGateEvalMode               	0
+fHsimDFuseVectors                  	0
+fHsimDFuseZero                     	0
+fHsimDFuseOpt                      	1
+fHsimPruneOpt                      	0
+fHsimSeqUdpPruneWithConstInputs    	0
+fHsimSafeDFuse                     	0
+fHsimVpdOptExpVec                  	0
+fHsimVpdOptSelGate                 	1
+fHsimVpdOptSkipFuncPorts           	0
+fHsimVpdOptAlways                  	1
+fHsimVpdOptMdbCell                 	0
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+fHsimVpdOptPartitionGate           	1
+fHsimVpdOptXmr                     	1
+fHsimVpdHilRtl                     	0
+fHsimSWave                         	0
+fHsimNoSched0InCell                	1
+fHsimPartialMdb                    	0
+hsimPdbLargeOffsetThreshold        	1048576
+fHsimFlatCell                      	0
+fHsimFlatCellLimit                 	0
+fHsimRegBank                       	0
+fHsimHmetisMaxPartSize             	0
+fHsimHmetisGateWt                  	0
+fHsimHmetisUbFactor                	0
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+fHsimHmetisMinPart                 	0
+fHsim2stCell                       	0
+fHsim2stCellMinSize                	0
+fHsimMdbcgDebug                    	0
+fHsimMdbcgDebugLite                	0
+fHsimMdbcgDistrib                  	0
+fHsimMdbcgSepmem                   	1
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+fHsimMdbHilPrune                   	0
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+fHsCgOptUdp                        	1
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+fHsCgOptDiag                       	0
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+fHsCgOptNoZCheck                   	0
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+fHsCgOpt4StateInfra                	0
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+fHsCgOptXprop                      	0
+fHsimMdbcgDiag                     	0
+fHsCgMaxInputs                     	6
+fHsCgOptFwdPass                    	1
+fHsimHpnodes                       	0
+fLightDump                         	0
+fHDLCosim                          	0
+fHDLCosimDebug                     	0
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+fHDLCosimTimeCoupledPorts          	0
+HDLCosimMaxDataPerDpi              	1
+HDLCosimMaxCallsPerDpi             	2147483647
+fHDLCosimCompileDUT                	0
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+fHsCgOptMiSched0                   	0
+fgcAddSched0                       	0
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+fHsimCgScalarVerilogForce          	1
+fVcsElabToRoot                     	1
+fHilIbnObnCallByName               	0
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+fHsVecOneld                        	0
+fNativeVpdDebug                    	0
+fHsimVcsGenTLS                     	1
+fAssertSuccDebugLevelDump          	0
+fHsimMinputsChangeCheck            	0
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+fHsimRenumberAlias                 	0
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+fHilCgMode                         	115
+fHsimUnionOpt                      	0
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+fHsimCertRaptScal                  	0
+fHsimCertRaptMdbClock              	0
+fHsCgOptMux                        	0
+fHsCgOptFrc                        	0
+fHsCgOpt30                         	0
+fHsLpNoCapsOpt                     	0
+fHsCgOpt4State                     	1
+fSkipStrChangeOnDelay              	1
+fHsimTcheckOpt                     	0
+fHsCgOptMuxMClk                    	0
+fHsCgOptMuxFrc                     	0
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+fHsimDbsFlagsByteArray             	0
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+fFgpSched0UdpData                  	0
+fFgpDepositDiag                    	0
+fFgpEvtDiag.diagOn                 	0
+fFgpEvtDiag.printAllNodes          	0
+fFgpMangleDiagLog                  	0
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+fFgpIbnSchedThreshold              	0
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+fFgpMpStateByte                    	0
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+fHsimVirtIntfDynLoadSched          	0
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+fFgpReportUnsafeFuncs              	0
+fHsCgOptUncPrlThreshold            	4
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