v1.0
This commit is contained in:
Core_kingdom
85
rtl/async_fifo.v
Normal file
85
rtl/async_fifo.v
Normal file
@@ -0,0 +1,85 @@
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module async_fifo #(
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parameter DATA_WIDTH = 8,
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parameter FIFO_DEPTH = 16
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)(
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input wr_clk,
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input wr_rst_n,
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input wr_en,
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input [DATA_WIDTH-1:0] wr_data,
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output full,
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input rd_clk,
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input rd_rst_n,
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input rd_en,
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output [DATA_WIDTH-1:0] rd_data,
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output empty
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);
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reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
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reg [$clog2(FIFO_DEPTH) : 0] wr_ptr, rd_ptr;
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integer i;
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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wr_ptr <= 'd0;
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for(i=0;i<FIFO_DEPTH;i=i+1) begin
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mem[i] <= 'd0;
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end
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end else if(wr_en && !full) begin
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mem[wr_ptr[$clog2(FIFO_DEPTH)-1:0]] <= wr_data;
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wr_ptr <= wr_ptr + 1'b1;
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end else begin
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wr_ptr <= wr_ptr;
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end
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end
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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rd_ptr <= 'd0;
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end else if(rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'b1;
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end else begin
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rd_ptr <= rd_ptr;
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end
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end
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wire [$clog2(FIFO_DEPTH):0] wr_ptr_g , rd_ptr_g;
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assign wr_ptr_g = wr_ptr ^(wr_ptr >>1);
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assign rd_ptr_g = rd_ptr ^(rd_ptr >>1);
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reg [$clog2(FIFO_DEPTH):0] wr_ptr_gr , wr_ptr_grr;
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reg [$clog2(FIFO_DEPTH):0] rd_ptr_gr , rd_ptr_grr;
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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wr_ptr_gr <= 0;
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wr_ptr_grr <=0;
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end else begin
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wr_ptr_gr <= wr_ptr_g;
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wr_ptr_grr <= wr_ptr_gr;
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end
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end
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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rd_ptr_gr <= 0;
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rd_ptr_grr <=0;
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end else begin
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rd_ptr_gr <= rd_ptr_g;
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rd_ptr_grr <= rd_ptr_gr;
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end
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end
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assign rd_data = mem[rd_ptr[$clog2(FIFO_DEPTH)-1:0]];
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assign full = ((wr_ptr_g[$clog2(FIFO_DEPTH)] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]) && (wr_ptr_g[$clog2(FIFO_DEPTH)-1] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]-1) && (wr_ptr_g[$clog2(FIFO_DEPTH)-2:0] ==
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rd_ptr_grr[$clog2(FIFO_DEPTH)-2 : 0])) ? 1:0;
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assign empty = (rd_ptr_g[$clog2(FIFO_DEPTH) : 0] ==
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wr_ptr_grr[$clog2(FIFO_DEPTH) :0]) ? 1:0;
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endmodule
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214
rtl/rchannel.v
Normal file
214
rtl/rchannel.v
Normal file
@@ -0,0 +1,214 @@
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module rchannel (
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input clk,
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input rst_n,
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input axi_s_arvalid,
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input [7:0] axi_s_arlen,
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input [25:0] axi_s_araddr,
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output axi_s_arready,
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output axi_s_rvalid,
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output axi_s_rlast,
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output [63:0] axi_s_rdata,
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output rframe_valid,
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output [159:0] rframe_data,
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input rframe_ready,
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input array2axi_rdata_valid,
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input [127:0] array2axi_rdata
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);
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wire rsof,reof;
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reg [15:0] rraddr;
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reg [5:0] rcaddr;
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wire [127:0] wdata;
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wire [7:0] arlen;
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wire [15:0] arraddr;
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wire [5:0] arcaddr;
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reg [6:0] rframe_cnt;
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reg [7:0] rdata_cnt;
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reg [1:0] cur_state,next_state;
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localparam [1:0] RCH_IDLE = 2'b00;
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localparam [1:0] RCH_GET_RADDR = 2'b01;
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localparam [1:0] RCH_SD_RADDR = 2'b10;
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wire sync_fifo_ar_wr_en;
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wire sync_fifo_ar_rd_en;
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wire sync_fifo_ar_full;
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wire sync_fifo_ar_empty;
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wire [29:0] sync_fifo_ar_wr_data;
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wire [29:0] sync_fifo_ar_rd_data;
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sync_fifo #(.DATA_WIDTH(30),
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.FIFO_DEPTH(4)
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) sync_fifo_ar (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (sync_fifo_ar_wr_en),
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.wr_data (sync_fifo_ar_wr_data),
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.full (sync_fifo_ar_full),
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.rd_en (sync_fifo_ar_rd_en),
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.rd_data (sync_fifo_ar_rd_data),
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.empty (sync_fifo_ar_empty)
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);
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wire sync_fifo_arlen_wr_en;
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wire sync_fifo_arlen_rd_en;
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wire sync_fifo_arlen_full;
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wire sync_fifo_arlen_empty;
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wire [7:0] sync_fifo_arlen_wr_data;
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wire [7:0] sync_fifo_arlen_rd_data;
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sync_fifo #(.DATA_WIDTH(8),
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.FIFO_DEPTH(4)
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) sync_fifo_arlen (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (sync_fifo_arlen_wr_en),
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.wr_data (sync_fifo_arlen_wr_data),
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.full (sync_fifo_arlen_full),
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.rd_en (sync_fifo_arlen_rd_en),
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.rd_data (sync_fifo_arlen_rd_data),
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.empty (sync_fifo_arlen_empty)
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);
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wire sync_fifo_r_wr_en;
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wire sync_fifo_r_rd_en;
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wire sync_fifo_r_full;
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wire sync_fifo_r_empty;
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wire [127:0]sync_fifo_r_wr_data;
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wire [63:0] sync_fifo_r_rd_data;
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sync_fifo_128_to_64 #(.DATA_IN_WIDTH(128),
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.FIFO_DEPTH(8),
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.DATA_OUT_WIDTH(64)
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) sync_fifo_r (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (sync_fifo_r_wr_en),
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.wr_data (sync_fifo_r_wr_data),
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.full (sync_fifo_r_full),
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.rd_en (sync_fifo_r_rd_en),
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.rd_data (sync_fifo_r_rd_data),
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.empty (sync_fifo_r_empty)
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);
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assign axi_s_arready = !sync_fifo_ar_full;
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assign rframe_valid = (cur_state == RCH_SD_RADDR);
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assign rframe_data = {rsof,reof,rraddr,rcaddr,128'b0,arlen};
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assign axi_s_rvalid = !sync_fifo_r_empty;
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assign axi_s_rdata = sync_fifo_r_rd_data;
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assign axi_s_rlast = axi_s_rvalid && (rdata_cnt == sync_fifo_arlen_rd_data);
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assign sync_fifo_ar_wr_en = axi_s_arvalid && axi_s_arready;
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assign sync_fifo_ar_wr_data = {axi_s_araddr[25:4],axi_s_arlen};
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assign sync_fifo_ar_rd_en = rframe_ready && rframe_valid &&
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rframe_cnt == arlen>>1'b1 && !sync_fifo_ar_empty;
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assign {arraddr , arcaddr, arlen} = sync_fifo_ar_rd_data;
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assign sync_fifo_arlen_wr_en = rframe_valid && rframe_ready &&
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rframe_cnt == arlen >> 1'b1;
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assign sync_fifo_arlen_wr_data = arlen;
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assign sync_fifo_arlen_rd_en = axi_s_rlast && axi_s_rvalid;
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assign rsof = rframe_valid && (rframe_cnt == 7'b0 || rcaddr == 6'd0);
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assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1 || rcaddr == 6'h3f);
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assign sync_fifo_r_wr_en = array2axi_rdata_valid && !sync_fifo_r_full;
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assign sync_fifo_r_wr_data = array2axi_rdata;
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assign sync_fifo_r_rd_en = !sync_fifo_r_empty;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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cur_state <= RCH_IDLE;
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end else begin
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cur_state <= next_state;
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end
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end
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always@(*) begin
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case(cur_state)
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RCH_IDLE: begin
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if(sync_fifo_ar_wr_en) begin
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next_state <= RCH_GET_RADDR;
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end else begin
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next_state <= RCH_IDLE;
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end
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end
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RCH_GET_RADDR: begin
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next_state <= RCH_SD_RADDR;
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end
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RCH_SD_RADDR: begin
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if(rframe_ready && rframe_valid && rframe_cnt == arlen >>1) begin
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next_state <= RCH_IDLE;
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end else begin
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next_state <= RCH_SD_RADDR;
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end
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end
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endcase
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rraddr <= 'd0;
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end else if(cur_state == RCH_GET_RADDR) begin
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rraddr <= arraddr;
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if(rframe_valid && rframe_ready) begin
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if(rcaddr == 6'b111111) begin
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rraddr <= rraddr + 1'b1;
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end else begin
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rraddr <= rraddr;
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end
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end
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rcaddr <= 'd0;
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end else if (cur_state == RCH_GET_RADDR) begin
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rcaddr <= arcaddr;
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if(rframe_valid && rframe_ready) begin
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if(rcaddr == 6'b111111) begin
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rcaddr <= 'd0;
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end else begin
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rcaddr <= rcaddr + 1;
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end
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end
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rframe_cnt <= 'd0;
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end else if (rframe_valid && rframe_ready) begin
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if(rframe_cnt == arlen>>1'b1) begin
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rframe_cnt <= 'd0;
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end else begin
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rframe_cnt <= rframe_cnt + 1'b1;
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end
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rdata_cnt <= 'd0;
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end else if(axi_s_rvalid) begin
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if(rdata_cnt == sync_fifo_arlen_rd_data) begin
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rdata_cnt <= 'd0;
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end else begin
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rdata_cnt <= rdata_cnt + 1'b1;
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end
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end
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end
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endmodule
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76
rtl/sync_fifo.v
Normal file
76
rtl/sync_fifo.v
Normal file
@@ -0,0 +1,76 @@
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module sync_fifo #(
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parameter DATA_WIDTH = 8,
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parameter FIFO_DEPTH = 16
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)(
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input clk,
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input rst_n,
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input wr_en,
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input [DATA_WIDTH-1:0] wr_data,
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output full,
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input rd_en,
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output [DATA_WIDTH-1:0] rd_data,
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output empty
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);
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localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
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reg [DATA_WIDTH-1:0] mem [0 : FIFO_DEPTH -1];
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reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr ,rd_ptrr;
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wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
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assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
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assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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wr_ptr <= 'd0;
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end else if(wr_en && !full) begin
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wr_ptr <= wr_ptr + 1'b1;
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end else begin
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wr_ptr <= wr_ptr;
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rd_ptr <= 'd0;
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rd_ptrr <= 'd0;
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end else if(rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'b1;
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rd_ptrr <= rd_ptr;
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end else begin
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rd_ptr <= rd_ptr;
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rd_ptrr <= rd_ptr;
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end
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end
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integer i;
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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for(i=0;i<FIFO_DEPTH;i=i+1) begin
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mem[i] <= 'd0;
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end
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end else if(wr_en && !full) begin
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mem[wr_addr] <= wr_data;
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end else begin
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mem[wr_addr] <= mem[wr_addr];
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end
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end
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/*always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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r_rd_data <= 'd0;
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end else if(rd_en && !empty) begin
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r_rd_data <= mem[rd_addr];
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end else begin
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r_rd_data <= r_rd_data;
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end
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end*/
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assign rd_data = mem[rd_addr];
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assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH -1:0] == rd_ptr[ADDR_WIDTH -1:0])) ? 1:0;
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assign empty = (wr_ptr == rd_ptr) ? 1:0;
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endmodule
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62
rtl/sync_fifo_128_to_64.v
Normal file
62
rtl/sync_fifo_128_to_64.v
Normal file
@@ -0,0 +1,62 @@
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module sync_fifo_128_to_64 #(
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parameter DATA_IN_WIDTH = 128,
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parameter DATA_OUT_WIDTH = 64,
|
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parameter FIFO_DEPTH = 16,
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parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
|
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)(
|
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input clk,
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input rst_n,
|
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input wr_en,
|
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input [DATA_IN_WIDTH-1:0] wr_data,
|
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output full,
|
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input rd_en,
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output [DATA_OUT_WIDTH-1:0] rd_data,
|
||||
output empty
|
||||
);
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reg [DATA_OUT_WIDTH-1:0] mem [0 :FIFO_DEPTH -1];
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reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
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wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
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assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
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assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
|
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wr_ptr <= 'd0;
|
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end else if(wr_en && !full) begin
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wr_ptr <= wr_ptr + 2'd2;
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end else begin
|
||||
wr_ptr <= wr_ptr;
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||||
end
|
||||
end
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always@(posedge clk or negedge rst_n) begin
|
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if(!rst_n) begin
|
||||
rd_ptr <= 'd0;
|
||||
end else if(rd_en && !empty) begin
|
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rd_ptr <= rd_ptr + 1'd1;
|
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end else begin
|
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rd_ptr <= rd_ptr;
|
||||
end
|
||||
end
|
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|
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integer i;
|
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always@(posedge clk or negedge rst_n) begin
|
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if(!rst_n) begin
|
||||
for(i=0;i<FIFO_DEPTH;i=i+1) begin
|
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mem[i] <= 'd0;
|
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end
|
||||
end else if(wr_en && !full) begin
|
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{mem[wr_addr+1'b1],mem[wr_addr]} <= wr_data;
|
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end else begin
|
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mem[wr_addr] <= mem[wr_addr];
|
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end
|
||||
end
|
||||
|
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assign rd_data = mem[rd_addr];
|
||||
|
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assign full = (wr_ptr - rd_ptr == FIFO_DEPTH) ? 1:0;
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assign empty = (wr_ptr == rd_ptr) ? 1:0;
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|
||||
endmodule
|
||||
62
rtl/sync_fifo_64_to_128.v
Normal file
62
rtl/sync_fifo_64_to_128.v
Normal file
@@ -0,0 +1,62 @@
|
||||
module sync_fifo_64_to_128 #(
|
||||
parameter DATA_IN_WIDTH = 64,
|
||||
parameter DATA_OUT_WIDTH = 128,
|
||||
parameter FIFO_DEPTH = 16,
|
||||
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
|
||||
)(
|
||||
input clk,
|
||||
input rst_n,
|
||||
input wr_en,
|
||||
input [DATA_IN_WIDTH-1:0] wr_data,
|
||||
output full,
|
||||
input rd_en,
|
||||
output [DATA_OUT_WIDTH-1:0] rd_data,
|
||||
output empty
|
||||
);
|
||||
|
||||
reg [DATA_IN_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
|
||||
reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
|
||||
wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
|
||||
|
||||
assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
|
||||
assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
wr_ptr <= 'd0;
|
||||
end else if(wr_en && !full) begin
|
||||
wr_ptr <= wr_ptr + 1'b1;
|
||||
end else begin
|
||||
wr_ptr <= wr_ptr;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
rd_ptr <= 'd0;
|
||||
end else if(rd_en && !empty) begin
|
||||
rd_ptr <= rd_ptr + 2'd2;
|
||||
end else begin
|
||||
rd_ptr <= rd_ptr;
|
||||
end
|
||||
end
|
||||
|
||||
integer i;
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
for(i=0;i<FIFO_DEPTH;i=i+1) begin
|
||||
mem[i] <= 'd0;
|
||||
end
|
||||
end else if(wr_en && !full) begin
|
||||
mem[wr_addr] <= wr_data;
|
||||
end else begin
|
||||
mem[wr_addr] <= mem[wr_addr];
|
||||
end
|
||||
end
|
||||
|
||||
assign rd_data = {mem[rd_addr+1],mem[rd_addr]};
|
||||
|
||||
assign full = (wr_ptr - rd_ptr == FIFO_DEPTH) ? 1:0;
|
||||
assign empty = (wr_ptr - rd_ptr <=1) ? 1:0;
|
||||
|
||||
endmodule
|
||||
168
rtl/wchannel.v
Normal file
168
rtl/wchannel.v
Normal file
@@ -0,0 +1,168 @@
|
||||
module wchannel(
|
||||
input clk,
|
||||
input rst_n,
|
||||
|
||||
input axi_s_awvalid,
|
||||
input [7:0] axi_s_awlen,
|
||||
input [25:0] axi_s_awaddr,
|
||||
output axi_s_awready,
|
||||
|
||||
input axi_s_wvalid,
|
||||
input axi_s_wlast,
|
||||
input [63:0] axi_s_wdata,
|
||||
output axi_s_wready,
|
||||
|
||||
output wframe_valid,
|
||||
output [159:0] wframe_data,
|
||||
input wframe_ready
|
||||
);
|
||||
wire wsof,weof;
|
||||
reg [15:0] wraddr;
|
||||
reg [5:0] wcaddr;
|
||||
wire [127:0] wdata;
|
||||
|
||||
wire [7:0] awlen;
|
||||
wire [15:0] awraddr;
|
||||
wire [5:0] awcaddr;
|
||||
|
||||
reg [6:0] wframe_cnt;
|
||||
|
||||
reg [1:0] cur_state,next_state;
|
||||
localparam [1:0] WCH_IDLE = 2'b01;
|
||||
localparam [1:0] WCH_SD_WADDR = 2'b10;
|
||||
localparam [1:0] WCH_SD_WDATA = 2'b11;
|
||||
|
||||
wire sync_fifo_aw_wr_en;
|
||||
wire [29:0] sync_fifo_aw_wr_data;
|
||||
wire sync_fifo_aw_rd_en;
|
||||
wire [29:0] sync_fifo_aw_rd_data;
|
||||
wire sync_fifo_aw_full;
|
||||
wire sync_fifo_aw_empty;
|
||||
|
||||
wire sync_fifo_w_wr_en;
|
||||
wire [63:0] sync_fifo_w_wr_data;
|
||||
wire sync_fifo_w_rd_en;
|
||||
wire [127:0] sync_fifo_w_rd_data;
|
||||
wire sync_fifo_w_full;
|
||||
wire sync_fifo_w_empty;
|
||||
|
||||
assign sync_fifo_aw_wr_en = axi_s_awvalid && axi_s_awready;
|
||||
assign sync_fifo_aw_wr_data = {axi_s_awaddr[25:4],axi_s_awlen};
|
||||
assign sync_fifo_aw_rd_en = wframe_ready && weof && !sync_fifo_aw_empty;
|
||||
assign {awraddr,awcaddr,awlen} = sync_fifo_aw_rd_data;
|
||||
assign axi_s_awready = !sync_fifo_aw_full;
|
||||
|
||||
|
||||
|
||||
assign sync_fifo_w_wr_en = axi_s_wvalid && axi_s_wready;
|
||||
assign sync_fifo_w_wr_data = axi_s_wdata;
|
||||
assign sync_fifo_w_rd_en = wframe_valid && wframe_ready;
|
||||
assign wdata = sync_fifo_w_rd_data;
|
||||
assign axi_s_wready = !sync_fifo_w_full;
|
||||
|
||||
assign wsof = wframe_valid && (wframe_cnt == 7'd0);
|
||||
assign weof = wframe_valid && ((wframe_cnt == awlen >> 1'b1));
|
||||
|
||||
assign wframe_data = {wsof,weof,wraddr,wcaddr,wdata,awlen};
|
||||
assign wframe_valid = !sync_fifo_w_empty && (cur_state == WCH_SD_WDATA);
|
||||
|
||||
sync_fifo #(.DATA_WIDTH(30),
|
||||
.FIFO_DEPTH(4)
|
||||
) sync_fifo_aw (.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.wr_en (sync_fifo_aw_wr_en),
|
||||
.wr_data (sync_fifo_aw_wr_data),
|
||||
.rd_en (sync_fifo_aw_rd_en),
|
||||
.rd_data (sync_fifo_aw_rd_data),
|
||||
.full (sync_fifo_aw_full),
|
||||
.empty (sync_fifo_aw_empty)
|
||||
);
|
||||
|
||||
sync_fifo_64_to_128 #(
|
||||
.DATA_IN_WIDTH(64),
|
||||
.DATA_OUT_WIDTH(128),
|
||||
.FIFO_DEPTH(8)
|
||||
) sync_fifo_w (.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.wr_en (sync_fifo_w_wr_en),
|
||||
.wr_data (sync_fifo_w_wr_data),
|
||||
.rd_en (sync_fifo_w_rd_en),
|
||||
.rd_data (sync_fifo_w_rd_data),
|
||||
.full (sync_fifo_w_full),
|
||||
.empty (sync_fifo_w_empty)
|
||||
);
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
wframe_cnt <= 'd0;
|
||||
end else if (sync_fifo_w_rd_en) begin
|
||||
if (wframe_cnt == (awlen >> 1'b1)) begin
|
||||
wframe_cnt <= 'd0;
|
||||
end else begin
|
||||
wframe_cnt <= wframe_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
cur_state <= WCH_IDLE;
|
||||
end else begin
|
||||
cur_state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
always@(*) begin
|
||||
case(cur_state)
|
||||
WCH_IDLE: begin
|
||||
if(sync_fifo_aw_wr_en) begin
|
||||
next_state <= WCH_SD_WADDR;
|
||||
end else begin
|
||||
next_state <= WCH_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
WCH_SD_WADDR: begin
|
||||
next_state <= WCH_SD_WDATA;
|
||||
end
|
||||
|
||||
WCH_SD_WDATA: begin
|
||||
if(sync_fifo_w_rd_en && (wframe_cnt == (awlen >> 1))) begin
|
||||
next_state <= WCH_IDLE;
|
||||
end else begin
|
||||
next_state <= WCH_SD_WDATA;
|
||||
end
|
||||
end
|
||||
|
||||
default : begin
|
||||
next_state <= WCH_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
wcaddr <= 'd0;
|
||||
end else if (cur_state == WCH_SD_WADDR) begin
|
||||
wcaddr <= awcaddr;
|
||||
end else if (sync_fifo_w_rd_en) begin
|
||||
if (wcaddr == 6'h3f) begin
|
||||
wcaddr <= 'd0;
|
||||
end else begin
|
||||
wcaddr <= wcaddr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
wraddr <= 'd0;
|
||||
end else if (cur_state == WCH_SD_WADDR) begin
|
||||
if (sync_fifo_w_rd_en && (wcaddr == 6'h3f)) begin
|
||||
wraddr <= wraddr + 1'b1;
|
||||
end else begin
|
||||
wraddr <= wraddr;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
BIN
sim/.vcs_checkpoint_shared_memory.ICer.37503
Normal file
BIN
sim/.vcs_checkpoint_shared_memory.ICer.37503
Normal file
Binary file not shown.
20
sim/Makefile
Executable file
20
sim/Makefile
Executable file
@@ -0,0 +1,20 @@
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
comp : clean vcs
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
find :
|
||||
find ../{rtl,tb} -name "*.v" > filelist.f
|
||||
#---------------------------------------------------------------------------------------
|
||||
vcs :
|
||||
vcs \
|
||||
-f filelist.f \
|
||||
-timescale=1ns/1ps \
|
||||
-debug -o simv\
|
||||
-full64 -R +vc +v2k -sverilog -debug_access+all\
|
||||
| tee vcs.log
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
verdi :
|
||||
verdi -f filelist.f -ssf tb.fsdb &
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
clean :
|
||||
rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
116
sim/csrc/Makefile
Normal file
116
sim/csrc/Makefile
Normal file
@@ -0,0 +1,116 @@
|
||||
# Makefile generated by VCS to build your model
|
||||
# This file may be modified; VCS will not overwrite it unless -Mupdate is used
|
||||
|
||||
# define default verilog source directory
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Choose name of executable
|
||||
PRODUCTBASE=$(VSRC)/simv
|
||||
|
||||
PRODUCT=$(PRODUCTBASE)
|
||||
|
||||
# Product timestamp file. If product is newer than this one,
|
||||
# we will also re-link the product.
|
||||
PRODUCT_TIMESTAMP=product_timestamp
|
||||
|
||||
# Path to runtime library
|
||||
DEPLIBS=
|
||||
VCSUCLI=-lvcsucli
|
||||
RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o $(DEPLIBS)
|
||||
|
||||
VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
|
||||
# Strip Flags for target product
|
||||
STRIPFLAGS=
|
||||
|
||||
PRE_LDFLAGS= # Loader Flags
|
||||
LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib
|
||||
# Picarchive Flags
|
||||
PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir
|
||||
|
||||
# C run time startup
|
||||
CRT0=
|
||||
# C run time startup
|
||||
CRTN=
|
||||
# Machine specific libraries
|
||||
SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
|
||||
CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O0 -fno-strict-aliasing
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing
|
||||
|
||||
LD_PARTIAL_LOADER=ld
|
||||
# Partial linking
|
||||
LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
|
||||
ASFLAGS=
|
||||
LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs
|
||||
# Note: if make gives you errors about include, either get gmake, or
|
||||
# replace the following line with the contents of the file filelist,
|
||||
# EACH TIME IT CHANGES
|
||||
# included file defines OBJS, and is automatically generated by vcs
|
||||
include filelist
|
||||
|
||||
OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS)
|
||||
|
||||
product : $(PRODUCT_TIMESTAMP)
|
||||
@echo $(PRODUCT) up to date
|
||||
|
||||
objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)
|
||||
|
||||
clean :
|
||||
rm -f $(VCS_OBJS) $(CU_OBJS)
|
||||
|
||||
clobber : clean
|
||||
rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP)
|
||||
|
||||
picclean :
|
||||
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
||||
@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
|
||||
|
||||
product_clean_order :
|
||||
@$(MAKE) -f Makefile --no-print-directory picclean
|
||||
@$(MAKE) -f Makefile --no-print-directory product_order
|
||||
|
||||
product_order : $(PRODUCT)
|
||||
|
||||
$(PRODUCT_TIMESTAMP) : product_clean_order
|
||||
-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
|
||||
$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
|
||||
@rm -f csrc[0-9]*.o
|
||||
@touch $(PRODUCT_TIMESTAMP)
|
||||
@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
|
||||
|
||||
$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsnew.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsimprofile.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libuclinative.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ)
|
||||
@touch $(PRODUCT)
|
||||
|
||||
47
sim/csrc/Makefile.hsopt
Normal file
47
sim/csrc/Makefile.hsopt
Normal file
@@ -0,0 +1,47 @@
|
||||
# Makefile generated by VCS to build rmapats.so for your model
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
# Loader Flags
|
||||
LDFLAGS=
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing
|
||||
|
||||
ASFLAGS=
|
||||
LIBS=
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
|
||||
rmapats.so: $(HSOPT_OBJS)
|
||||
@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)
|
||||
BIN
sim/csrc/SIM_l.o
Normal file
BIN
sim/csrc/SIM_l.o
Normal file
Binary file not shown.
1
sim/csrc/_10313_archive_1.so
Symbolic link
1
sim/csrc/_10313_archive_1.so
Symbolic link
@@ -0,0 +1 @@
|
||||
.//../simv.daidir//_10313_archive_1.so
|
||||
1
sim/csrc/_12247_archive_1.so
Symbolic link
1
sim/csrc/_12247_archive_1.so
Symbolic link
@@ -0,0 +1 @@
|
||||
.//../simv.daidir//_12247_archive_1.so
|
||||
1
sim/csrc/_csrc0.so
Symbolic link
1
sim/csrc/_csrc0.so
Symbolic link
@@ -0,0 +1 @@
|
||||
.//../simv.daidir//_csrc0.so
|
||||
1
sim/csrc/_prev_archive_1.so
Symbolic link
1
sim/csrc/_prev_archive_1.so
Symbolic link
@@ -0,0 +1 @@
|
||||
.//../simv.daidir//_prev_archive_1.so
|
||||
350
sim/csrc/_prev_cginfo.json
Normal file
350
sim/csrc/_prev_cginfo.json
Normal file
@@ -0,0 +1,350 @@
|
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"MlibObjs": {},
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"NameTable": {
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"...MASTER...": [
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"SIM",
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"amcQw",
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"module",
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3
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"module",
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1
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"tb_rchannel": [
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"tb_rchannel",
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"TJvMf",
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"module",
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"stat": {
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"realTime": 0.45762920379638672,
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"Frontend(%)": 66.396885468195578,
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"CurCompileUdps": {},
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"SIMBData": {
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"out": "amcQwB.o",
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"bytes": 117946,
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||||
"text": 0,
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||||
"archive": "archive.0/_10313_archive_1.a"
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||||
},
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||||
"incremental": "on",
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"CurCompileModules": [
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||||
"...MASTER...",
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||||
"...MASTER...",
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||||
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||||
"std",
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||||
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||||
"tb_rchannel"
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],
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"PEModules": [],
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"CompileProcesses": [
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||||
"cgproc.10313.json"
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||||
],
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"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"csrc": "csrc",
|
||||
"master_pid": 10313,
|
||||
"default_output_dir": "csrc",
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"hostname": "IC_EDA",
|
||||
"cwd": "/home/ICer/ic_prjs/mc/sim",
|
||||
"daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"archive_dir": "archive.0"
|
||||
},
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||||
"rlimit": {
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||||
"data": -1,
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||||
"stack": -1
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||||
},
|
||||
"CompileStatus": "Successful"
|
||||
}
|
||||
964
sim/csrc/_vcs_pli_stub_.c
Normal file
964
sim/csrc/_vcs_pli_stub_.c
Normal file
@@ -0,0 +1,964 @@
|
||||
#ifndef _GNU_SOURCE
|
||||
#define _GNU_SOURCE
|
||||
#endif
|
||||
#include <stdio.h>
|
||||
#include <dlfcn.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern void* VCS_dlsymLookup(const char *);
|
||||
extern void vcsMsgReportNoSource1(const char *, const char*);
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
extern void novas_call_fsdbDumpvars(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvars
|
||||
void novas_call_fsdbDumpvars(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:misc */
|
||||
#ifndef __VCS_PLI_STUB_novas_misc
|
||||
#define __VCS_PLI_STUB_novas_misc
|
||||
extern void novas_misc(int data, int reason, int iparam );
|
||||
#pragma weak novas_misc
|
||||
void novas_misc(int data, int reason, int iparam )
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason, iparam );
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
|
||||
#endif /* __VCS_PLI_STUB_novas_misc */
|
||||
|
||||
/* PLI routine: $fsdbDumpvarsByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvarsByFile
|
||||
void novas_call_fsdbDumpvarsByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
|
||||
|
||||
/* PLI routine: $fsdbAddRuntimeSignal:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
|
||||
#pragma weak novas_call_fsdbAddRuntimeSignal
|
||||
void novas_call_fsdbAddRuntimeSignal(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
|
||||
|
||||
/* PLI routine: $sps_create_transaction_stream:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
extern void novas_call_sps_create_transaction_stream(int data, int reason);
|
||||
#pragma weak novas_call_sps_create_transaction_stream
|
||||
void novas_call_sps_create_transaction_stream(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
|
||||
|
||||
/* PLI routine: $sps_begin_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
extern void novas_call_sps_begin_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_begin_transaction
|
||||
void novas_call_sps_begin_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
|
||||
|
||||
/* PLI routine: $sps_end_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
extern void novas_call_sps_end_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_end_transaction
|
||||
void novas_call_sps_end_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
|
||||
|
||||
/* PLI routine: $sps_free_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
extern void novas_call_sps_free_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_free_transaction
|
||||
void novas_call_sps_free_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
|
||||
|
||||
/* PLI routine: $sps_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
extern void novas_call_sps_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_attribute
|
||||
void novas_call_sps_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
|
||||
|
||||
/* PLI routine: $sps_update_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
#define __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
extern void novas_call_sps_update_label(int data, int reason);
|
||||
#pragma weak novas_call_sps_update_label
|
||||
void novas_call_sps_update_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
|
||||
|
||||
/* PLI routine: $sps_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
extern void novas_call_sps_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_relation
|
||||
void novas_call_sps_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbWhatif:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
extern void novas_call_fsdbWhatif(int data, int reason);
|
||||
#pragma weak novas_call_fsdbWhatif
|
||||
void novas_call_fsdbWhatif(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
|
||||
|
||||
/* PLI routine: $paa_init:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_init
|
||||
#define __VCS_PLI_STUB_novas_call_paa_init
|
||||
extern void novas_call_paa_init(int data, int reason);
|
||||
#pragma weak novas_call_paa_init
|
||||
void novas_call_paa_init(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_init */
|
||||
|
||||
/* PLI routine: $paa_sync:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_sync
|
||||
#define __VCS_PLI_STUB_novas_call_paa_sync
|
||||
extern void novas_call_paa_sync(int data, int reason);
|
||||
#pragma weak novas_call_paa_sync
|
||||
void novas_call_paa_sync(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
extern void novas_call_fsdbDumpClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassMethod
|
||||
void novas_call_fsdbDumpClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassMethod
|
||||
void novas_call_fsdbSuppressClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassProp:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
extern void novas_call_fsdbSuppressClassProp(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassProp
|
||||
void novas_call_fsdbSuppressClassProp(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
|
||||
|
||||
/* PLI routine: $fsdbDumpMDAByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpMDAByFile
|
||||
void novas_call_fsdbDumpMDAByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_begin
|
||||
void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_define_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_stream_attribute
|
||||
void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_end
|
||||
void novas_call_fsdbEvent_create_stream_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
extern void novas_call_fsdbEvent_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_begin
|
||||
void novas_call_fsdbEvent_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_set_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
extern void novas_call_fsdbEvent_set_label(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_set_label
|
||||
void novas_call_fsdbEvent_set_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_attribute
|
||||
void novas_call_fsdbEvent_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_tag:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
extern void novas_call_fsdbEvent_add_tag(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_tag
|
||||
void novas_call_fsdbEvent_add_tag(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
|
||||
|
||||
/* PLI routine: $fsdbTrans_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
extern void novas_call_fsdbEvent_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_end
|
||||
void novas_call_fsdbEvent_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
extern void novas_call_fsdbEvent_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_relation
|
||||
void novas_call_fsdbEvent_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbTrans_get_error_code:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_get_error_code
|
||||
void novas_call_fsdbEvent_get_error_code(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_stream_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_stream_attribute
|
||||
void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_scope_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_scope_attribute
|
||||
void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
|
||||
|
||||
/* PLI routine: $sps_interactive:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
#define __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
extern void novas_call_sps_interactive(int data, int reason);
|
||||
#pragma weak novas_call_sps_interactive
|
||||
void novas_call_sps_interactive(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
|
||||
|
||||
/* PLI routine: $sps_test:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_test
|
||||
#define __VCS_PLI_STUB_novas_call_sps_test
|
||||
extern void novas_call_sps_test(int data, int reason);
|
||||
#pragma weak novas_call_sps_test
|
||||
void novas_call_sps_test(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_test */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObject:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
extern void novas_call_fsdbDumpClassObject(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObject
|
||||
void novas_call_fsdbDumpClassObject(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObjectByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObjectByFile
|
||||
void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
|
||||
|
||||
/* PLI routine: $ridbDump:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_ridbDump
|
||||
#define __VCS_PLI_STUB_novas_call_ridbDump
|
||||
extern void novas_call_ridbDump(int data, int reason);
|
||||
#pragma weak novas_call_ridbDump
|
||||
void novas_call_ridbDump(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
|
||||
|
||||
/* PLI routine: $sps_flush_file:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
#define __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
extern void novas_call_sps_flush_file(int data, int reason);
|
||||
#pragma weak novas_call_sps_flush_file
|
||||
void novas_call_sps_flush_file(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
|
||||
|
||||
/* PLI routine: $fsdbDumpSingle:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
extern void novas_call_fsdbDumpSingle(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpSingle
|
||||
void novas_call_fsdbDumpSingle(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
|
||||
|
||||
/* PLI routine: $fsdbDumpIO:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
extern void novas_call_fsdbDumpIO(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpIO
|
||||
void novas_call_fsdbDumpIO(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
BIN
sim/csrc/_vcs_pli_stub_.o
Normal file
BIN
sim/csrc/_vcs_pli_stub_.o
Normal file
Binary file not shown.
BIN
sim/csrc/archive.1/_12247_archive_1.a
Normal file
BIN
sim/csrc/archive.1/_12247_archive_1.a
Normal file
Binary file not shown.
1
sim/csrc/archive.1/_12247_archive_1.a.info
Normal file
1
sim/csrc/archive.1/_12247_archive_1.a.info
Normal file
@@ -0,0 +1 @@
|
||||
amcQwB.o
|
||||
BIN
sim/csrc/archive.1/_prev_archive_1.a
Normal file
BIN
sim/csrc/archive.1/_prev_archive_1.a
Normal file
Binary file not shown.
2
sim/csrc/archive.1/_prev_archive_1.a.info
Normal file
2
sim/csrc/archive.1/_prev_archive_1.a.info
Normal file
@@ -0,0 +1,2 @@
|
||||
reYIK_d.o
|
||||
TJvMf_d.o
|
||||
BIN
sim/csrc/cgincr.sdb
Normal file
BIN
sim/csrc/cgincr.sdb
Normal file
Binary file not shown.
377
sim/csrc/cginfo.json
Normal file
377
sim/csrc/cginfo.json
Normal file
@@ -0,0 +1,377 @@
|
||||
{
|
||||
"MlibObjs": {},
|
||||
"cycles_program_begin": 3307152958815,
|
||||
"CompileStrategy": "fullobj",
|
||||
"perf": [
|
||||
{
|
||||
"stat": [
|
||||
"main",
|
||||
"entry",
|
||||
0.026144981384277344,
|
||||
0.043098999999999998,
|
||||
0.048230000000000002,
|
||||
211404,
|
||||
211404,
|
||||
0.0,
|
||||
0.0,
|
||||
1754402057.363112,
|
||||
3307153106779
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"entry",
|
||||
0.042268037796020508,
|
||||
0.049146000000000002,
|
||||
0.053419000000000001,
|
||||
267312,
|
||||
268112,
|
||||
0.0,
|
||||
0.0,
|
||||
1754402057.379235,
|
||||
3307182112175
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"exit",
|
||||
0.050005912780761719,
|
||||
0.056211999999999998,
|
||||
0.054091,
|
||||
268348,
|
||||
268996,
|
||||
0.0,
|
||||
0.0,
|
||||
1754402057.3869729,
|
||||
3307196068791
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"entry",
|
||||
0.052634000778198242,
|
||||
0.058027000000000002,
|
||||
0.054862000000000001,
|
||||
268348,
|
||||
268996,
|
||||
0.0,
|
||||
0.0,
|
||||
1754402057.389601,
|
||||
3307200944808
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"entry",
|
||||
0.061315059661865234,
|
||||
0.065280000000000005,
|
||||
0.056263000000000001,
|
||||
273568,
|
||||
273572,
|
||||
0.0,
|
||||
0.0,
|
||||
1754402057.3982821,
|
||||
3307216457851
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"exit",
|
||||
0.14647507667541504,
|
||||
0.086853,
|
||||
0.077547000000000005,
|
||||
283588,
|
||||
283608,
|
||||
0.012430999999999999,
|
||||
0.013950000000000001,
|
||||
1754402057.4834421,
|
||||
3307369718733
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"entry",
|
||||
0.14656496047973633,
|
||||
0.086901000000000006,
|
||||
0.077590000000000006,
|
||||
283588,
|
||||
283608,
|
||||
0.012430999999999999,
|
||||
0.013950000000000001,
|
||||
1754402057.483532,
|
||||
3307369821873
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"exit",
|
||||
0.15060806274414062,
|
||||
0.089954000000000006,
|
||||
0.078579999999999997,
|
||||
283588,
|
||||
283608,
|
||||
0.012430999999999999,
|
||||
0.013950000000000001,
|
||||
1754402057.4875751,
|
||||
3307377128743
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"exit",
|
||||
0.15065693855285645,
|
||||
0.089980000000000004,
|
||||
0.078603999999999993,
|
||||
283588,
|
||||
283608,
|
||||
0.012430999999999999,
|
||||
0.013950000000000001,
|
||||
1754402057.4876239,
|
||||
3307377178846
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"entry",
|
||||
0.15068292617797852,
|
||||
0.089994000000000005,
|
||||
0.078615000000000004,
|
||||
283588,
|
||||
283608,
|
||||
0.012430999999999999,
|
||||
0.013950000000000001,
|
||||
1754402057.4876499,
|
||||
3307377221306
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"entry",
|
||||
0.19117498397827148,
|
||||
0.090045,
|
||||
0.080729999999999996,
|
||||
282164,
|
||||
283608,
|
||||
0.033097000000000001,
|
||||
0.028851000000000002,
|
||||
1754402057.528142,
|
||||
3307450157519
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"exit",
|
||||
0.23283195495605469,
|
||||
0.122961,
|
||||
0.084728999999999999,
|
||||
282188,
|
||||
283608,
|
||||
0.033097000000000001,
|
||||
0.032874,
|
||||
1754402057.5697989,
|
||||
3307525185634
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"exit",
|
||||
0.2377159595489502,
|
||||
0.12631200000000001,
|
||||
0.086262000000000005,
|
||||
284128,
|
||||
284132,
|
||||
0.033097000000000001,
|
||||
0.032874,
|
||||
1754402057.574683,
|
||||
3307533964801
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"main",
|
||||
"exit",
|
||||
0.23819112777709961,
|
||||
0.126583,
|
||||
0.086446999999999996,
|
||||
284120,
|
||||
284132,
|
||||
0.033097000000000001,
|
||||
0.032874,
|
||||
1754402057.5751581,
|
||||
3307534766369
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
],
|
||||
"CurCompileUdps": {},
|
||||
"CompileProcesses": [
|
||||
"cgproc.12247.json"
|
||||
],
|
||||
"CurCompileModules": [
|
||||
"...MASTER...",
|
||||
"std",
|
||||
"tb_rchannel"
|
||||
],
|
||||
"PrevCompiledModules": {
|
||||
"std": {
|
||||
"reYIK_d": {
|
||||
"bytes": 43078,
|
||||
"mod": "std",
|
||||
"out": "reYIK_d.o",
|
||||
"mode": 4,
|
||||
"checksum": 0,
|
||||
"archive": "archive.1/_prev_archive_1.a"
|
||||
}
|
||||
},
|
||||
"tb_rchannel": {
|
||||
"TJvMf_d": {
|
||||
"bytes": 94788,
|
||||
"mod": "tb_rchannel",
|
||||
"out": "TJvMf_d.o",
|
||||
"mode": 4,
|
||||
"checksum": 0,
|
||||
"archive": "archive.1/_prev_archive_1.a"
|
||||
}
|
||||
},
|
||||
"...MASTER...": {
|
||||
"amcQw_d": {
|
||||
"bytes": 7904,
|
||||
"mod": "...MASTER...",
|
||||
"out": "objs/amcQw_d.o",
|
||||
"mode": 4,
|
||||
"checksum": 0
|
||||
}
|
||||
}
|
||||
},
|
||||
"NameTable": {
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"tb_rchannel": [
|
||||
"tb_rchannel",
|
||||
"TJvMf",
|
||||
"module",
|
||||
2
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
3
|
||||
]
|
||||
},
|
||||
"SIMBData": {
|
||||
"out": "amcQwB.o",
|
||||
"bytes": 117070,
|
||||
"archive": "archive.1/_12247_archive_1.a",
|
||||
"text": 0
|
||||
},
|
||||
"cpu_cycles_pass2_start": 3307450168560,
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
],
|
||||
"stat": {
|
||||
"ru_self_cgstart": {
|
||||
"ru_maxrss_kb": 80808,
|
||||
"ru_utime_sec": 0.090082999999999996,
|
||||
"ru_stime_sec": 0.080764000000000002,
|
||||
"ru_minflt": 25946,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 27,
|
||||
"ru_nivcsw": 9
|
||||
},
|
||||
"ru_self_end": {
|
||||
"ru_maxrss_kb": 90168,
|
||||
"ru_utime_sec": 0.126638,
|
||||
"ru_stime_sec": 0.086485000000000006,
|
||||
"ru_minflt": 29557,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 29,
|
||||
"ru_nivcsw": 9
|
||||
},
|
||||
"ru_childs_cgstart": {
|
||||
"ru_maxrss_kb": 29296,
|
||||
"ru_utime_sec": 0.033097000000000001,
|
||||
"ru_stime_sec": 0.028851000000000002,
|
||||
"ru_minflt": 10148,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 26,
|
||||
"ru_nivcsw": 22
|
||||
},
|
||||
"cpu_cycles_total": 381884822,
|
||||
"cpu_cycles_cgstart": 3307450206879,
|
||||
"nMops": 7107,
|
||||
"Frontend(%)": 77.115222086580886,
|
||||
"ru_childs_end": {
|
||||
"ru_maxrss_kb": 29668,
|
||||
"ru_utime_sec": 0.033097000000000001,
|
||||
"ru_stime_sec": 0.032874,
|
||||
"ru_minflt": 10742,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 27,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"cpu_cycles_end": 3307534843637,
|
||||
"nQuads": 2574,
|
||||
"totalObjSize": 117070,
|
||||
"mopSpeed": 194419.36807550257,
|
||||
"CodeGen(%)": 22.884777913419111,
|
||||
"quadSpeed": 70414.443988510422,
|
||||
"mop/quad": 2.7610722610722611,
|
||||
"outputSizePerQuad": 45.481740481740481,
|
||||
"peak_mem_kb": 284132,
|
||||
"realTime": 0.23830199241638184
|
||||
},
|
||||
"incremental": "on",
|
||||
"PEModules": [],
|
||||
"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"cwd": "/home/ICer/ic_prjs/mc/sim",
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"hostname": "IC_EDA",
|
||||
"master_pid": 12247,
|
||||
"csrc": "csrc",
|
||||
"daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"default_output_dir": "csrc",
|
||||
"archive_dir": "archive.1"
|
||||
},
|
||||
"rlimit": {
|
||||
"data": -1,
|
||||
"stack": -1
|
||||
},
|
||||
"CompileStatus": "Successful"
|
||||
}
|
||||
170
sim/csrc/cgproc.12247.json
Normal file
170
sim/csrc/cgproc.12247.json
Normal file
@@ -0,0 +1,170 @@
|
||||
{
|
||||
"Modules": {
|
||||
"...MASTER...": {
|
||||
"nRouts": 5,
|
||||
"start_perf": [
|
||||
0.19128203392028809,
|
||||
0.090102000000000002,
|
||||
0.080781000000000006,
|
||||
282164,
|
||||
283608,
|
||||
1754402057.528249,
|
||||
3307450306333
|
||||
],
|
||||
"child_modules": {
|
||||
"std": 1,
|
||||
"tb_rchannel": 1
|
||||
},
|
||||
"end_perf": [
|
||||
0.19858002662658691,
|
||||
0.091245999999999994,
|
||||
0.082950999999999997,
|
||||
282176,
|
||||
283608,
|
||||
3307463473880,
|
||||
0,
|
||||
0
|
||||
],
|
||||
"nQuads": 0,
|
||||
"nMops": 0
|
||||
},
|
||||
"std": {
|
||||
"start_perf": [
|
||||
0.19872212409973145,
|
||||
0.091245999999999994,
|
||||
0.083093,
|
||||
282176,
|
||||
283608,
|
||||
1754402057.5356891,
|
||||
3307463716318
|
||||
],
|
||||
"child_modules": {},
|
||||
"Compiled Times": 2,
|
||||
"nMops": 528,
|
||||
"Compiled": "Yes",
|
||||
"end_perf": [
|
||||
0.20293402671813965,
|
||||
0.094464000000000006,
|
||||
0.084083000000000005,
|
||||
282192,
|
||||
283608,
|
||||
3307471412441,
|
||||
8589934594,
|
||||
0
|
||||
],
|
||||
"svclass": [
|
||||
"$vcs_nba_dyn_obj",
|
||||
0,
|
||||
35,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"sigprop$$",
|
||||
0,
|
||||
35,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"process",
|
||||
0,
|
||||
200,
|
||||
8,
|
||||
8,
|
||||
0,
|
||||
"event",
|
||||
0,
|
||||
34,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"mailbox",
|
||||
0,
|
||||
140,
|
||||
9,
|
||||
9,
|
||||
0,
|
||||
"semaphore",
|
||||
0,
|
||||
84,
|
||||
5,
|
||||
5,
|
||||
0
|
||||
],
|
||||
"nQuads": 218,
|
||||
"nRouts": 33
|
||||
},
|
||||
"tb_rchannel": {
|
||||
"nRouts": 305,
|
||||
"start_perf": [
|
||||
0.20321393013000488,
|
||||
0.094746999999999998,
|
||||
0.084083000000000005,
|
||||
282192,
|
||||
283608,
|
||||
1754402057.5401809,
|
||||
3307471851392
|
||||
],
|
||||
"child_modules": {},
|
||||
"nMops": 6579,
|
||||
"Compiled Times": 2,
|
||||
"Compiled": "Yes",
|
||||
"end_perf": [
|
||||
0.22820496559143066,
|
||||
0.119739,
|
||||
0.084083000000000005,
|
||||
282192,
|
||||
283608,
|
||||
3307516798771,
|
||||
25769803777,
|
||||
0
|
||||
],
|
||||
"nQuads": 2356
|
||||
}
|
||||
},
|
||||
"CompUnits": {},
|
||||
"reusePaths": {
|
||||
"reYIK_d": {
|
||||
"icPath": "csrc"
|
||||
},
|
||||
"amcQw_d": {
|
||||
"icPath": "csrc"
|
||||
},
|
||||
"TJvMf_d": {
|
||||
"icPath": "csrc"
|
||||
}
|
||||
},
|
||||
"ObjArchives": [
|
||||
{
|
||||
"archive": "archive.1/_12247_archive_1.a",
|
||||
"objects": [
|
||||
[
|
||||
"amcQwB.o",
|
||||
117070
|
||||
]
|
||||
],
|
||||
"size": 117070
|
||||
}
|
||||
],
|
||||
"stat": {
|
||||
"ru_self_end": {
|
||||
"ru_maxrss_kb": 90168,
|
||||
"ru_utime_sec": 0.12639900000000001,
|
||||
"ru_stime_sec": 0.086320999999999995,
|
||||
"ru_minflt": 29552,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 29,
|
||||
"ru_nivcsw": 9
|
||||
},
|
||||
"cpu_cycles_end": 3307534115943,
|
||||
"ru_childs_end": {
|
||||
"ru_maxrss_kb": 29668,
|
||||
"ru_utime_sec": 0.033097000000000001,
|
||||
"ru_stime_sec": 0.032874,
|
||||
"ru_minflt": 10742,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 27,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"peak_mem_kb": 284132
|
||||
}
|
||||
}
|
||||
31
sim/csrc/filelist
Normal file
31
sim/csrc/filelist
Normal file
@@ -0,0 +1,31 @@
|
||||
|
||||
|
||||
AR=ar
|
||||
DOTLIBS=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
|
||||
# This file is automatically generated by VCS. Any changes you make to it
|
||||
# will be overwritten the next time VCS is run
|
||||
VCS_LIBEXT=
|
||||
XTRN_OBJS=
|
||||
|
||||
DPI_WRAPPER_OBJS =
|
||||
DPI_STUB_OBJS =
|
||||
# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
|
||||
include filelist.dpi
|
||||
PLI_STUB_OBJS =
|
||||
include filelist.pli
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
include filelist.cu
|
||||
|
||||
VCS_INCR_OBJS=
|
||||
|
||||
|
||||
AUGDIR=
|
||||
AUG_LDFLAGS=
|
||||
SHARED_OBJ_SO=
|
||||
|
||||
|
||||
|
||||
VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)
|
||||
50
sim/csrc/filelist.cu
Normal file
50
sim/csrc/filelist.cu
Normal file
@@ -0,0 +1,50 @@
|
||||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _12247_archive_1.so
|
||||
_12247_archive_1.so : archive.1/_12247_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_12247_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_12247_archive_1.so $@
|
||||
|
||||
|
||||
ARCHIVE_OBJS += _prev_archive_1.so
|
||||
_prev_archive_1.so : archive.1/_prev_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_prev_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
VCS_ARC0 =_csrc0.so
|
||||
|
||||
VCS_OBJS0 =objs/amcQw_d.o
|
||||
|
||||
|
||||
O0_OBJS =
|
||||
|
||||
$(O0_OBJS) : %.o: %.c
|
||||
$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
|
||||
|
||||
|
||||
%.o: %.c
|
||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
||||
|
||||
$(VCS_ARC0) : $(VCS_OBJS0)
|
||||
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
|
||||
rm -f $(VCS_ARC0)
|
||||
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
|
||||
|
||||
CU_UDP_OBJS = \
|
||||
|
||||
|
||||
CU_LVL_OBJS = \
|
||||
SIM_l.o
|
||||
|
||||
MAIN_OBJS = \
|
||||
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
0
sim/csrc/filelist.dpi
Normal file
0
sim/csrc/filelist.dpi
Normal file
13
sim/csrc/filelist.hsopt
Normal file
13
sim/csrc/filelist.hsopt
Normal file
@@ -0,0 +1,13 @@
|
||||
rmapats_mop.o: rmapats.m
|
||||
@/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
|
||||
|
||||
rmapats.o: rmapats.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
|
||||
rmapats%.o: rmapats%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
rmar.o: rmar.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
|
||||
rmar%.o: rmar%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
|
||||
include filelist.hsopt.objs
|
||||
1
sim/csrc/filelist.hsopt.llvm2_0.objs
Normal file
1
sim/csrc/filelist.hsopt.llvm2_0.objs
Normal file
@@ -0,0 +1 @@
|
||||
LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o
|
||||
7
sim/csrc/filelist.hsopt.objs
Normal file
7
sim/csrc/filelist.hsopt.objs
Normal file
@@ -0,0 +1,7 @@
|
||||
HSOPT_OBJS +=rmapats_mop.o \
|
||||
rmapats.o \
|
||||
rmar.o rmar_nd.o
|
||||
|
||||
include filelist.hsopt.llvm2_0.objs
|
||||
HSOPT_OBJS += $(LLVM_OBJS)
|
||||
|
||||
4
sim/csrc/filelist.pli
Normal file
4
sim/csrc/filelist.pli
Normal file
@@ -0,0 +1,4 @@
|
||||
PLI_STUB_OBJS += _vcs_pli_stub_.o
|
||||
_vcs_pli_stub_.o: _vcs_pli_stub_.c
|
||||
@$(CC) -I/home/synopsys/vcs-mx/O-2018.09-1/include -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
|
||||
@strip -g _vcs_pli_stub_.o
|
||||
BIN
sim/csrc/hsim/hsim.sdb
Normal file
BIN
sim/csrc/hsim/hsim.sdb
Normal file
Binary file not shown.
0
sim/csrc/import_dpic.h
Normal file
0
sim/csrc/import_dpic.h
Normal file
BIN
sim/csrc/objs/amcQw_d.o
Normal file
BIN
sim/csrc/objs/amcQw_d.o
Normal file
Binary file not shown.
BIN
sim/csrc/pre.cgincr.sdb
Normal file
BIN
sim/csrc/pre.cgincr.sdb
Normal file
Binary file not shown.
0
sim/csrc/product_timestamp
Normal file
0
sim/csrc/product_timestamp
Normal file
43
sim/csrc/rmapats.c
Normal file
43
sim/csrc/rmapats.c
Normal file
@@ -0,0 +1,43 @@
|
||||
// file = 0; split type = patterns; threshold = 100000; total count = 0.
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <strings.h>
|
||||
#include "rmapats.h"
|
||||
|
||||
void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685);
|
||||
void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685)
|
||||
{
|
||||
U I1546;
|
||||
U I1547;
|
||||
U I1548;
|
||||
struct futq * I1549;
|
||||
struct dummyq_struct * pQ = I1288;
|
||||
I1546 = ((U )vcs_clocks) + I685;
|
||||
I1548 = I1546 & ((1 << fHashTableSize) - 1);
|
||||
I1282->I727 = (EBLK *)(-1);
|
||||
I1282->I731 = I1546;
|
||||
if (I1546 < (U )vcs_clocks) {
|
||||
I1547 = ((U *)&vcs_clocks)[1];
|
||||
sched_millenium(pQ, I1282, I1547 + 1, I1546);
|
||||
}
|
||||
else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
|
||||
I1282->I733 = (struct eblk *)peblkFutQ1Tail;
|
||||
peblkFutQ1Tail->I727 = I1282;
|
||||
peblkFutQ1Tail = I1282;
|
||||
}
|
||||
else if ((I1549 = pQ->I1189[I1548].I745)) {
|
||||
I1282->I733 = (struct eblk *)I1549->I744;
|
||||
I1549->I744->I727 = (RP )I1282;
|
||||
I1549->I744 = (RmaEblk *)I1282;
|
||||
}
|
||||
else {
|
||||
sched_hsopt(pQ, I1282, I1546);
|
||||
}
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void SinitHsimPats(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
2453
sim/csrc/rmapats.h
Normal file
2453
sim/csrc/rmapats.h
Normal file
File diff suppressed because it is too large
Load Diff
0
sim/csrc/rmapats.m
Normal file
0
sim/csrc/rmapats.m
Normal file
BIN
sim/csrc/rmapats.o
Normal file
BIN
sim/csrc/rmapats.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmapats_mop.o
Normal file
BIN
sim/csrc/rmapats_mop.o
Normal file
Binary file not shown.
13
sim/csrc/rmar.c
Normal file
13
sim/csrc/rmar.c
Normal file
@@ -0,0 +1,13 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "rmar0.h"
|
||||
|
||||
// stubs for Hil functions
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void __Hil__Static_Init_Func__(void) {}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
18
sim/csrc/rmar.h
Normal file
18
sim/csrc/rmar.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef _RMAR1_H_
|
||||
#define _RMAR1_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __DO_RMAHDR_
|
||||
#include "rmar0.h"
|
||||
#endif /*__DO_RMAHDR_*/
|
||||
|
||||
extern UP rmaFunctionRtlArray[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
BIN
sim/csrc/rmar.o
Normal file
BIN
sim/csrc/rmar.o
Normal file
Binary file not shown.
13
sim/csrc/rmar0.h
Normal file
13
sim/csrc/rmar0.h
Normal file
@@ -0,0 +1,13 @@
|
||||
#ifndef _RMAR0_H_
|
||||
#define _RMAR0_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
BIN
sim/csrc/rmar_llvm_0_0.o
Normal file
BIN
sim/csrc/rmar_llvm_0_0.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmar_llvm_0_1.o
Normal file
BIN
sim/csrc/rmar_llvm_0_1.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmar_nd.o
Normal file
BIN
sim/csrc/rmar_nd.o
Normal file
Binary file not shown.
12
sim/filelist.f
Normal file
12
sim/filelist.f
Normal file
@@ -0,0 +1,12 @@
|
||||
../rtl/sync_fifo_128_to_64.v
|
||||
#../rtl/sync_fifo_64_to_128.v
|
||||
#../rtl/async_fifo.v
|
||||
#../rtl/wchannel.v
|
||||
../rtl/sync_fifo.v
|
||||
../rtl/rchannel.v
|
||||
#../tb/tb_sync_fifo_128_to_64.v
|
||||
#../tb/tb_async_fifo.v
|
||||
#../tb/tb_sync_fifo_64_to_128.v
|
||||
#../tb/tb_sync_fifo.v
|
||||
#../tb/tb_wchannel.v
|
||||
../tb/tb_rchannel.v
|
||||
BIN
sim/inter.fsdb
Normal file
BIN
sim/inter.fsdb
Normal file
Binary file not shown.
943
sim/novas.conf
Normal file
943
sim/novas.conf
Normal file
File diff suppressed because one or more lines are too long
1359
sim/novas.rc
Normal file
1359
sim/novas.rc
Normal file
File diff suppressed because it is too large
Load Diff
790
sim/novas_dump.log
Normal file
790
sim/novas_dump.log
Normal file
@@ -0,0 +1,790 @@
|
||||
#######################################################################################
|
||||
# log primitive debug message of FSDB dumping #
|
||||
# This is for R&D to analyze when there are issues happening when FSDB dump #
|
||||
#######################################################################################
|
||||
ANF: vcsd_get_serial_mode_status('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
VCS compile option:
|
||||
option[0]: /home/ICer/ic_prjs/mc/sim/simv
|
||||
option[1]: -sml=verdi
|
||||
option[2]: +fsdb+gate=off
|
||||
option[3]: -ucli2Proc
|
||||
option[4]: -ucli
|
||||
option[5]: -l
|
||||
option[6]: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
option[7]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
option[8]: -Mcc=gcc
|
||||
option[9]: -Mcplusplus=g++
|
||||
option[10]: -Masflags=
|
||||
option[11]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[12]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[13]: -Mldflags= -rdynamic
|
||||
option[14]: -Mout=simv
|
||||
option[15]: -Mamsrun=
|
||||
option[16]: -Mvcsaceobjs=
|
||||
option[17]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
option[18]: -Mexternalobj=
|
||||
option[19]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
option[20]: -Mcrt0=
|
||||
option[21]: -Mcrtn=
|
||||
option[22]: -Mcsrc=
|
||||
option[23]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[24]: -Xvcs_run_simv=1
|
||||
option[25]: -timescale=1ns/1ps
|
||||
option[26]: -Xcbug=0x1
|
||||
option[27]: -o
|
||||
option[28]: simv
|
||||
option[29]: -full64
|
||||
option[30]: +vc
|
||||
option[31]: +v2k
|
||||
option[32]: -debug_access+all
|
||||
option[33]: +vpi
|
||||
option[34]: +vcsd1
|
||||
option[35]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[36]: -picarchive
|
||||
option[37]: +cli+4
|
||||
option[38]: -debug=3
|
||||
option[39]: +memcbk
|
||||
option[40]: -P
|
||||
option[41]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[42]: -fsdb
|
||||
option[43]: -sverilog
|
||||
option[44]: +vpi
|
||||
option[45]: -gen_obj
|
||||
option[46]: -f
|
||||
option[47]: filelist.f
|
||||
option[48]: -load
|
||||
option[49]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[50]: timescale=1ns/1ps
|
||||
Chronologic Simulation VCS Release O-2018.09-1_Full64
|
||||
Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
|
||||
CPU cores: 8
|
||||
Limit information:
|
||||
======================================
|
||||
cputime unlimited
|
||||
filesize unlimited
|
||||
datasize unlimited
|
||||
stacksize unlimited
|
||||
coredumpsize 0 kbytes
|
||||
memoryuse unlimited
|
||||
vmemoryuse unlimited
|
||||
descriptors 4096
|
||||
memorylocked 64 kbytes
|
||||
maxproc 4096
|
||||
======================================
|
||||
(Special)Runtime environment variables:
|
||||
|
||||
Runtime environment variables:
|
||||
XDG_VTNR=1
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
SSH_AGENT_PID=3332
|
||||
XDG_SESSION_ID=1
|
||||
HOSTNAME=IC_EDA
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
NOVAS_SYNC_MOTIF_DISP=
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
SHELL=/bin/bash
|
||||
VTE_VERSION=5204
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
TERM=xterm-256color
|
||||
MAKEFLAGS=
|
||||
HISTSIZE=1000
|
||||
SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
LC_ALL=C
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
IMSETTINGS_MODULE=none
|
||||
USER=ICer
|
||||
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
|
||||
LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
GNOME_TERMINAL_SERVICE=:1.106
|
||||
XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SNPSLMD_LICENSE_FILE=27000@IC_EDA
|
||||
USERNAME=ICer
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3198,unix/unix:/tmp/.ICE-unix/3198
|
||||
MAKELEVEL=1
|
||||
MFLAGS=
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
PATH=/bin:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
|
||||
MAIL=/var/spool/mail/ICer
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
QT_IM_MODULE=ibus
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
XDG_SESSION_TYPE=x11
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
PWD=/home/ICer/ic_prjs/mc/sim
|
||||
XMODIFIERS=@im=none
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SYS_PROG_NAME=verdi
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
LANG=C
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
KDEDIRS=/usr
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
CDSHOME=/home/cadence/IC617
|
||||
SYS_INST_DIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
GDMSESSION=gnome-classic
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
HISTCONTROL=ignoredups
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
HOME=/home/ICer
|
||||
XDG_SEAT=seat0
|
||||
RISCV=/home/Riscv_Tools
|
||||
SHLVL=3
|
||||
MGC_HOME=/home/mentor/
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
VERDI_ORIGNAL_LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
MGC_LICENSE_FILE=/home/mentor//license/license.dat
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
CADHOME=/home/cadence
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
LOGNAME=ICer
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc
|
||||
SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
WINDOWPATH=1
|
||||
LD_NOVERSION=1
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
DISPLAY=:0
|
||||
QT_PLUGIN_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/plugins
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JizYR8/database
|
||||
COLORTERM=truecolor
|
||||
PS_HWPC=OFF
|
||||
NOVAS_LC_ALL=C
|
||||
NOVAS_SIGNAL_BASE_EXTRACTION=1
|
||||
SIGNAL_BASE_EXTRACTION=1
|
||||
NOVAS_VERDI_SVTB_BETA=1
|
||||
VERDI_SVTB_BETA=1
|
||||
NOVAS_VERDI_SVTB_ALPHA=1
|
||||
VERDI_SVTB_ALPHA=1
|
||||
NOVAS_VERDI_TB_HT=1
|
||||
VERDI_TB_HT=1
|
||||
NOVAS_WAVE_REDRAW_ALLVC=1
|
||||
WAVE_REDRAW_ALLVC=1
|
||||
NOVAS_TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
|
||||
TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
|
||||
XKEYSYMDB=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/XKeysymDB2.1
|
||||
XLOCALEDIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/locale
|
||||
NOVAS_SIGNAL_BASED_BA=0
|
||||
SIGNAL_BASED_BA=0
|
||||
SYNOPSYS_SIM=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DISABLE_LIBRARY_MAP_CHECK=1
|
||||
SNPS_SIM_DEFAULT_GUI=verdi
|
||||
FSDB_FILE=/home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
VCS_UCLI_STDIN_BLOCKING=1
|
||||
FSDB_VHDL_PROTECTED=1
|
||||
FSDB_RD_IR_ENABLE=1
|
||||
FSDB_SVA_STATUS=1
|
||||
VCS_HEAP_EXEC=true
|
||||
VCS_PATHMAP_PRELOAD_DONE=1
|
||||
VCS_STACK_EXEC=true
|
||||
VCS_EXEC_DONE=1
|
||||
VCS_STOP_SAFE=1
|
||||
DVE_SIM_SELECT_LOOP=on
|
||||
Runtime command line arguments:
|
||||
argv[0]=/home/ICer/ic_prjs/mc/sim/simv
|
||||
argv[1]=-sml=verdi
|
||||
argv[2]=+fsdb+gate=off
|
||||
argv[3]=-ucli2Proc
|
||||
argv[4]=-ucli
|
||||
argv[5]=-l
|
||||
argv[6]=/home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
326 profile - 100
|
||||
CPU/Mem usage: 0.000 sys, 0.050 user, 236.30M mem
|
||||
327 Tue Aug 5 21:54:29 2025
|
||||
328 pliAppInit
|
||||
329 ndpGetenv(FSDB_FILE): /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
330 ndpGetenv(FSDB_SVA_STATUS): 1
|
||||
331 ndpGetenv(FSDB_VHDL_PROTECTED): 1
|
||||
332 FSDB_GATE & FSDB_RTL is disabled.
|
||||
333 Enable Parallel Dumping.
|
||||
334 pliAppMiscSet: New Sim Round
|
||||
335 pliEntryInit
|
||||
336 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
337 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
338 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
339 sps_tcl_fsdbDumpfile_main at 0
|
||||
340 argv[0]: /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
341 *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
|
||||
342 compile option from '/home/ICer/ic_prjs/mc/sim/simv.daidir/vcs_rebuild'.
|
||||
343 "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
344 sps_tcl_fsdbDumpflush_vd_main
|
||||
345 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
346 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
347 sps_tcl_fsdbDumpvars_vd_main
|
||||
348 argv[0]: 0
|
||||
349 argv[1]: tb_rchannel.array2axi_rdata
|
||||
350 argv[2]: +all
|
||||
351 argv[3]: +trace_process
|
||||
352 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
353 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
354 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
|
||||
355 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 329.37M mem
|
||||
incr: 0.000 sys, 0.000 user, 2.20M mem
|
||||
accu: 0.000 sys, 0.000 user, 2.20M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 2.20M mem
|
||||
|
||||
Count usage: 1 var, 1 idcode, 1 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
356 Tue Aug 5 21:54:30 2025
|
||||
357 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.26M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 1 var, 1 idcode, 1 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
358 Tue Aug 5 21:54:30 2025
|
||||
359 sps_tcl_fsdbDumpvars_vd_main
|
||||
360 argv[0]: 0
|
||||
361 argv[1]: tb_rchannel.array2axi_rdata_valid
|
||||
362 argv[2]: +all
|
||||
363 argv[3]: +trace_process
|
||||
364 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
|
||||
365 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 2 var, 2 idcode, 2 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
366 Tue Aug 5 21:54:30 2025
|
||||
367 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 2 var, 2 idcode, 2 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
368 Tue Aug 5 21:54:30 2025
|
||||
369 sps_tcl_fsdbDumpvars_vd_main
|
||||
370 argv[0]: 0
|
||||
371 argv[1]: tb_rchannel.axi_s_araddr
|
||||
372 argv[2]: +all
|
||||
373 argv[3]: +trace_process
|
||||
374 *Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
|
||||
375 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 3 var, 3 idcode, 3 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
376 Tue Aug 5 21:54:30 2025
|
||||
377 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 3 var, 3 idcode, 3 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
378 Tue Aug 5 21:54:30 2025
|
||||
379 sps_tcl_fsdbDumpvars_vd_main
|
||||
380 argv[0]: 0
|
||||
381 argv[1]: tb_rchannel.axi_s_arlen
|
||||
382 argv[2]: +all
|
||||
383 argv[3]: +trace_process
|
||||
384 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
|
||||
385 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 4 var, 4 idcode, 4 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
386 Tue Aug 5 21:54:30 2025
|
||||
387 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 4 var, 4 idcode, 4 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
388 Tue Aug 5 21:54:30 2025
|
||||
389 sps_tcl_fsdbDumpvars_vd_main
|
||||
390 argv[0]: 0
|
||||
391 argv[1]: tb_rchannel.axi_s_arready
|
||||
392 argv[2]: +all
|
||||
393 argv[3]: +trace_process
|
||||
394 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
|
||||
395 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 5 var, 5 idcode, 5 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
396 Tue Aug 5 21:54:30 2025
|
||||
397 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 5 var, 5 idcode, 5 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
398 Tue Aug 5 21:54:30 2025
|
||||
399 sps_tcl_fsdbDumpvars_vd_main
|
||||
400 argv[0]: 0
|
||||
401 argv[1]: tb_rchannel.axi_s_arvalid
|
||||
402 argv[2]: +all
|
||||
403 argv[3]: +trace_process
|
||||
404 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
|
||||
405 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 6 var, 6 idcode, 6 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
406 Tue Aug 5 21:54:30 2025
|
||||
407 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 6 var, 6 idcode, 6 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
408 Tue Aug 5 21:54:30 2025
|
||||
409 sps_tcl_fsdbDumpvars_vd_main
|
||||
410 argv[0]: 0
|
||||
411 argv[1]: tb_rchannel.axi_s_rdata
|
||||
412 argv[2]: +all
|
||||
413 argv[3]: +trace_process
|
||||
414 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
|
||||
415 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.010 user, 0.00M mem
|
||||
|
||||
Count usage: 7 var, 7 idcode, 7 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
416 Tue Aug 5 21:54:30 2025
|
||||
417 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 7 var, 7 idcode, 7 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
418 Tue Aug 5 21:54:30 2025
|
||||
419 sps_tcl_fsdbDumpvars_vd_main
|
||||
420 argv[0]: 0
|
||||
421 argv[1]: tb_rchannel.axi_s_rlast
|
||||
422 argv[2]: +all
|
||||
423 argv[3]: +trace_process
|
||||
424 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
|
||||
425 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 8 var, 8 idcode, 8 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
426 Tue Aug 5 21:54:30 2025
|
||||
427 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 8 var, 8 idcode, 8 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
428 Tue Aug 5 21:54:30 2025
|
||||
429 sps_tcl_fsdbDumpvars_vd_main
|
||||
430 argv[0]: 0
|
||||
431 argv[1]: tb_rchannel.axi_s_rvalid
|
||||
432 argv[2]: +all
|
||||
433 argv[3]: +trace_process
|
||||
434 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
|
||||
435 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 9 var, 9 idcode, 9 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
436 Tue Aug 5 21:54:30 2025
|
||||
437 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 9 var, 9 idcode, 9 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
438 Tue Aug 5 21:54:30 2025
|
||||
439 sps_tcl_fsdbDumpvars_vd_main
|
||||
440 argv[0]: 0
|
||||
441 argv[1]: tb_rchannel.clk
|
||||
442 argv[2]: +all
|
||||
443 argv[3]: +trace_process
|
||||
444 *Verdi* : Dumping the signal (tb_rchannel.clk).
|
||||
445 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 10 var, 10 idcode, 10 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
446 Tue Aug 5 21:54:30 2025
|
||||
447 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 10 var, 10 idcode, 10 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
448 Tue Aug 5 21:54:30 2025
|
||||
449 sps_tcl_fsdbDumpvars_vd_main
|
||||
450 argv[0]: 0
|
||||
451 argv[1]: tb_rchannel.rframe_data
|
||||
452 argv[2]: +all
|
||||
453 argv[3]: +trace_process
|
||||
454 *Verdi* : Dumping the signal (tb_rchannel.rframe_data).
|
||||
455 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 11 var, 11 idcode, 11 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
456 Tue Aug 5 21:54:30 2025
|
||||
457 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 11 var, 11 idcode, 11 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
458 Tue Aug 5 21:54:30 2025
|
||||
459 sps_tcl_fsdbDumpvars_vd_main
|
||||
460 argv[0]: 0
|
||||
461 argv[1]: tb_rchannel.rframe_ready
|
||||
462 argv[2]: +all
|
||||
463 argv[3]: +trace_process
|
||||
464 *Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
|
||||
465 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 12 var, 12 idcode, 12 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
466 Tue Aug 5 21:54:30 2025
|
||||
467 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 12 var, 12 idcode, 12 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
468 Tue Aug 5 21:54:30 2025
|
||||
469 sps_tcl_fsdbDumpvars_vd_main
|
||||
470 argv[0]: 0
|
||||
471 argv[1]: tb_rchannel.rframe_valid
|
||||
472 argv[2]: +all
|
||||
473 argv[3]: +trace_process
|
||||
474 *Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
|
||||
475 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 13 var, 13 idcode, 13 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
476 Tue Aug 5 21:54:30 2025
|
||||
477 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 13 var, 13 idcode, 13 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
478 Tue Aug 5 21:54:30 2025
|
||||
479 sps_tcl_fsdbDumpvars_vd_main
|
||||
480 argv[0]: 0
|
||||
481 argv[1]: tb_rchannel.rst_n
|
||||
482 argv[2]: +all
|
||||
483 argv[3]: +trace_process
|
||||
484 *Verdi* : Dumping the signal (tb_rchannel.rst_n).
|
||||
485 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 14 var, 14 idcode, 14 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
486 Tue Aug 5 21:54:30 2025
|
||||
487 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 14 var, 14 idcode, 14 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
488 Tue Aug 5 21:54:30 2025
|
||||
489 sps_tcl_fsdbDumpflush_vd_main
|
||||
490 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
491 sps_tcl_fsdbDumpflush_vd_main
|
||||
492 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
493 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_rchannel.v(98)
|
||||
494 argv[0]: (tb.fsdb)
|
||||
495 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_rchannel.v(99)
|
||||
496 argv[0]: (0)
|
||||
497 argv[1]: (handle) tb_rchannel
|
||||
498 argv[2]: (+all)
|
||||
499 *Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
500 *Verdi* : Enable +all dumping.
|
||||
501 *Verdi* : End of traversing.
|
||||
502 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.070 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.06M mem
|
||||
|
||||
Count usage: 129 var, 85 idcode, 72 callback
|
||||
incr: 115 var, 71 idcode, 58 callback
|
||||
accu: 115 var, 71 idcode, 58 callback
|
||||
accu incr: 115 var, 71 idcode, 58 callback
|
||||
503 Tue Aug 5 21:54:32 2025
|
||||
504 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.070 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 129 var, 85 idcode, 72 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 115 var, 71 idcode, 58 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
505 Tue Aug 5 21:54:32 2025
|
||||
506 sps_tcl_fsdbDumpflush_vd_main
|
||||
507 *Verdi* : Flush all FSDB Files at 365,000 ps.
|
||||
508 End of simulation at 365000
|
||||
509 Tue Aug 5 22:01:50 2025
|
||||
510 Begin FSDB profile info:
|
||||
511 FSDB Writer : bc1(186) bcn(270) mtf/stf(0/4)
|
||||
FSDB Writer elapsed time : flush(0.010457) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
512 End FSDB profile info
|
||||
513 Parallel profile - Flush:22 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
|
||||
514 ProduceTime:0.212615372 ConsumerTime:0.000000000 Buffer:64MB
|
||||
515 SimExit
|
||||
516 Sim process exit
|
||||
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.normal_done
Normal file
0
sim/simv.daidir/.normal_done
Normal file
148
sim/simv.daidir/.vcs.timestamp
Normal file
148
sim/simv.daidir/.vcs.timestamp
Normal file
@@ -0,0 +1,148 @@
|
||||
0
|
||||
39
|
||||
+cli+4
|
||||
+itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
+memcbk
|
||||
+v2k
|
||||
+vc
|
||||
+vcsd1
|
||||
+vpi
|
||||
+vpi
|
||||
-Mamsrun=
|
||||
-Masflags=
|
||||
-Mcc=gcc
|
||||
-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
-Mcplusplus=g++
|
||||
-Mcrt0=
|
||||
-Mcrtn=
|
||||
-Mcsrc=
|
||||
-Mexternalobj=
|
||||
-Mldflags= -rdynamic
|
||||
-Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
-Mout=simv
|
||||
-Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
-Mvcsaceobjs=
|
||||
-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
-P
|
||||
-Xcbug=0x1
|
||||
-Xvcs_run_simv=1
|
||||
-debug=3
|
||||
-debug_access+all
|
||||
-f filelist.f
|
||||
-fsdb
|
||||
-full64
|
||||
-gen_obj
|
||||
-o simv
|
||||
-picarchive
|
||||
-sverilog
|
||||
-timescale=1ns/1ps
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
90
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/mc/sim
|
||||
XMODIFIERS=@im=ibus
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
XDG_VTNR=1
|
||||
XDG_SESSION_TYPE=x11
|
||||
XDG_SESSION_ID=1
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
XDG_SEAT=seat0
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JizYR8/database
|
||||
WINDOWPATH=1
|
||||
VTE_VERSION=5204
|
||||
VMR_MODE_FLAG=64
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
VCS_MX_HOME_INTERNAL=1
|
||||
VCS_MODE_FLAG=64
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
VCS_DEPTH=0
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
VCS_ARCH=linux64
|
||||
USERNAME=ICer
|
||||
UNAME=/bin/uname
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
SSH_AGENT_PID=3332
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3198,unix/unix:/tmp/.ICE-unix/3198
|
||||
SCRNAME=vcs
|
||||
SCRIPT_NAME=vcs
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
RISCV=/home/Riscv_Tools
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
QT_IM_MODULE=ibus
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
OVA_UUM=0
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
MGC_LICENSE_FILE=/home/mentor//license/license.dat
|
||||
MGC_HOME=/home/mentor/
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
MFLAGS=
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
MAKELEVEL=1
|
||||
MAKEFLAGS=
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
LC_ALL=C
|
||||
KDEDIRS=/usr
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
IMSETTINGS_MODULE=none
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
HISTCONTROL=ignoredups
|
||||
GNOME_TERMINAL_SERVICE=:1.106
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
GDMSESSION=gnome-classic
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
COLORTERM=truecolor
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
CDSHOME=/home/cadence/IC617
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
CADHOME=/home/cadence
|
||||
0
|
||||
7
|
||||
1754401710 ../tb/tb_rchannel.v
|
||||
1754402050 ../rtl/rchannel.v
|
||||
1754372349 ../rtl/sync_fifo.v
|
||||
1754381818 ../rtl/sync_fifo_128_to_64.v
|
||||
1754401741 filelist.f
|
||||
1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
4
|
||||
1539402341 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so
|
||||
1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
|
||||
1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
|
||||
1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
1754402058 simv.daidir
|
||||
-1 partitionlib
|
||||
BIN
sim/simv.daidir/_12247_archive_1.so
Executable file
BIN
sim/simv.daidir/_12247_archive_1.so
Executable file
Binary file not shown.
BIN
sim/simv.daidir/_csrc0.so
Executable file
BIN
sim/simv.daidir/_csrc0.so
Executable file
Binary file not shown.
BIN
sim/simv.daidir/_prev_archive_1.so
Executable file
BIN
sim/simv.daidir/_prev_archive_1.so
Executable file
Binary file not shown.
BIN
sim/simv.daidir/binmap.sdb
Normal file
BIN
sim/simv.daidir/binmap.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/build_db
Executable file
4
sim/simv.daidir/build_db
Executable file
@@ -0,0 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1
|
||||
11
sim/simv.daidir/cc/cc_bcode.db
Normal file
11
sim/simv.daidir/cc/cc_bcode.db
Normal file
@@ -0,0 +1,11 @@
|
||||
sid tb_rchannel
|
||||
bcid 0 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET
|
||||
bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU CALL_ARG_VAL,6,0 NOT AND AND RET
|
||||
bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND AND RET
|
||||
bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_EQU OR AND RET
|
||||
bcid 5 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,5,0 OPT_CONST,63 WIDTH,1 M_EQU OR AND RET
|
||||
bcid 6 6 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 XOR WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,1 M_EQU AND RET
|
||||
bcid 7 7 WIDTH,3 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
bcid 8 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 PAD SUBTRACT OPT_CONST,8 WIDTH,1 M_EQU RET
|
||||
bcid 9 9 WIDTH,4 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
@@ -0,0 +1,2 @@
|
||||
Dummy_file
|
||||
Missing line/file info
|
||||
20
sim/simv.daidir/cgname.json
Normal file
20
sim/simv.daidir/cgname.json
Normal file
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"tb_rchannel": [
|
||||
"tb_rchannel",
|
||||
"TJvMf",
|
||||
"module",
|
||||
2
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
3
|
||||
]
|
||||
}
|
||||
0
sim/simv.daidir/covg_defs
Normal file
0
sim/simv.daidir/covg_defs
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
@@ -0,0 +1,4 @@
|
||||
O-2018.09-1_Full64
|
||||
Build Date = Oct 12 2018 20:38:10
|
||||
RedHat
|
||||
Compile Location: /home/ICer/ic_prjs/mc/sim
|
||||
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
Binary file not shown.
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
@@ -0,0 +1,9 @@
|
||||
#!/bin/sh -h
|
||||
PYTHONHOME=/home/synopsys/vcs-mx/O-2018.09-1/etc/search/pyh
|
||||
export PYTHONHOME
|
||||
PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_h3ehMU.xml.gz" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh -h
|
||||
|
||||
FILE_PATH="/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch"
|
||||
lockfile="${FILE_PATH}"/lock
|
||||
|
||||
FSearch_lock_release() {
|
||||
echo "" > /dev/null
|
||||
}
|
||||
create_fsearch_db_ctrl() {
|
||||
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
|
||||
if [ -s "${FILE_PATH}"/fsearch.log ]; then
|
||||
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
|
||||
else
|
||||
cat "${FILE_PATH}"/fsearch.stat
|
||||
fi
|
||||
return
|
||||
fi
|
||||
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
|
||||
MY_PID=`echo $!`
|
||||
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
|
||||
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
|
||||
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
|
||||
return
|
||||
}
|
||||
|
||||
dir_name=`/bin/dirname "$0"`
|
||||
if [ "${dir_name}" = "." ]; then
|
||||
cd $dir_name
|
||||
dir_name=`/bin/pwd`
|
||||
fi
|
||||
if [ -d "$dir_name"/../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../..
|
||||
fi
|
||||
|
||||
if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
||||
trap FSearch_lock_release EXIT
|
||||
(
|
||||
flock 193
|
||||
create_fsearch_db_ctrl "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
exit 193
|
||||
) 193> "$lockfile"
|
||||
rstat=$?
|
||||
if [ "${rstat}"x != "193x" ]; then
|
||||
exit $rstat
|
||||
fi
|
||||
else
|
||||
"/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
elif [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_h3ehMU.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_h3ehMU.xml.gz
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
Binary file not shown.
4
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
4
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
@@ -0,0 +1,4 @@
|
||||
/home/ICer/ic_prjs/mc/rtl/rchannel.v
|
||||
/home/ICer/ic_prjs/mc/rtl/sync_fifo.v
|
||||
/home/ICer/ic_prjs/mc/rtl/sync_fifo_128_to_64.v
|
||||
/home/ICer/ic_prjs/mc/tb/tb_rchannel.v
|
||||
1
sim/simv.daidir/debug_dump/topmodules
Normal file
1
sim/simv.daidir/debug_dump/topmodules
Normal file
@@ -0,0 +1 @@
|
||||
~<7E>
|
||||
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/eblklvl.db
Normal file
BIN
sim/simv.daidir/eblklvl.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
Binary file not shown.
78
sim/simv.daidir/external_functions
Normal file
78
sim/simv.daidir/external_functions
Normal file
@@ -0,0 +1,78 @@
|
||||
pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC
|
||||
pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC
|
||||
pli $dumpportson DumpPortsOnCALL - DumpPortsMISC
|
||||
pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC
|
||||
pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC
|
||||
pli $simlearn simLearnCall simLearnCheck simLearnMisc
|
||||
pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC
|
||||
pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC
|
||||
pli $countdrivers CountDriversCALL - -
|
||||
pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC
|
||||
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcc.sdb
Normal file
BIN
sim/simv.daidir/pcc.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/prof.sdb
Normal file
BIN
sim/simv.daidir/prof.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.dat
Normal file
BIN
sim/simv.daidir/rmapats.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.so
Executable file
BIN
sim/simv.daidir/rmapats.so
Executable file
Binary file not shown.
1
sim/simv.daidir/saifNetInfo.db
Normal file
1
sim/simv.daidir/saifNetInfo.db
Normal file
@@ -0,0 +1 @@
|
||||
0
|
||||
16
sim/simv.daidir/simv.kdb
Normal file
16
sim/simv.daidir/simv.kdb
Normal file
@@ -0,0 +1,16 @@
|
||||
rc file Version 1.0
|
||||
|
||||
[Design]
|
||||
COMPILE_PATH=/home/ICer/ic_prjs/mc/sim
|
||||
SystemC=FALSE
|
||||
UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=tb_rchannel
|
||||
OPTION=-ssz -ssv -ssy
|
||||
ELAB_OPTION=-ssz -ssv -ssy
|
||||
|
||||
[Value]
|
||||
WREALX=ffff534e50535f58
|
||||
WREALZ=ffff534e50535f5a
|
||||
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/tt.sdb
Normal file
BIN
sim/simv.daidir/tt.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/vcs_rebuild
Executable file
4
sim/simv.daidir/vcs_rebuild
Executable file
@@ -0,0 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1
|
||||
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
@@ -0,0 +1,673 @@
|
||||
hsDirType 1
|
||||
fHsimDesignHasDebugNodes 61
|
||||
fNSParam 1024
|
||||
fLargeSizeSdfTest 0
|
||||
fHsimDelayGateMbme 0
|
||||
fNoMergeDelays 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimCertRaptMode 0
|
||||
fSharedMasterElab 0
|
||||
hsimLevelizeDone 1
|
||||
fHsimCompressDiag 1
|
||||
fHsimPowerOpt 0
|
||||
fLoopReportElab 0
|
||||
fHsimRtl 0
|
||||
fHsimCbkOptVec 1
|
||||
fHsimDynamicCcnHeur 1
|
||||
fHsimPvcs 0
|
||||
fHsimPvcsCcn 0
|
||||
fHsimOldLdr 0
|
||||
fHsimSingleDB 1
|
||||
uVfsGcLimit 50
|
||||
fHsimCompatSched 0
|
||||
fHsimCompatOrder 0
|
||||
fHsimTransUsingdoMpd32 0
|
||||
fHsimDynamicElabForGates 1
|
||||
fHsimDynamicElabForVectors 0
|
||||
fHsimDynamicElabForVectorsAlways 0
|
||||
fHsimDynamicElabForVectorsMinputs 0
|
||||
fHsimDeferForceSelTillReElab 0
|
||||
fHsimModByModElab 1
|
||||
fSvNettRealResType 0
|
||||
fHsimExprID 1
|
||||
fHsimSequdpon 0
|
||||
fHsimDatapinOpt 0
|
||||
fHsimExprPrune 0
|
||||
fHsimMimoGate 0
|
||||
fHsimNewChangeCheckFrankch 1
|
||||
fHsimNoSched0Front 0
|
||||
fHsimNoSched0FrontForMd 1
|
||||
fHsimScalReg 0
|
||||
fHsimNtbVl 0
|
||||
fHsimICTimeStamp 0
|
||||
fHsimICDiag 0
|
||||
fHsimNewCSDF 1
|
||||
vcselabIncrMode 2
|
||||
fHsimMPPackDelay 0
|
||||
fHsimMultDriver 0
|
||||
fHsimPart 0
|
||||
fHsimPrlComp 0
|
||||
fHsimPartTest 0
|
||||
fHsimTestChangeCheck 0
|
||||
fHsimTestFlatNodeOrder 0
|
||||
fHsimTestNState 0
|
||||
fHsimPartDebug 0
|
||||
fHsimPartFlags 0
|
||||
fHsimOdeSched0 0
|
||||
fHsimNewRootSig 1
|
||||
fHsimDisableRootSigModeOpt 0
|
||||
fHsimTestRootSigModeOpt 0
|
||||
fHsimIncrWriteOnce 0
|
||||
fHsimUnifInterfaceFlow 1
|
||||
fHsimUnifInterfaceFlowDiag 0
|
||||
fHsimUnifInterfaceFlowXmrDiag 0
|
||||
fHsimUnifInterfaceMultiDrvChk 1
|
||||
fHsimXVirForGenerateScope 0
|
||||
fHsimCongruencyIntTestI 0
|
||||
fHsimCongruencySVA 0
|
||||
fHsimCongruencySVADbg 0
|
||||
fHsimCongruencyLatchEdgeFix 0
|
||||
fHsimCongruencyFlopEdgeFix 0
|
||||
fHsimCongruencyXprop 0
|
||||
fHsimCongruencyXpropFix 0
|
||||
fHsimCongruencyXpropDbsEdge 0
|
||||
fHsimCongruencyResetRecoveryDbs 0
|
||||
fHsimCongruencyClockControlDiag 0
|
||||
fHsimCongruencySampleUpdate 0
|
||||
fHsimCongruencyFFDbsFix 0
|
||||
fHsimCongruency 0
|
||||
fHsimCongruencySlave 0
|
||||
fHsimCongruencyCombinedLoads 0
|
||||
fHsimCongruencyFGP 0
|
||||
fHsimDeraceClockDataUdp 0
|
||||
fHsimDeraceClockDataLERUpdate 0
|
||||
fHsimCongruencyPC 0
|
||||
fHsimCongruencyPCInl 0
|
||||
fHsimCongruencyPCDbg 0
|
||||
fHsimCongruencyPCNoReuse 0
|
||||
fHsimCongruencyDumpHier 0
|
||||
fHsimCongruencyResolution 0
|
||||
fHsimCongruencyEveBus 0
|
||||
fHsimHcExpr 0
|
||||
fHsCgOptModOpt 0
|
||||
fHsCgOptSlowProp 0
|
||||
fHsimCcnOpt 1
|
||||
fHsimCcnOpt2 1
|
||||
fHsimCcnOpt3 0
|
||||
fHsimSmdMap 0
|
||||
fHsimSmdDiag 0
|
||||
fHsimSmdSimProf 0
|
||||
fHsimSgdDiag 0
|
||||
fHsimRtDiagLite 0
|
||||
fHsimRtDiagLiteCevent 100
|
||||
fHsimRtDiag 0
|
||||
fHsimSkRtDiag 0
|
||||
fHsimDDBSRtdiag 0
|
||||
fHsimDbg 0
|
||||
fHsimCompWithGates 0
|
||||
fHsimMdbDebugOpt 0
|
||||
fHsimMdbDebugOptP1 0
|
||||
fHsimMdbDebugOptP2 0
|
||||
fHsimMdbPruneOpt 1
|
||||
fHsimMdbMemOpt 0
|
||||
hsimRandValue 0
|
||||
fHsimSimMemProfile 0
|
||||
fHsimSimTimeProfile 0
|
||||
fHsimElabMemProfile 0
|
||||
fHsimElabTimeProfile 0
|
||||
fHsimElabMemNodesProfile 0
|
||||
fHsimElabMemAllNodesProfile 0
|
||||
fHsimDisableVpdGatesProfile 0
|
||||
fHsimFileProfile 0
|
||||
fHsimCountProfile 0
|
||||
fHsimXmrDefault 1
|
||||
fHsimFuseWireAndReg 0
|
||||
fHsimFuseSelfDrvLogic 0
|
||||
fHsimFuseProcess 0
|
||||
fHsimAllXmrs 1
|
||||
fHsimMvsimDb 0
|
||||
fHsimTaskFuncXmrs 0
|
||||
fHsimTaskFuncXmrsDbg 0
|
||||
fHsimAllTaskFuncXmrs 0
|
||||
fHsimPageArray 16383
|
||||
fHsimPageControls 16383
|
||||
hsDfsNodePageElems 0
|
||||
hsNodePageElems 0
|
||||
hsFlatNodePageElems 0
|
||||
hsGateMapPageElems 0
|
||||
hsGateOffsetPageElems 0
|
||||
hsGateInputOffsetPageElems 0
|
||||
hsDbsOffsetPageElems 0
|
||||
hsMinPulseWidthPageElems 0
|
||||
hsNodeUpPatternPageElems 0
|
||||
hsNodeDownPatternPageElems 0
|
||||
hsNodeUpOffsetPageElems 0
|
||||
hsNodeEblkOffsetPageElems 0
|
||||
hsNodeDownOffsetPageElems 0
|
||||
hsNodeUpdateOffsetPageElems 0
|
||||
hsSdfOffsetPageElems 0
|
||||
fHsimPageAllLevelData 0
|
||||
fHsimAggrCg 0
|
||||
fHsimViWire 1
|
||||
fHsimPcCbOpt 1
|
||||
fHsimAmsTunneling 0
|
||||
fHsimAmsTunnelingDiag 0
|
||||
fHsimScUpwardXmrNoSplit 1
|
||||
fHsimOrigNdbViewOnly 0
|
||||
fHsimVcsInterface 1
|
||||
fHsimVcsInterfaceAlias 1
|
||||
fHsimSVTypesIntf 1
|
||||
fUnifiedAssertCtrlDiag 0
|
||||
fHsimEnable2StateScal 0
|
||||
fHsimDisable2StateScalIbn 0
|
||||
fHsimVcsInterfaceAliasDbg 0
|
||||
fHsimVcsInterfaceDbg 0
|
||||
fHsimVcsVirtIntfDbg 0
|
||||
fHsimVcsAllIntfVarMem 0
|
||||
fHsimCheckVIDynLoadOffsets 0
|
||||
fHsimModInline 1
|
||||
fHsimModInlineDbg 0
|
||||
fHsimPCDrvLoadDbg 0
|
||||
fHsimDrvChk 1
|
||||
fHsimRtlProcessingNeeded 0
|
||||
fHsimGrpByGrpElab 0
|
||||
fHsimGrpByGrpElabMaster 0
|
||||
fHsimNoParentSplitPC 0
|
||||
fHsimNusymMode 0
|
||||
fHsimOneIntfPart 0
|
||||
fHsimCompressInSingleDb 2
|
||||
fHsimCompressFlatDb 0
|
||||
fHsimNoTime0Sched 1
|
||||
fHsimMdbVectorizeInstances 0
|
||||
fHsimMdbSplitGates 0
|
||||
fHsimDeleteInstances 0
|
||||
fHsimUserDeleteInstances 0
|
||||
fHsimDeleteGdb 0
|
||||
fHsimDeleteInstancesMdb 0
|
||||
fHsimShortInstMap 0
|
||||
fHsimMdbVectorizationDump 0
|
||||
fHsimScanVectorize 0
|
||||
fHsimParallelScanVectorize 0
|
||||
noInstsInVectorization 0
|
||||
cHsimNonReplicatedInstances 0
|
||||
fHsimScanRaptor 0
|
||||
fHsimConfigFileCount 0
|
||||
fHsimVectorConstProp 0
|
||||
fHsimPromoteParam 0
|
||||
fHsimNoVecInRaptor 0
|
||||
fRaptorDumpVal 0
|
||||
fRaptorVecNodes 0
|
||||
fRaptorVecNodes2 0
|
||||
fRaptorNonVecNodes 0
|
||||
fRaptorBdrNodes 0
|
||||
fRaptorVecGates 0
|
||||
fRaptorNonVecGates 0
|
||||
fRaptorTotalNodesBeforeVect 0
|
||||
fRaptorTotalGatesBeforeVect 0
|
||||
fHsimCountRaptorBits 0
|
||||
fHsimNewEvcd 1
|
||||
fHsimNewEvcdMX 0
|
||||
fHsimNewEvcdVecRoot 1
|
||||
fHsimNewEvcdForce 1
|
||||
fHsimNewEvcdTest 0
|
||||
fHsimNewEvcdObnDrv 1
|
||||
fHsimNewEvcdW 1
|
||||
fHsimNewEvcdWTest 0
|
||||
fHsimEvcdDbgFlags 0
|
||||
fHsimDumpOffsetData 1
|
||||
fFlopGlitchDetect 0
|
||||
fHsimClkGlitch 0
|
||||
fHsimGlitchDumpOnce 0
|
||||
fHsimDynamicElab 1
|
||||
fHsimCgVectors2Debug 0
|
||||
fHsimOdeDynElab 0
|
||||
fHsimOdeDynElabDiag 0
|
||||
fHsimOdeSeqUdp 0
|
||||
fHsimOdeSeqUdpXEdge 0
|
||||
fHsimOdeSeqUdpDbg 0
|
||||
fHsimOdeRmvSched0 0
|
||||
fHsimAllLevelSame 0
|
||||
fHsimRtlDbsList 0
|
||||
fHsimPePort 0
|
||||
fHsimPeXmr 0
|
||||
fHsimPePortDiag 0
|
||||
fHsimUdpDbs 0
|
||||
fHsimRemoveDbgCaps 0
|
||||
fFsdbGateOnepassTraverse 0
|
||||
fHsimAllowVecGateInVpd 1
|
||||
fHsimAllowAllVecGateInVpd 0
|
||||
fHsimAllowUdpInVpd 1
|
||||
fHsimAllowAlwaysCombInVpd 1
|
||||
fHsimAllowAlwaysCombCmpDvcSimv 0
|
||||
fHsimAllowAlwaysCombDbg 0
|
||||
fHsimMakeAllP2SPrimary 0
|
||||
fHsimMakeAllSeqPrimary 0
|
||||
fHsimNoCcnDump 0
|
||||
fHsimFsdbProfDiag 0
|
||||
fVpdSeqGate 0
|
||||
fVpdHsIntVecGate 0
|
||||
fVpdHsCmplxVecGate 0
|
||||
fVpdHsVecGateDiags 0
|
||||
fSeqGateCodePatch 0
|
||||
fVpdLongFaninOpt 0
|
||||
fVpdSeqLongFaninOpt 0
|
||||
fVpdNoLoopDetect 0
|
||||
fVpdNoSeqLoopDetect 0
|
||||
fVpdOptAllowConstDriver 0
|
||||
fVpdAllowCellReconstruction 0
|
||||
fVpdRtlForSharedLib 0
|
||||
fHsimVpdOptGate 1
|
||||
fHsimVpdOptDelay 0
|
||||
fHsimVpdOptMPDelay 0
|
||||
fHsimCbkOptDiag 0
|
||||
fHsimSK 0
|
||||
fHsimSharedKernel 1
|
||||
fHsimOnepass 0
|
||||
fHsimStitchNew 0
|
||||
fHsimParallelLevelize 0
|
||||
fHsimParallelLevelizeDbg 0
|
||||
fHsimSeqUdpDbsByteArray 0
|
||||
fHsimCoLocate 0
|
||||
fHsimSeqUdpEblkOpt 0
|
||||
fHsimSeqUdpEblkOptDiag 0
|
||||
fHsimGateInputAndDbsOffsetsOpt 1
|
||||
fHsimUdpDynElab 0
|
||||
fHsimCompressData 4
|
||||
fHsimIgnoreZForDfuse 1
|
||||
fHsimIgnoreDifferentCaps 0
|
||||
fHandleGlitchQC 1
|
||||
fGlitchDetectForAllRtlLoads 0
|
||||
fHsimFuseConstDriversOpt 1
|
||||
fHsimIgnoreReElab 0
|
||||
fHsimFuseMultiDrivers 0
|
||||
fHsimNoSched0Reg 0
|
||||
fHsimAmsFusionEnabled 0
|
||||
fHsimRtlDbs 0
|
||||
fHsimWakeupId 0
|
||||
fHsimPassiveIbn 0
|
||||
fHsimBcOpt 1
|
||||
fHsimCertitude 0
|
||||
fHsimCertRapAutoTest 0
|
||||
fHsimRaceDetect 0
|
||||
fCheckTcCond 0
|
||||
fHsimScanOptRelaxDbg 0
|
||||
fHsimScanOptRelaxDbgDynamic 0
|
||||
fHsimScanOptRelaxDbgDynamicPli 0
|
||||
fHsimScanOptRelaxDbgDiag 0
|
||||
fHsimScanOptRelaxDbgDiagHi 0
|
||||
fHsimScanOptNoErrorOnPliAccess 0
|
||||
fHsimScanOptTiming 0
|
||||
fRelaxIbnSchedCheck 0
|
||||
fHsimScanOptNoDumpCombo 0
|
||||
fHsimScanOptPrintSwitchState 0
|
||||
fHsimScanOptSelectiveSwitchOn 0
|
||||
fHsimScanOptSingleSEPliOpt 1
|
||||
fHsimScanOptDesignHasDebugAccessOnly 0
|
||||
fHsimScanOptPrintPcode 0
|
||||
fHsimScanDbgPerf 0
|
||||
fHsimNoStitchMap 0
|
||||
fHsimUnifiedModName 0
|
||||
fHsimCbkMemOptDebug 0
|
||||
fHsimMasterModuleOnly 0
|
||||
fHsimMdbOptimizeSelects 0
|
||||
fHsimMdbScalarizePorts 0
|
||||
fHsimMdbOptimizeSelectsHeuristic 1
|
||||
fHsimMdb1006Partition 0
|
||||
fHsimVectorPgate 0
|
||||
fHsimNoHs 0
|
||||
fHsimXmrPartition 0
|
||||
fHsimNewPartition 0
|
||||
fHsimElabPart 0
|
||||
fHsimNewPartTHold 0
|
||||
fHsimParitionCellInstNum 1000
|
||||
fHsimParitionCellNodeNum 1000
|
||||
fHsimParitionCellXMRNum 1000
|
||||
fHsimNewPartCutSingleInstLimit 268435455
|
||||
fHsimElabModDistNum 0
|
||||
fHsimNewPartAutoUpperLimit 0
|
||||
fHsimPCPortPartition 0
|
||||
fHsimPortPartition 0
|
||||
fHsimDumpMdb 0
|
||||
fHsimElabDiag 0
|
||||
fHsimSimpCollect 0
|
||||
fHsimPcodeDiag 0
|
||||
fHsimFastelab 0
|
||||
fHsimMacroOpt 0
|
||||
fHsimSkipOpt 0
|
||||
fHsimSkipOptFanoutlimit 0
|
||||
fHsimSkipOptRootlimit 0
|
||||
fHsimFuseDelayChains 0
|
||||
fFusempchainsFanoutlimit 0
|
||||
fFusempchainsDiagCount 0
|
||||
fHsimCgVectorGates 0
|
||||
fHsimCgVectorGates1 0
|
||||
fHsimCgVectorGates2 0
|
||||
fHsimCgVectorGatesNoReElab 0
|
||||
fHsimCgScalarGates 0
|
||||
fHsimCgScalarGatesExpr 0
|
||||
fHsimCgScalarGatesLut 0
|
||||
fHsimCgRtl 1
|
||||
fHsimCgRtlFilter 0
|
||||
fHsimCgRtlDebug 0
|
||||
fHsimCgRtlSize 15
|
||||
fHsimNewCgRt 0
|
||||
fHsimNewCgMPRt 0
|
||||
fHsimNewCgMPRetain 0
|
||||
fHsimCgRtlInfra 1
|
||||
fHsimGlueOpt 0
|
||||
fHsimPGatePatchOpt 0
|
||||
fHsimCgNoPic 0
|
||||
fHsimElabModCg 0
|
||||
fPossibleNullChecks 0
|
||||
fHsimProcessNoSplit 1
|
||||
fHsimMdbOptInSchedDelta 0
|
||||
fScaleTimeValue 0
|
||||
fDebugTimeScale 0
|
||||
fPartCompSDF 0
|
||||
fHsimNbaGate 1
|
||||
fDumpSDFBasedMod 1
|
||||
fOptimisticNtcSolver 0
|
||||
fHsimAllMtm 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimSdgOptEnable 0
|
||||
fHsimSVTypesRefPorts 0
|
||||
fHsimGrpByGrpElabIncr 0
|
||||
fHsimMarkRefereeInVcsElab 0
|
||||
fHsimStreamOpFix 1
|
||||
fHsimInterface 0
|
||||
fHsimMxWrapOpt 0
|
||||
fHsimMxTopBdryOpt 0
|
||||
fHsimClasses 0
|
||||
fHsimAggressiveDce 0
|
||||
fHsimDceDebug 1
|
||||
fHsimDceDebugUseHeuristics 1
|
||||
fHsimMdbNewDebugOpt 0
|
||||
fHsimMdbNewDebugOptExitOnError 1
|
||||
fHsimNewDebugOptMemDiag 0
|
||||
hsGlobalVerboseLevel 0
|
||||
fHsimMdbVectorConstProp 1
|
||||
fHsimEnableSeqUdpWrite 1
|
||||
fHsimDumpMDBOnlyForSeqUdp 0
|
||||
fHsimInitRegRandom 0
|
||||
fHsimInitRegRandomVcs 1
|
||||
fEnableNewFinalStrHash 0
|
||||
fEnableNewAssert 1
|
||||
fRunDbgDmma 0
|
||||
fAssrtCtrlSigChk 1
|
||||
fCheckSigValidity 0
|
||||
fUniqPriToAstRewrite 0
|
||||
fUniqPriToAstCtrl 0
|
||||
fAssertcontrolUniqPriNewImpl 0
|
||||
fRTLoopDectEna 0
|
||||
fCmplLoopDectEna 0
|
||||
fHsimMopFlow 1
|
||||
fUCaseLabelCtrl 0
|
||||
fUniSolRtSvaEna 1
|
||||
fUniSolSvaEna 1
|
||||
fXpropRtCtrlCallerOnly 0
|
||||
fHsimRaptorPart 0
|
||||
fHsimEnableDbsMemOpt 1
|
||||
fHsimDebugDbsMemOpt 0
|
||||
fHsimRenPart 0
|
||||
fHsimShortElabInsts 0
|
||||
fHsimXmrAllWires 0
|
||||
fHsimXmrDiag 0
|
||||
fHsimXmrPort 0
|
||||
fHsimFalcon 1
|
||||
fHsimGenForProfile 0
|
||||
fCompressSDF 0
|
||||
fDlpSvtbExclElab 0
|
||||
fHsimGates1209 0
|
||||
fHsimCgRtlNoShareSmd 0
|
||||
fHsimGenForErSum 0
|
||||
fVpdOpt 1
|
||||
fHsimMdbCell 0
|
||||
fHsimCellDebug 0
|
||||
fHsimNoPeekInMdbCell 0
|
||||
igetOpcodeSmdPtrLayoutId -1
|
||||
igetFieldSmdPtr -1
|
||||
fDebugDump 1
|
||||
fHsimOrigNodeNames 0
|
||||
fHsimCgVectors2VOnly 0
|
||||
fHsimMdbDeltaGate 0
|
||||
fHsimMdbVecDeltaGate 1
|
||||
fHsimVpdOptVfsDB 1
|
||||
fHsimMdbPruneVpdGates 1
|
||||
fHsimPcPe 0
|
||||
fHsimVpdGateOnlyFlag 1
|
||||
fHsimMxConnFrc 0
|
||||
fHsimNewForceCbkVec 0
|
||||
fHsimNewForceCbkVecDiag 0
|
||||
fHsimMdbReplaceVpdHighConn 1
|
||||
fHsimVpdOptSVTypes 1
|
||||
fHsHasPeUpXmr 0
|
||||
fHsimCompactVpdFn 1
|
||||
fHsimPIP 0
|
||||
fHsimRTLoopDectOrgName 0
|
||||
fHsimVpdOptPC 0
|
||||
fHsimFusePeXmrFo 0
|
||||
fHsimXmrSched 0
|
||||
fHsimNoMdg 0
|
||||
fHsimVectorGates 0
|
||||
fHsimRtlLite 0
|
||||
fHsimMdbcgLut 0
|
||||
fHsimMdbcgSelective 0
|
||||
fHsimVcselabGates 0
|
||||
fHsimMdbcgLevelize 0
|
||||
fHsimParGateEvalMode 0
|
||||
fHsimDFuseVectors 0
|
||||
fHsimDFuseZero 0
|
||||
fHsimDFuseOpt 1
|
||||
fHsimPruneOpt 0
|
||||
fHsimSeqUdpPruneWithConstInputs 0
|
||||
fHsimSafeDFuse 0
|
||||
fHsimVpdOptExpVec 0
|
||||
fHsimVpdOptSelGate 1
|
||||
fHsimVpdOptSkipFuncPorts 0
|
||||
fHsimVpdOptAlways 1
|
||||
fHsimVpdOptMdbCell 0
|
||||
fHsimVpdOptPartialMdb 1
|
||||
fHsimVpdOptPartitionGate 1
|
||||
fHsimVpdOptXmr 1
|
||||
fHsimVpdHilRtl 0
|
||||
fHsimSWave 0
|
||||
fHsimNoSched0InCell 1
|
||||
fHsimPartialMdb 0
|
||||
hsimPdbLargeOffsetThreshold 1048576
|
||||
fHsimFlatCell 0
|
||||
fHsimFlatCellLimit 0
|
||||
fHsimRegBank 0
|
||||
fHsimHmetisMaxPartSize 0
|
||||
fHsimHmetisGateWt 0
|
||||
fHsimHmetisUbFactor 0
|
||||
fHsimHmetis 0
|
||||
fHsimHmetisDiag 0
|
||||
fHsimRenumGatesForMdbCell 0
|
||||
fHsimHmetisMinPart 0
|
||||
fHsim2stCell 0
|
||||
fHsim2stCellMinSize 0
|
||||
fHsimMdbcgDebug 0
|
||||
fHsimMdbcgDebugLite 0
|
||||
fHsimMdbcgDistrib 0
|
||||
fHsimMdbcgSepmem 1
|
||||
fHsimMdbcgObjDiag 0
|
||||
fHsimMdbcg2stDiag 0
|
||||
fHsimMdbcgRttrace 0
|
||||
fHsimMdbVectorGateGroup 1
|
||||
fHsimMdbProcDfuse 1
|
||||
fHsimMdbHilPrune 0
|
||||
fHsCgOpt 1
|
||||
fHsCgOptUdp 1
|
||||
fHsCgOptRtl 1
|
||||
fHsCgOptDiag 0
|
||||
fHsCgOptAggr 0
|
||||
fHsCgOptNoZCheck 0
|
||||
fHsCgOptEnableZSupport 0
|
||||
fHsCgOpt4StateInfra 0
|
||||
fHsCgOptUdpChkDataForWakeup 1
|
||||
fHsCgOptXprop 0
|
||||
fHsimMdbcgDiag 0
|
||||
fHsCgMaxInputs 6
|
||||
fHsCgOptFwdPass 1
|
||||
fHsimHpnodes 0
|
||||
fLightDump 0
|
||||
fHDLCosim 0
|
||||
fHDLCosimDebug 0
|
||||
fHDLCosimTimeCoupled 0
|
||||
fHDLCosimTimeCoupledPorts 0
|
||||
HDLCosimMaxDataPerDpi 1
|
||||
HDLCosimMaxCallsPerDpi 2147483647
|
||||
fHDLCosimCompileDUT 0
|
||||
fHDLCosimCustomCompile 0
|
||||
fHDLCosimBoundaryAnalysis 0
|
||||
fVpdBeforeScan 1
|
||||
fHsCgOptMiSched0 0
|
||||
fgcAddSched0 0
|
||||
fParamClassOptRtDiag 0
|
||||
fHsRegress 0
|
||||
fHsBenchmark 0
|
||||
fHsimCgScalarVerilogForce 1
|
||||
fVcsElabToRoot 1
|
||||
fHilIbnObnCallByName 0
|
||||
fHsimMdbcgCellPartition 0
|
||||
fHsimCompressVpdSig 0
|
||||
fHsimLowPowerOpt 0
|
||||
fHsimUdpOpt 1
|
||||
fHsVecOneld 0
|
||||
fNativeVpdDebug 0
|
||||
fHsimVcsGenTLS 1
|
||||
fAssertSuccDebugLevelDump 0
|
||||
fHsimMinputsChangeCheck 0
|
||||
fHsimClkLayout 0
|
||||
fHsimIslandLayout 0
|
||||
fHsimConfigSched0 0
|
||||
fHsimSelectFuseAfterDfuse 0
|
||||
fHsimFoldedCell 0
|
||||
fHsimSWaveEmul 0
|
||||
fHsimSWaveDumpMDB 0
|
||||
fHsimSWaveDumpFlatData 0
|
||||
fHsimRenumberAlias 0
|
||||
fHsimAliasRenumbered 0
|
||||
fHilCgMode 115
|
||||
fHsimUnionOpt 0
|
||||
fHsimFuseSGDBoundaryNodes 0
|
||||
fHsimRemoveCapsVec 0
|
||||
fHsimCertRaptScal 0
|
||||
fHsimCertRaptMdbClock 0
|
||||
fHsCgOptMux 0
|
||||
fHsCgOptFrc 0
|
||||
fHsCgOpt30 0
|
||||
fHsLpNoCapsOpt 0
|
||||
fHsCgOpt4State 1
|
||||
fSkipStrChangeOnDelay 1
|
||||
fHsimTcheckOpt 0
|
||||
fHsCgOptMuxMClk 0
|
||||
fHsCgOptMuxFrc 0
|
||||
fHsCgOptNoPcb 0
|
||||
fHsCgOptMin1 0
|
||||
fHsCgOptUdpChk 0
|
||||
fHsChkXForSlowSigProp 1
|
||||
fHsimVcsParallelDbg 0
|
||||
fHsimVcsParallelStrategy 0
|
||||
fHsimVcsParallelOpt 0
|
||||
fHsimVcsParallelSubLevel 4
|
||||
fHsimParallelEblk 0
|
||||
fHsimByteCodeParts 1
|
||||
fFgpNovlInComp 0
|
||||
fFutEventPRL 0
|
||||
fFgpNbaDelay 0
|
||||
fHsimDbsFlagsByteArray 0
|
||||
fHsimDbsFlagsByteArrayTC 0
|
||||
fHsimDbsFlagsThreadArray 0
|
||||
fHsimGateEdgeEventSched 0
|
||||
fHsimEgschedDynelab 0
|
||||
fHsimUdpClkDynelab 0
|
||||
fUdpLayoutOnClk 0
|
||||
fDbsPreCheck 0
|
||||
fHsimSched0Analysis 0
|
||||
fHsimMultiDriverSched0 0
|
||||
fHsimLargeIbnSched 0
|
||||
fFgpHierarchical 0
|
||||
fFgpHierAllElabModAsRoot 0
|
||||
fFgpHierPCElabModAsRoot 0
|
||||
fFgpAdjustDataLevelOfLatch 1
|
||||
fHsimUdpXedgeEval 0
|
||||
fFgpRaceCheck 0
|
||||
fFgpUnifyClk 0
|
||||
fFgpSmallClkTree 0
|
||||
fFgpSmallRtlClkTree 4
|
||||
fFgpNoRtlUnlink 0
|
||||
fFgpNoRtlAuxLevel 0
|
||||
fFgpNumPartitions 8
|
||||
fFgpMultiSocketCompile 0
|
||||
fFgpDataDepOn 0
|
||||
fFgpDDIgnore 0
|
||||
fFgpTbCbOn 0
|
||||
fFgpTbEvOn 1
|
||||
fFgpTbNoVSA 0
|
||||
fFgpTbEvXmr 0
|
||||
fFgpDisabledLevel 512
|
||||
fFgpSched0User 0
|
||||
fFgpNoSdDelayedNbas 1
|
||||
fFgpTimingFlags 0
|
||||
fFgpSched0Level 0
|
||||
fHsimFgpMultiClock 0
|
||||
fFgpScanOptFix 0
|
||||
fFgpSched0UdpData 0
|
||||
fFgpDepositDiag 0
|
||||
fFgpEvtDiag.diagOn 0
|
||||
fFgpEvtDiag.printAllNodes 0
|
||||
fFgpMangleDiagLog 0
|
||||
fFgpMultiExclDiag 0
|
||||
fFgpSingleExclReason 0
|
||||
fHsDoFaninFanoutSanity 0
|
||||
fHsFgpNonDbsOva 1
|
||||
fFgpParallelTask 1
|
||||
fFgpIbnSched 0
|
||||
fFgpIbnSchedOpt 0
|
||||
fFgpIbnSchedThreshold 0
|
||||
fFgpIbnSchedDyn 0
|
||||
fFgpMpStateByte 0
|
||||
fFgpTcStateByte 0
|
||||
fHsimVirtIntfDynLoadSched 0
|
||||
fFgpNoRtimeFgp 0
|
||||
fHsFgpGlSched0 0
|
||||
fFgpExclReason 0
|
||||
fHsimIslandByIslandElab 0
|
||||
fHsimIslandByIslandFlat 151652416
|
||||
fHsimIslandByIslandFlat1 4
|
||||
fHsimVpdIBIF 0
|
||||
fHsimXmrIBIF 0
|
||||
fHsimReportTime 0
|
||||
fHsimElabJ 0
|
||||
hf_fHsimElabJ 0
|
||||
fHsimElabJOpt 0
|
||||
fHsimSchedMinput 0
|
||||
fHsimSchedSeqPrim 0
|
||||
fHsimSchedSelectFanout 0
|
||||
fHsimSchedSelectFanoutDebug 0
|
||||
fSpecifyInDesign 0
|
||||
fFgpDynamicReadOn 0
|
||||
fHsCgOptAllUc 0
|
||||
fHsimXmrRepl 0
|
||||
fZoix 0
|
||||
fHsimDfuseNewOpt 0
|
||||
fHsimBfuseNewOpt 0
|
||||
fFgpXmrSched 0
|
||||
fHsimClearClkCaps 0
|
||||
fHsimDiagClkConfig 0
|
||||
fHsimDiagClkConfigDebug 0
|
||||
fHsimDiagClkConfigDumpAll 0
|
||||
fHsDiagClkConfigPara 0
|
||||
fHsimDiagClkConfigAn 0
|
||||
fHsimCanDumpClkConfig 0
|
||||
fFgpInitRout 0
|
||||
fFgpIgnoreExclSD 0
|
||||
fHsCgOptNoClockFusing 0
|
||||
fHsClkWheelLimit 50000
|
||||
fHsimPCSharedLibSpecified 0
|
||||
fHsFgpSchedCgUcLoads 1
|
||||
fHsCgOptNewSelCheck 1
|
||||
fFgpReportUnsafeFuncs 0
|
||||
fHsCgOptUncPrlThreshold 4
|
||||
fHsimLowPowerRetAnalysisInChild 0
|
||||
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user