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Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10

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Core_kingdom
2025-08-06 22:43:11 +08:00
parent 60ce7951ec
commit 22f0c2aa7f
61 changed files with 1074 additions and 1817 deletions
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4
rtl/frame_arbiter.v
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@@ -29,10 +29,10 @@ module frame_arbiter(
assign axi2array_frame_valid = (cur_state == FARB_WR) && wframe_valid ||
(cur_state == FARB_RD) && rframe_valid;
assign axi2array_frame_data = {rw_frag,frame};
assign axi2array_frame_data = {rw_flag,frame};
assign wframe_ready = (cur_state == FARB_WR) && axi2array_frame_ready;
assign rframe_ready = (cur_state == FARB_RD) && axi2array_frame_ready;
assign rwflag = (cur_state == FARB_WR);
assign rw_flag = (cur_state == FARB_WR);
assign frame = (cur_state == FARB_WR) ? wframe_data[159:8]:
rframe_data[159:8];
assign len = (cur_state == FARB_WR) ? wframe_data[7:0]:

4
rtl/rchannel.v
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@@ -118,8 +118,8 @@ module rchannel (
rframe_cnt == arlen >> 1'b1;
assign sync_fifo_arlen_wr_data = arlen;
assign sync_fifo_arlen_rd_en = axi_s_rlast && axi_s_rvalid;
assign rsof = rframe_valid && (rframe_cnt == 7'b0 || rcaddr == 6'd0);
assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1 || rcaddr == 6'h3f);
assign rsof = rframe_valid && (rframe_cnt == 7'b0);
assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1);
assign sync_fifo_r_wr_en = array2axi_rdata_valid && !sync_fifo_r_full;

6
rtl/sync_fifo_128_to_64.v
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@@ -1,9 +1,8 @@
module sync_fifo_128_to_64 #(
parameter DATA_IN_WIDTH = 128,
parameter DATA_OUT_WIDTH = 64,
parameter FIFO_DEPTH = 16,
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
)(
parameter FIFO_DEPTH = 16
)(
input clk,
input rst_n,
input wr_en,
@@ -13,6 +12,7 @@ module sync_fifo_128_to_64 #(
output [DATA_OUT_WIDTH-1:0] rd_data,
output empty
);
localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
reg [DATA_OUT_WIDTH-1:0] mem [0 :FIFO_DEPTH -1];
reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;

6
rtl/sync_fifo_64_to_128.v
View File

@@ -1,8 +1,8 @@
module sync_fifo_64_to_128 #(
parameter DATA_IN_WIDTH = 64,
parameter DATA_OUT_WIDTH = 128,
parameter FIFO_DEPTH = 16,
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
parameter FIFO_DEPTH = 16
)(
input clk,
input rst_n,
@@ -13,7 +13,7 @@ module sync_fifo_64_to_128 #(
output [DATA_OUT_WIDTH-1:0] rd_data,
output empty
);
localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
reg [DATA_IN_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;