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Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10

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Core_kingdom
2025-08-06 22:43:11 +08:00
parent 60ce7951ec
commit 22f0c2aa7f
61 changed files with 1074 additions and 1817 deletions
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BIN
sim/csrc/cgincr.sdb
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429
sim/csrc/cginfo.json
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@@ -1,36 +1,34 @@
{
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@@ -38,15 +36,15 @@
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@@ -54,30 +52,30 @@
"stat": [
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{
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@@ -85,15 +83,15 @@
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@@ -101,15 +99,15 @@
"stat": [
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@@ -117,15 +115,15 @@
"stat": [
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@@ -135,15 +133,15 @@
"stat": [
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@@ -151,30 +149,30 @@
"stat": [
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@@ -182,15 +180,15 @@
"stat": [
"DoPass2",
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@@ -200,15 +198,15 @@
"stat": [
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@@ -218,59 +216,29 @@
"stat": [
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}
],
"CurCompileUdps": {},
"CompileProcesses": [
"cgproc.12247.json"
],
"CurCompileModules": [
"...MASTER...",
"std",
"tb_rchannel"
],
"PrevCompiledModules": {
"std": {
"reYIK_d": {
"bytes": 43078,
"mod": "std",
"out": "reYIK_d.o",
"mode": 4,
"checksum": 0,
"archive": "archive.1/_prev_archive_1.a"
}
},
"tb_rchannel": {
"TJvMf_d": {
"bytes": 94788,
"mod": "tb_rchannel",
"out": "TJvMf_d.o",
"mode": 4,
"checksum": 0,
"archive": "archive.1/_prev_archive_1.a"
}
},
"...MASTER...": {
"amcQw_d": {
"bytes": 7904,
"mod": "...MASTER...",
"out": "objs/amcQw_d.o",
"mode": 4,
"checksum": 0
}
}
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"incremental": "on",
"MlibObjs": {},
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"rlimit": {
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"stack": -1
},
"CompileStrategy": "fullobj",
"PrevCompiledModules": {},
"NameTable": {
"std": [
"std",
@@ -291,87 +259,92 @@
3
]
},
"stat": {
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},
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"ru_nivcsw": 4
},
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},
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],
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"bytes": 117070,
"archive": "archive.1/_12247_archive_1.a",
"text": 0
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"archive": "archive.0/_25796_archive_1.a"
},
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},
"incremental": "on",
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"CompileProcesses": [
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],
"Misc": {
"vcs_version": "O-2018.09-1_Full64",
"csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
"cwd": "/home/ICer/ic_prjs/mc/sim",
"archive_dir": "archive.0",
"csrc": "csrc",
"master_pid": 25796,
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
"hostname": "IC_EDA",
"master_pid": 12247,
"csrc": "csrc",
"daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
"daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
"default_output_dir": "csrc",
"archive_dir": "archive.1"
},
"rlimit": {
"data": -1,
"stack": -1
"cwd": "/home/ICer/ic_prjs/mc/IC_PRJ/sim",
"daidir_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir",
"csrc_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc",
"daidir": "simv.daidir",
"default_output_dir": "csrc"
},
"CompileStatus": "Successful"
}

29
sim/csrc/filelist.cu
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@@ -1,26 +1,15 @@
PIC_LD=ld
ARCHIVE_OBJS=
ARCHIVE_OBJS += _12247_archive_1.so
_12247_archive_1.so : archive.1/_12247_archive_1.a
ARCHIVE_OBJS += _25796_archive_1.so
_25796_archive_1.so : archive.0/_25796_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_12247_archive_1.so --whole-archive $< --no-whole-archive
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_25796_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_12247_archive_1.so $@
ARCHIVE_OBJS += _prev_archive_1.so
_prev_archive_1.so : archive.1/_prev_archive_1.a
@$(AR) -s $<
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
@rm -f $@
@ln -sf .//../simv.daidir//_prev_archive_1.so $@
@ln -sf .//../simv.daidir//_25796_archive_1.so $@
VCS_ARC0 =_csrc0.so
VCS_OBJS0 =objs/amcQw_d.o
O0_OBJS =
@@ -31,12 +20,6 @@ $(O0_OBJS) : %.o: %.c
%.o: %.c
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
$(VCS_ARC0) : $(VCS_OBJS0)
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
rm -f $(VCS_ARC0)
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
CU_UDP_OBJS = \
@@ -44,7 +27,7 @@ CU_LVL_OBJS = \
SIM_l.o
MAIN_OBJS = \
objs/amcQw_d.o
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)

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sim/csrc/hsim/hsim.sdb
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sim/csrc/objs/amcQw_d.o
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