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Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10

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Core_kingdom
2025-08-06 22:43:11 +08:00
parent 60ce7951ec
commit 22f0c2aa7f
61 changed files with 1074 additions and 1817 deletions
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sim/simv.daidir/debug_dump/src_files_verilog
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@@ -1,4 +1,4 @@
/home/ICer/ic_prjs/mc/rtl/rchannel.v
/home/ICer/ic_prjs/mc/rtl/sync_fifo.v
/home/ICer/ic_prjs/mc/rtl/sync_fifo_128_to_64.v
/home/ICer/ic_prjs/mc/tb/tb_rchannel.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/rchannel.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo_128_to_64.v
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v