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Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10

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Core_kingdom
2025-08-06 22:43:11 +08:00
parent 60ce7951ec
commit 22f0c2aa7f
61 changed files with 1074 additions and 1817 deletions
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30
sim/verdiLog/novas_sim.log
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@@ -1,30 +1,18 @@
Invoking simulator...
Verdi>simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
*Verdi* : Flush all FSDB Files at 0 ps.
*Verdi* : Enable RPC Server(12621)
*Verdi* : Enable RPC Server(26345)
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
Verdi>fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
*Verdi* : Dumping the signal (tb_rchannel.clk).
*Verdi* : Dumping the signal (tb_rchannel.rframe_data).
*Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
*Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
*Verdi* : Dumping the signal (tb_rchannel.rst_n).
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
Verdi>fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
*Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
*Verdi* : End of dumping.
*Verdi* : Flush all FSDB Files at 0 ps.
*Verdi* : Flush all FSDB Files at 0 ps.
Verdi>run
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
@@ -36,6 +24,6 @@ Simulation complete, time is 365000 ps.
tb_rchannel.v, 1 : module tb_rchannel;
V C S S i m u l a t i o n R e p o r t
Time: 365000 ps
CPU Time: 0.200 seconds; Data structure size: 0.0Mb
Tue Aug 5 22:01:50 2025
CPU Time: 0.250 seconds; Data structure size: 0.0Mb
Wed Aug 6 22:41:15 2025
debExit