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Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10

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Core_kingdom
2025-08-06 22:43:11 +08:00
parent 60ce7951ec
commit 22f0c2aa7f
61 changed files with 1074 additions and 1817 deletions
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55
sim/verdiLog/sim.log
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@@ -1,36 +1,36 @@
Command: /home/ICer/ic_prjs/mc/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
Command: /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
ucli% synUtils::getArch
linux64
ucli% loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd
LoadFSDBDumpCmd success
ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/sim/inter.fsdb} ;fsdbDumpflush ;
ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb} ;fsdbDumpflush ;
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
*Verdi* : Flush all FSDB Files at 0 ps.
ucli% sps_interactive
*Verdi* : Enable RPC Server(12621)
*Verdi* : Enable RPC Server(26345)
ucli% ucliCore::getToolPID
12621
26345
ucli% ucliCore::getToolPID
12621
26345
ucli% if {[catch {ucliCore::setFocus tool}]} {}
ucli% puts $ucliCore::nativeUcliMode
0
ucli% ucliCore::getToolTopPID
12621
26345
ucli% pid
12635
ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.12621 }
26359
ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.26345 }
ucli% if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024}
1024
@@ -64,21 +64,10 @@ ucli% lappend ucliCore::resultTagsForVerdi <?special_verdi_begin?> <?special_ver
<?special_verdi_begin?> <?special_verdi_end?>
ucli% if {[catch {ucliCore::setFocus tool}]} {}
ucli% fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
*Verdi* : Dumping the signal (tb_rchannel.clk).
*Verdi* : Dumping the signal (tb_rchannel.rframe_data).
*Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
*Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
*Verdi* : Dumping the signal (tb_rchannel.rst_n).
ucli% fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
*Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
*Verdi* : End of dumping.
*Verdi* : Flush all FSDB Files at 0 ps.
ucli% fsdbDumpflush
*Verdi* : Flush all FSDB Files at 0 ps.
@@ -103,10 +92,10 @@ hasTB: 0
inputFilename:
keyFilename: ucli.key
line: 1
logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
macroIndex: -1
macroOffset: -1
pid: 12621
pid: 26345
scope: tb_rchannel
startCol: 0
state: stopped
@@ -124,8 +113,6 @@ ucli% if {[catch {ucliCore::setFocus tool}]} {}
ucli% checkpoint -list -all
There are no checkpoints present.
ucli% if {[catch {ucliCore::setFocus tool}]} {}
ucli% stop
No stop points are set
ucli% if {[catch {ucliCore::setFocus tool}]} {}
@@ -142,7 +129,7 @@ tb_rchannel.v, 1 : module tb_rchannel;
ucli% synEnv::hasFataled
0
ucli% ucliCore::getToolPID
12621
26345
ucli% save::getUserdefinedProcs
::stateVerdiChangeCB ::LoadFSDBDumpCmd
ucli% if {[catch {ucliCore::setFocus tool}]} {}
@@ -165,10 +152,10 @@ hasTB: 0
inputFilename:
keyFilename: ucli.key
line: 1
logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
macroIndex: -1
macroOffset: -1
pid: 12621
pid: 26345
scope: tb_rchannel
startCol: 0
state: stopped
@@ -195,8 +182,8 @@ ucli% if {[catch {ucliCore::setFocus tool}]} {}
ucli% finish; quit
V C S S i m u l a t i o n R e p o r t
Time: 365000 ps
CPU Time: 0.200 seconds; Data structure size: 0.0Mb
Tue Aug 5 22:01:50 2025
CPU Time: 0.250 seconds; Data structure size: 0.0Mb
Wed Aug 6 22:41:15 2025
VERDI_SIM_Terminated