Finish top-module(axi_slave test_successful): 2025-08-06 22:43:10
This commit is contained in:
Core_kingdom
BIN
.Makefile.swp
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BIN
.Makefile.swp
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2
Makefile
2
Makefile
@@ -1,4 +1,4 @@
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COMMIT_MSG ?= "Auto-commit: $(shell date '+%Y-%m-%d %H:%M:%S')"
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COMMIT_MSG ?= "Finish top-module(axi_slave test_successful): $(shell date '+%Y-%m-%d %H:%M:%S')"
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#--------------------------------------------------------------
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help:
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@@ -29,10 +29,10 @@ module frame_arbiter(
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assign axi2array_frame_valid = (cur_state == FARB_WR) && wframe_valid ||
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(cur_state == FARB_RD) && rframe_valid;
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assign axi2array_frame_data = {rw_frag,frame};
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assign axi2array_frame_data = {rw_flag,frame};
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assign wframe_ready = (cur_state == FARB_WR) && axi2array_frame_ready;
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assign rframe_ready = (cur_state == FARB_RD) && axi2array_frame_ready;
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assign rwflag = (cur_state == FARB_WR);
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assign rw_flag = (cur_state == FARB_WR);
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assign frame = (cur_state == FARB_WR) ? wframe_data[159:8]:
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rframe_data[159:8];
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assign len = (cur_state == FARB_WR) ? wframe_data[7:0]:
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@@ -118,8 +118,8 @@ module rchannel (
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rframe_cnt == arlen >> 1'b1;
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assign sync_fifo_arlen_wr_data = arlen;
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assign sync_fifo_arlen_rd_en = axi_s_rlast && axi_s_rvalid;
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assign rsof = rframe_valid && (rframe_cnt == 7'b0 || rcaddr == 6'd0);
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assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1 || rcaddr == 6'h3f);
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assign rsof = rframe_valid && (rframe_cnt == 7'b0);
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assign reof = rframe_valid && (rframe_cnt == arlen >>1'b1);
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assign sync_fifo_r_wr_en = array2axi_rdata_valid && !sync_fifo_r_full;
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@@ -1,9 +1,8 @@
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module sync_fifo_128_to_64 #(
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parameter DATA_IN_WIDTH = 128,
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parameter DATA_OUT_WIDTH = 64,
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parameter FIFO_DEPTH = 16,
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parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
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)(
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parameter FIFO_DEPTH = 16
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)(
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input clk,
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input rst_n,
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input wr_en,
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@@ -13,6 +12,7 @@ module sync_fifo_128_to_64 #(
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output [DATA_OUT_WIDTH-1:0] rd_data,
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output empty
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);
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localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
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reg [DATA_OUT_WIDTH-1:0] mem [0 :FIFO_DEPTH -1];
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reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
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@@ -1,8 +1,8 @@
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module sync_fifo_64_to_128 #(
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parameter DATA_IN_WIDTH = 64,
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parameter DATA_OUT_WIDTH = 128,
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parameter FIFO_DEPTH = 16,
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parameter ADDR_WIDTH = $clog2(FIFO_DEPTH)
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parameter FIFO_DEPTH = 16
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)(
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input clk,
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input rst_n,
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@@ -13,7 +13,7 @@ module sync_fifo_64_to_128 #(
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output [DATA_OUT_WIDTH-1:0] rd_data,
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output empty
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);
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localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
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reg [DATA_IN_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
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reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
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wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
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@@ -1,36 +1,34 @@
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@@ -38,15 +36,15 @@
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@@ -85,15 +83,15 @@
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@@ -117,15 +115,15 @@
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"ru_utime_sec": 0.047620999999999997,
|
||||
"ru_nvcsw": 25,
|
||||
"ru_stime_sec": 0.045328,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 30316,
|
||||
"ru_minflt": 10693,
|
||||
"ru_nivcsw": 23
|
||||
},
|
||||
"CodeGen(%)": 40.089553730768436,
|
||||
"nMops": 7030,
|
||||
"cpu_cycles_total": 659455284,
|
||||
"nQuads": 2556,
|
||||
"totalObjSize": 262988,
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.29250999999999999,
|
||||
"ru_nvcsw": 32,
|
||||
"ru_stime_sec": 0.055988000000000003,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 88536,
|
||||
"ru_minflt": 30657,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"cpu_cycles_end": 8955513736141,
|
||||
"quadSpeed": 18744.912252396287,
|
||||
"outputSizePerQuad": 102.8904538341158,
|
||||
"Frontend(%)": 59.910446269231564,
|
||||
"peak_mem_kb": 283444
|
||||
},
|
||||
"CurCompileModules": [
|
||||
"...MASTER...",
|
||||
"...MASTER...",
|
||||
"std",
|
||||
"std",
|
||||
"tb_rchannel",
|
||||
"tb_rchannel"
|
||||
],
|
||||
"CurCompileUdps": {},
|
||||
"SIMBData": {
|
||||
"out": "amcQwB.o",
|
||||
"bytes": 117070,
|
||||
"archive": "archive.1/_12247_archive_1.a",
|
||||
"text": 0
|
||||
"bytes": 117874,
|
||||
"text": 0,
|
||||
"archive": "archive.0/_25796_archive_1.a"
|
||||
},
|
||||
"cpu_cycles_pass2_start": 3307450168560,
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
],
|
||||
"stat": {
|
||||
"ru_self_cgstart": {
|
||||
"ru_maxrss_kb": 80808,
|
||||
"ru_utime_sec": 0.090082999999999996,
|
||||
"ru_stime_sec": 0.080764000000000002,
|
||||
"ru_minflt": 25946,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 27,
|
||||
"ru_nivcsw": 9
|
||||
},
|
||||
"ru_self_end": {
|
||||
"ru_maxrss_kb": 90168,
|
||||
"ru_utime_sec": 0.126638,
|
||||
"ru_stime_sec": 0.086485000000000006,
|
||||
"ru_minflt": 29557,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 29,
|
||||
"ru_nivcsw": 9
|
||||
},
|
||||
"ru_childs_cgstart": {
|
||||
"ru_maxrss_kb": 29296,
|
||||
"ru_utime_sec": 0.033097000000000001,
|
||||
"ru_stime_sec": 0.028851000000000002,
|
||||
"ru_minflt": 10148,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 26,
|
||||
"ru_nivcsw": 22
|
||||
},
|
||||
"cpu_cycles_total": 381884822,
|
||||
"cpu_cycles_cgstart": 3307450206879,
|
||||
"nMops": 7107,
|
||||
"Frontend(%)": 77.115222086580886,
|
||||
"ru_childs_end": {
|
||||
"ru_maxrss_kb": 29668,
|
||||
"ru_utime_sec": 0.033097000000000001,
|
||||
"ru_stime_sec": 0.032874,
|
||||
"ru_minflt": 10742,
|
||||
"ru_majflt": 0,
|
||||
"ru_nvcsw": 27,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"cpu_cycles_end": 3307534843637,
|
||||
"nQuads": 2574,
|
||||
"totalObjSize": 117070,
|
||||
"mopSpeed": 194419.36807550257,
|
||||
"CodeGen(%)": 22.884777913419111,
|
||||
"quadSpeed": 70414.443988510422,
|
||||
"mop/quad": 2.7610722610722611,
|
||||
"outputSizePerQuad": 45.481740481740481,
|
||||
"peak_mem_kb": 284132,
|
||||
"realTime": 0.23830199241638184
|
||||
},
|
||||
"incremental": "on",
|
||||
"PEModules": [],
|
||||
"CompileProcesses": [
|
||||
"cgproc.25796.json"
|
||||
],
|
||||
"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/sim/csrc",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"cwd": "/home/ICer/ic_prjs/mc/sim",
|
||||
"archive_dir": "archive.0",
|
||||
"csrc": "csrc",
|
||||
"master_pid": 25796,
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"hostname": "IC_EDA",
|
||||
"master_pid": 12247,
|
||||
"csrc": "csrc",
|
||||
"daidir": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/sim/simv.daidir",
|
||||
"default_output_dir": "csrc",
|
||||
"archive_dir": "archive.1"
|
||||
},
|
||||
"rlimit": {
|
||||
"data": -1,
|
||||
"stack": -1
|
||||
"cwd": "/home/ICer/ic_prjs/mc/IC_PRJ/sim",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc",
|
||||
"daidir": "simv.daidir",
|
||||
"default_output_dir": "csrc"
|
||||
},
|
||||
"CompileStatus": "Successful"
|
||||
}
|
||||
@@ -1,26 +1,15 @@
|
||||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _12247_archive_1.so
|
||||
_12247_archive_1.so : archive.1/_12247_archive_1.a
|
||||
ARCHIVE_OBJS += _25796_archive_1.so
|
||||
_25796_archive_1.so : archive.0/_25796_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_12247_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_25796_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_12247_archive_1.so $@
|
||||
|
||||
|
||||
ARCHIVE_OBJS += _prev_archive_1.so
|
||||
_prev_archive_1.so : archive.1/_prev_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_prev_archive_1.so $@
|
||||
@ln -sf .//../simv.daidir//_25796_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
VCS_ARC0 =_csrc0.so
|
||||
|
||||
VCS_OBJS0 =objs/amcQw_d.o
|
||||
|
||||
|
||||
O0_OBJS =
|
||||
@@ -31,12 +20,6 @@ $(O0_OBJS) : %.o: %.c
|
||||
|
||||
%.o: %.c
|
||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
||||
|
||||
$(VCS_ARC0) : $(VCS_OBJS0)
|
||||
$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0)
|
||||
rm -f $(VCS_ARC0)
|
||||
@ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0)
|
||||
|
||||
CU_UDP_OBJS = \
|
||||
|
||||
|
||||
@@ -44,7 +27,7 @@ CU_LVL_OBJS = \
|
||||
SIM_l.o
|
||||
|
||||
MAIN_OBJS = \
|
||||
objs/amcQw_d.o
|
||||
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,13 +1,14 @@
|
||||
#../rtl/sync_fifo_128_to_64.v
|
||||
../rtl/sync_fifo_128_to_64.v
|
||||
#../rtl/sync_fifo_64_to_128.v
|
||||
#../rtl/async_fifo.v
|
||||
#../rtl/wchannel.v
|
||||
#../rtl/sync_fifo.v
|
||||
#../rtl/rchannel.v
|
||||
../rtl/frame_arbiter.v
|
||||
../rtl/sync_fifo.v
|
||||
../rtl/rchannel.v
|
||||
#../rtl/frame_arbiter.v
|
||||
#../tb/tb_sync_fifo_128_to_64.v
|
||||
#../tb/tb_async_fifo.v
|
||||
#../tb/tb_sync_fifo_64_to_128.v
|
||||
#../tb/tb_sync_fifo.v
|
||||
#../tb/tb_wchannel.v
|
||||
#../tb/tb_rchannel.v
|
||||
../tb/tb_rchannel.v
|
||||
#../tb/tb_frame_arbiter.v
|
||||
|
||||
BIN
sim/inter.fsdb
BIN
sim/inter.fsdb
Binary file not shown.
661
sim/novas.conf
661
sim/novas.conf
File diff suppressed because one or more lines are too long
76
sim/novas.rc
76
sim/novas.rc
@@ -277,12 +277,12 @@ CellNameToCase =
|
||||
PinNameToCase =
|
||||
[InteractiveDebug]
|
||||
tbvLocalWatchArrayLimit = 50
|
||||
Watch_0 = 150 80 217 0
|
||||
Watch_1 = 150 80 80 287
|
||||
Watch_2 = 150 80 80 200
|
||||
Watch_3 = 150 80 80 200
|
||||
Watch_4 = 150 80 80 200
|
||||
Watch_5 = 150 80 80 200
|
||||
Watch_0 = 150 80 80 0
|
||||
Watch_1 = 150 80 80 306
|
||||
Watch_2 = 150 80 80 200
|
||||
Watch_3 = 150 80 80 200
|
||||
Watch_4 = 150 80 80 200
|
||||
Watch_5 = 150 80 80 200
|
||||
[Language]
|
||||
EditWindow_Font = COURIER12
|
||||
Background = ID_WHITE
|
||||
@@ -376,8 +376,8 @@ saveWaveformStat = TRUE
|
||||
savePropStat = FALSE
|
||||
savePropDtl = TRUE
|
||||
[QtDialog]
|
||||
qWaveSignalDialog = 0,65,800,479
|
||||
QwUserAskDlg = 797,387,324,134
|
||||
qWaveSignalDialog = 547,204,800,479
|
||||
QwUserAskDlg = 795,385,324,134
|
||||
[Relationship]
|
||||
hideRecursiceNode = FALSE
|
||||
[Session Cache]
|
||||
@@ -385,7 +385,7 @@ hideRecursiceNode = FALSE
|
||||
3 = string (session file name)
|
||||
4 = string (session file name)
|
||||
5 = string (session file name)
|
||||
1 = /home/ICer/ic_prjs/mc/sim/verdiLog/novas_autosave.ses
|
||||
1 = /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/novas_autosave.ses
|
||||
[Simulation]
|
||||
scsPath = scsim
|
||||
scsOption =
|
||||
@@ -450,8 +450,8 @@ iscCmdSep = FALSE
|
||||
ScsDebugAll = FALSE
|
||||
NoAppendOption = FALSE
|
||||
invokeSimPath = work
|
||||
vcs_svOption = -sml=verdi
|
||||
smartlog = TRUE
|
||||
vcs_svOption = -sml=verdi
|
||||
[SimulationPlus2]
|
||||
eventDumpUnfinish = FALSE
|
||||
dumpPowerRoot = FALSE
|
||||
@@ -567,7 +567,7 @@ pdmlMacro = ID_BLACK
|
||||
font = COURIER12
|
||||
annotFont = Helvetica_M_R_10
|
||||
[Text.1]
|
||||
viewport = -1 27 1918 778 45
|
||||
viewport = -10 20 1914 774 45
|
||||
[TextPrinter]
|
||||
Orientation = Landscape
|
||||
Indicator = FALSE
|
||||
@@ -659,27 +659,27 @@ DefaultLogTimeUnit = "1.000000ns"
|
||||
parRuleSets = "/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_OVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_UVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRule\
|
||||
s/par_rule_LP.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_VCS.rc "
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column0]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
name = Time
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column1]
|
||||
name = Code
|
||||
width = 60
|
||||
visualIndex = 2
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Type
|
||||
width = 60
|
||||
visualIndex = 3
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column3]
|
||||
name = Time
|
||||
name = Code
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
visualIndex = 2
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column4]
|
||||
@@ -695,23 +695,23 @@ DefaultLogTimeUnit = "1.000000ns"
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0]
|
||||
parRuleSets = ""
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1]
|
||||
name = Code
|
||||
name = Severity
|
||||
width = 60
|
||||
visualIndex = 2
|
||||
visualIndex = 1
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2]
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1]
|
||||
name = Type
|
||||
width = 60
|
||||
visualIndex = 3
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3]
|
||||
name = Time
|
||||
width = 60
|
||||
@@ -719,9 +719,9 @@ visualIndex = 0
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4]
|
||||
name = Severity
|
||||
name = Code
|
||||
width = 60
|
||||
visualIndex = 1
|
||||
visualIndex = 2
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.parRule]
|
||||
@@ -741,8 +741,8 @@ ovaForbidSuccessColor = -c ID_GREEN5
|
||||
SigGroupRuleFile =
|
||||
DisplayFileName = FALSE
|
||||
waveform_vertical_scroll_bar = TRUE
|
||||
getSignalForm = 0 28 800 479 164 381 390 89
|
||||
viewPort = 0 27 1293 439 181 244
|
||||
getSignalForm = 547 167 800 479 164 381 390 89
|
||||
viewPort = 0 27 1914 590 285 195
|
||||
signalSpacing = 5
|
||||
digitalSignalHeight = 15
|
||||
analogSignalHeight = 98
|
||||
@@ -986,7 +986,7 @@ maskIsolation = TRUE
|
||||
maskRetention = TRUE
|
||||
maskDrivingPowerOff = TRUE
|
||||
maskToggle = TRUE
|
||||
autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/mc/sim/verdiLog\"" "\"novas_autosave_sig\""
|
||||
autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog\"" "\"novas_autosave_sig\""
|
||||
signal_rc_attribute = 65535
|
||||
signal_rc_alias_attribute = 0
|
||||
ConvertAttr1 = -inc FALSE
|
||||
@@ -1014,7 +1014,7 @@ curveWindow_Drag&Drop_Mode = TRUE
|
||||
hspiceIncOpenMode = TRUE
|
||||
pcSelectMode = TRUE
|
||||
hierarchyDelimiter = /
|
||||
RecentFile1 = "\"/home/ICer/ic_prjs/mc/sim/tb.fsdb\""
|
||||
RecentFile1 = "\"/home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb\""
|
||||
open_file_time_range = FALSE
|
||||
open_file_dir
|
||||
open_rc_file_dir
|
||||
@@ -1342,7 +1342,7 @@ AddImportArgument = FALSE
|
||||
LineBreakWithScope = TRUE
|
||||
StopAfterCompileOption = -s
|
||||
[wave.0]
|
||||
viewPort = 0 27 1293 439 181 244
|
||||
viewPort = 0 27 1914 590 285 195
|
||||
[wave.1]
|
||||
viewPort = 127 219 960 332 100 65
|
||||
[wave.2]
|
||||
|
||||
@@ -2,121 +2,121 @@
|
||||
# log primitive debug message of FSDB dumping #
|
||||
# This is for R&D to analyze when there are issues happening when FSDB dump #
|
||||
#######################################################################################
|
||||
ANF: vcsd_get_serial_mode_status('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('/home/ICer/ic_prjs/mc/sim/simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
ANF: vcsd_get_serial_mode_status('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
VCS compile option:
|
||||
option[0]: /home/ICer/ic_prjs/mc/sim/simv
|
||||
option[0]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv
|
||||
option[1]: -sml=verdi
|
||||
option[2]: +fsdb+gate=off
|
||||
option[3]: -ucli2Proc
|
||||
option[4]: -ucli
|
||||
option[5]: -l
|
||||
option[6]: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
option[6]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
option[7]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
option[8]: -Mcc=gcc
|
||||
option[9]: -Mcplusplus=g++
|
||||
@@ -136,31 +136,24 @@ VCS compile option:
|
||||
option[23]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[24]: -Xvcs_run_simv=1
|
||||
option[25]: -timescale=1ns/1ps
|
||||
option[26]: -Xcbug=0x1
|
||||
option[27]: -o
|
||||
option[28]: simv
|
||||
option[29]: -full64
|
||||
option[30]: +vc
|
||||
option[31]: +v2k
|
||||
option[32]: -debug_access+all
|
||||
option[33]: +vpi
|
||||
option[34]: +vcsd1
|
||||
option[35]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[36]: -picarchive
|
||||
option[37]: +cli+4
|
||||
option[38]: -debug=3
|
||||
option[39]: +memcbk
|
||||
option[40]: -P
|
||||
option[41]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[42]: -fsdb
|
||||
option[43]: -sverilog
|
||||
option[44]: +vpi
|
||||
option[45]: -gen_obj
|
||||
option[46]: -f
|
||||
option[47]: filelist.f
|
||||
option[48]: -load
|
||||
option[49]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[50]: timescale=1ns/1ps
|
||||
option[26]: -full64
|
||||
option[27]: +vc
|
||||
option[28]: +v2k
|
||||
option[29]: -debug_access+all
|
||||
option[30]: +vpi
|
||||
option[31]: +vcsd1
|
||||
option[32]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[33]: -picarchive
|
||||
option[34]: -P
|
||||
option[35]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[36]: -fsdb
|
||||
option[37]: -sverilog
|
||||
option[38]: -gen_obj
|
||||
option[39]: -f
|
||||
option[40]: filelist.f
|
||||
option[41]: -load
|
||||
option[42]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[43]: timescale=1ns/1ps
|
||||
Chronologic Simulation VCS Release O-2018.09-1_Full64
|
||||
Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
|
||||
CPU cores: 8
|
||||
@@ -169,7 +162,7 @@ Limit information:
|
||||
cputime unlimited
|
||||
filesize unlimited
|
||||
datasize unlimited
|
||||
stacksize unlimited
|
||||
stacksize 8192 kbytes
|
||||
coredumpsize 0 kbytes
|
||||
memoryuse unlimited
|
||||
vmemoryuse unlimited
|
||||
@@ -182,11 +175,10 @@ maxproc 4096
|
||||
Runtime environment variables:
|
||||
XDG_VTNR=1
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
SSH_AGENT_PID=3332
|
||||
SSH_AGENT_PID=3826
|
||||
XDG_SESSION_ID=1
|
||||
HOSTNAME=IC_EDA
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
NOVAS_SYNC_MOTIF_DISP=
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
SHELL=/bin/bash
|
||||
@@ -197,7 +189,7 @@ MAKEFLAGS=
|
||||
HISTSIZE=1000
|
||||
SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/83465594_02bf_4b80_a6ef_1d361b15e756
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
@@ -208,14 +200,14 @@ IMSETTINGS_MODULE=none
|
||||
USER=ICer
|
||||
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
|
||||
LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
GNOME_TERMINAL_SERVICE=:1.106
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
MAKE_TERMOUT=/dev/pts/0
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SNPSLMD_LICENSE_FILE=27000@IC_EDA
|
||||
USERNAME=ICer
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3198,unix/unix:/tmp/.ICE-unix/3198
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3690,unix/unix:/tmp/.ICE-unix/3690
|
||||
MAKELEVEL=1
|
||||
MFLAGS=
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
@@ -229,7 +221,7 @@ CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
XDG_SESSION_TYPE=x11
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
PWD=/home/ICer/ic_prjs/mc/sim
|
||||
PWD=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
XMODIFIERS=@im=none
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SYS_PROG_NAME=verdi
|
||||
@@ -246,7 +238,6 @@ XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
HISTCONTROL=ignoredups
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
HOME=/home/ICer
|
||||
XDG_SEAT=seat0
|
||||
RISCV=/home/Riscv_Tools
|
||||
@@ -263,9 +254,9 @@ DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
MAKE_TERMERR=/dev/pts/0
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-LHuevZztAf,guid=55ddfa7976bc586b8b8ee131689354d9
|
||||
NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc
|
||||
SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
@@ -282,7 +273,7 @@ LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JizYR8/database
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JLN4Y3/database
|
||||
COLORTERM=truecolor
|
||||
PS_HWPC=OFF
|
||||
NOVAS_LC_ALL=C
|
||||
@@ -305,7 +296,7 @@ SIGNAL_BASED_BA=0
|
||||
SYNOPSYS_SIM=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DISABLE_LIBRARY_MAP_CHECK=1
|
||||
SNPS_SIM_DEFAULT_GUI=verdi
|
||||
FSDB_FILE=/home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
FSDB_FILE=/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
VCS_UCLI_STDIN_BLOCKING=1
|
||||
FSDB_VHDL_PROTECTED=1
|
||||
FSDB_RD_IR_ENABLE=1
|
||||
@@ -317,474 +308,120 @@ VCS_EXEC_DONE=1
|
||||
VCS_STOP_SAFE=1
|
||||
DVE_SIM_SELECT_LOOP=on
|
||||
Runtime command line arguments:
|
||||
argv[0]=/home/ICer/ic_prjs/mc/sim/simv
|
||||
argv[0]=/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv
|
||||
argv[1]=-sml=verdi
|
||||
argv[2]=+fsdb+gate=off
|
||||
argv[3]=-ucli2Proc
|
||||
argv[4]=-ucli
|
||||
argv[5]=-l
|
||||
argv[6]=/home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
326 profile - 100
|
||||
CPU/Mem usage: 0.000 sys, 0.050 user, 236.30M mem
|
||||
327 Tue Aug 5 21:54:29 2025
|
||||
328 pliAppInit
|
||||
329 ndpGetenv(FSDB_FILE): /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
330 ndpGetenv(FSDB_SVA_STATUS): 1
|
||||
331 ndpGetenv(FSDB_VHDL_PROTECTED): 1
|
||||
332 FSDB_GATE & FSDB_RTL is disabled.
|
||||
333 Enable Parallel Dumping.
|
||||
334 pliAppMiscSet: New Sim Round
|
||||
335 pliEntryInit
|
||||
336 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
337 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
338 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
339 sps_tcl_fsdbDumpfile_main at 0
|
||||
340 argv[0]: /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
341 *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
|
||||
342 compile option from '/home/ICer/ic_prjs/mc/sim/simv.daidir/vcs_rebuild'.
|
||||
343 "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
344 sps_tcl_fsdbDumpflush_vd_main
|
||||
345 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
346 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
347 sps_tcl_fsdbDumpvars_vd_main
|
||||
348 argv[0]: 0
|
||||
349 argv[1]: tb_rchannel.array2axi_rdata
|
||||
350 argv[2]: +all
|
||||
351 argv[3]: +trace_process
|
||||
352 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
353 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
354 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
|
||||
355 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 329.37M mem
|
||||
incr: 0.000 sys, 0.000 user, 2.20M mem
|
||||
accu: 0.000 sys, 0.000 user, 2.20M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 2.20M mem
|
||||
argv[6]=/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
317 profile - 100
|
||||
CPU/Mem usage: 0.030 sys, 0.110 user, 236.15M mem
|
||||
318 Wed Aug 6 22:32:55 2025
|
||||
319 pliAppInit
|
||||
320 ndpGetenv(FSDB_FILE): /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
321 ndpGetenv(FSDB_SVA_STATUS): 1
|
||||
322 ndpGetenv(FSDB_VHDL_PROTECTED): 1
|
||||
323 FSDB_GATE & FSDB_RTL is disabled.
|
||||
324 Enable Parallel Dumping.
|
||||
325 pliAppMiscSet: New Sim Round
|
||||
326 pliEntryInit
|
||||
327 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
328 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
329 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
330 sps_tcl_fsdbDumpfile_main at 0
|
||||
331 argv[0]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
332 *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
|
||||
333 compile option from '/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/vcs_rebuild'.
|
||||
334 "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
335 sps_tcl_fsdbDumpflush_vd_main
|
||||
336 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
337 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
338 sps_tcl_fsdbDumpvarsByFile_vd_main at 0 : N/A(0)
|
||||
339 *Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
|
||||
340 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
341 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
342 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 329.39M mem
|
||||
incr: 0.000 sys, 0.000 user, 2.65M mem
|
||||
accu: 0.000 sys, 0.000 user, 2.65M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 2.65M mem
|
||||
|
||||
Count usage: 1 var, 1 idcode, 1 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
356 Tue Aug 5 21:54:30 2025
|
||||
357 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
incr: 44 var, 44 idcode, 44 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu incr: 44 var, 44 idcode, 44 callback
|
||||
343 Wed Aug 6 22:32:57 2025
|
||||
344 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 330.44M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.26M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 1 var, 1 idcode, 1 callback
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
358 Tue Aug 5 21:54:30 2025
|
||||
359 sps_tcl_fsdbDumpvars_vd_main
|
||||
360 argv[0]: 0
|
||||
361 argv[1]: tb_rchannel.array2axi_rdata_valid
|
||||
362 argv[2]: +all
|
||||
363 argv[3]: +trace_process
|
||||
364 *Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
|
||||
365 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
345 Wed Aug 6 22:32:57 2025
|
||||
346 *Verdi* : End of dumping.
|
||||
347 fsdbDumpvarsByFile: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 330.44M mem
|
||||
incr: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 3.70M mem
|
||||
|
||||
Count usage: 2 var, 2 idcode, 2 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
366 Tue Aug 5 21:54:30 2025
|
||||
367 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
incr: 44 var, 44 idcode, 44 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu incr: 44 var, 44 idcode, 44 callback
|
||||
348 Wed Aug 6 22:32:57 2025
|
||||
349 sps_tcl_fsdbDumpflush_vd_main
|
||||
350 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
351 sps_tcl_fsdbDumpflush_vd_main
|
||||
352 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
353 sps_tcl_fsdbDumpflush_vd_main
|
||||
354 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
355 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_rchannel.v(98)
|
||||
356 argv[0]: (tb.fsdb)
|
||||
357 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_rchannel.v(99)
|
||||
358 argv[0]: (0)
|
||||
359 argv[1]: (handle) tb_rchannel
|
||||
360 argv[2]: (+all)
|
||||
361 *Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
362 *Verdi* : Enable +all dumping.
|
||||
363 *Verdi* : End of traversing.
|
||||
364 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.110 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 2 var, 2 idcode, 2 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
368 Tue Aug 5 21:54:30 2025
|
||||
369 sps_tcl_fsdbDumpvars_vd_main
|
||||
370 argv[0]: 0
|
||||
371 argv[1]: tb_rchannel.axi_s_araddr
|
||||
372 argv[2]: +all
|
||||
373 argv[3]: +trace_process
|
||||
374 *Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
|
||||
375 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 3 var, 3 idcode, 3 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
376 Tue Aug 5 21:54:30 2025
|
||||
377 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 3 var, 3 idcode, 3 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
378 Tue Aug 5 21:54:30 2025
|
||||
379 sps_tcl_fsdbDumpvars_vd_main
|
||||
380 argv[0]: 0
|
||||
381 argv[1]: tb_rchannel.axi_s_arlen
|
||||
382 argv[2]: +all
|
||||
383 argv[3]: +trace_process
|
||||
384 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
|
||||
385 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 4 var, 4 idcode, 4 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
386 Tue Aug 5 21:54:30 2025
|
||||
387 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 4 var, 4 idcode, 4 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
388 Tue Aug 5 21:54:30 2025
|
||||
389 sps_tcl_fsdbDumpvars_vd_main
|
||||
390 argv[0]: 0
|
||||
391 argv[1]: tb_rchannel.axi_s_arready
|
||||
392 argv[2]: +all
|
||||
393 argv[3]: +trace_process
|
||||
394 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
|
||||
395 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 5 var, 5 idcode, 5 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
396 Tue Aug 5 21:54:30 2025
|
||||
397 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 5 var, 5 idcode, 5 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
398 Tue Aug 5 21:54:30 2025
|
||||
399 sps_tcl_fsdbDumpvars_vd_main
|
||||
400 argv[0]: 0
|
||||
401 argv[1]: tb_rchannel.axi_s_arvalid
|
||||
402 argv[2]: +all
|
||||
403 argv[3]: +trace_process
|
||||
404 *Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
|
||||
405 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 6 var, 6 idcode, 6 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
406 Tue Aug 5 21:54:30 2025
|
||||
407 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.060 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 6 var, 6 idcode, 6 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
408 Tue Aug 5 21:54:30 2025
|
||||
409 sps_tcl_fsdbDumpvars_vd_main
|
||||
410 argv[0]: 0
|
||||
411 argv[1]: tb_rchannel.axi_s_rdata
|
||||
412 argv[2]: +all
|
||||
413 argv[3]: +trace_process
|
||||
414 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
|
||||
415 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.010 user, 0.00M mem
|
||||
|
||||
Count usage: 7 var, 7 idcode, 7 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
416 Tue Aug 5 21:54:30 2025
|
||||
417 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.010 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 7 var, 7 idcode, 7 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
418 Tue Aug 5 21:54:30 2025
|
||||
419 sps_tcl_fsdbDumpvars_vd_main
|
||||
420 argv[0]: 0
|
||||
421 argv[1]: tb_rchannel.axi_s_rlast
|
||||
422 argv[2]: +all
|
||||
423 argv[3]: +trace_process
|
||||
424 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
|
||||
425 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 8 var, 8 idcode, 8 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
426 Tue Aug 5 21:54:30 2025
|
||||
427 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.100 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 8 var, 8 idcode, 8 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
428 Tue Aug 5 21:54:30 2025
|
||||
429 sps_tcl_fsdbDumpvars_vd_main
|
||||
430 argv[0]: 0
|
||||
431 argv[1]: tb_rchannel.axi_s_rvalid
|
||||
432 argv[2]: +all
|
||||
433 argv[3]: +trace_process
|
||||
434 *Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
|
||||
435 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
Count usage: 159 var, 85 idcode, 72 callback
|
||||
incr: 115 var, 41 idcode, 28 callback
|
||||
accu: 115 var, 41 idcode, 28 callback
|
||||
accu incr: 115 var, 41 idcode, 28 callback
|
||||
365 Wed Aug 6 22:32:59 2025
|
||||
366 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.130 sys, 0.110 user, 333.21M mem
|
||||
incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 1.05M mem
|
||||
accu incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 9 var, 9 idcode, 9 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
436 Tue Aug 5 21:54:30 2025
|
||||
437 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 9 var, 9 idcode, 9 callback
|
||||
Count usage: 159 var, 85 idcode, 72 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu: 115 var, 41 idcode, 28 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
438 Tue Aug 5 21:54:30 2025
|
||||
439 sps_tcl_fsdbDumpvars_vd_main
|
||||
440 argv[0]: 0
|
||||
441 argv[1]: tb_rchannel.clk
|
||||
442 argv[2]: +all
|
||||
443 argv[3]: +trace_process
|
||||
444 *Verdi* : Dumping the signal (tb_rchannel.clk).
|
||||
445 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 10 var, 10 idcode, 10 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
446 Tue Aug 5 21:54:30 2025
|
||||
447 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 10 var, 10 idcode, 10 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
448 Tue Aug 5 21:54:30 2025
|
||||
449 sps_tcl_fsdbDumpvars_vd_main
|
||||
450 argv[0]: 0
|
||||
451 argv[1]: tb_rchannel.rframe_data
|
||||
452 argv[2]: +all
|
||||
453 argv[3]: +trace_process
|
||||
454 *Verdi* : Dumping the signal (tb_rchannel.rframe_data).
|
||||
455 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 11 var, 11 idcode, 11 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
456 Tue Aug 5 21:54:30 2025
|
||||
457 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 11 var, 11 idcode, 11 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
458 Tue Aug 5 21:54:30 2025
|
||||
459 sps_tcl_fsdbDumpvars_vd_main
|
||||
460 argv[0]: 0
|
||||
461 argv[1]: tb_rchannel.rframe_ready
|
||||
462 argv[2]: +all
|
||||
463 argv[3]: +trace_process
|
||||
464 *Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
|
||||
465 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 12 var, 12 idcode, 12 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
466 Tue Aug 5 21:54:30 2025
|
||||
467 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 12 var, 12 idcode, 12 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
468 Tue Aug 5 21:54:30 2025
|
||||
469 sps_tcl_fsdbDumpvars_vd_main
|
||||
470 argv[0]: 0
|
||||
471 argv[1]: tb_rchannel.rframe_valid
|
||||
472 argv[2]: +all
|
||||
473 argv[3]: +trace_process
|
||||
474 *Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
|
||||
475 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 13 var, 13 idcode, 13 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
476 Tue Aug 5 21:54:30 2025
|
||||
477 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 13 var, 13 idcode, 13 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
478 Tue Aug 5 21:54:30 2025
|
||||
479 sps_tcl_fsdbDumpvars_vd_main
|
||||
480 argv[0]: 0
|
||||
481 argv[1]: tb_rchannel.rst_n
|
||||
482 argv[2]: +all
|
||||
483 argv[3]: +trace_process
|
||||
484 *Verdi* : Dumping the signal (tb_rchannel.rst_n).
|
||||
485 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 14 var, 14 idcode, 14 callback
|
||||
incr: 1 var, 1 idcode, 1 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 1 var, 1 idcode, 1 callback
|
||||
486 Tue Aug 5 21:54:30 2025
|
||||
487 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.070 user, 330.42M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 14 var, 14 idcode, 14 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 1 var, 1 idcode, 1 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
488 Tue Aug 5 21:54:30 2025
|
||||
489 sps_tcl_fsdbDumpflush_vd_main
|
||||
490 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
491 sps_tcl_fsdbDumpflush_vd_main
|
||||
492 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
493 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_rchannel.v(98)
|
||||
494 argv[0]: (tb.fsdb)
|
||||
495 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_rchannel.v(99)
|
||||
496 argv[0]: (0)
|
||||
497 argv[1]: (handle) tb_rchannel
|
||||
498 argv[2]: (+all)
|
||||
499 *Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
500 *Verdi* : Enable +all dumping.
|
||||
501 *Verdi* : End of traversing.
|
||||
502 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.070 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.06M mem
|
||||
|
||||
Count usage: 129 var, 85 idcode, 72 callback
|
||||
incr: 115 var, 71 idcode, 58 callback
|
||||
accu: 115 var, 71 idcode, 58 callback
|
||||
accu incr: 115 var, 71 idcode, 58 callback
|
||||
503 Tue Aug 5 21:54:32 2025
|
||||
504 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.070 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.06M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 129 var, 85 idcode, 72 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 115 var, 71 idcode, 58 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
505 Tue Aug 5 21:54:32 2025
|
||||
506 sps_tcl_fsdbDumpflush_vd_main
|
||||
507 *Verdi* : Flush all FSDB Files at 365,000 ps.
|
||||
508 End of simulation at 365000
|
||||
509 Tue Aug 5 22:01:50 2025
|
||||
510 Begin FSDB profile info:
|
||||
511 FSDB Writer : bc1(186) bcn(270) mtf/stf(0/4)
|
||||
FSDB Writer elapsed time : flush(0.010457) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
367 Wed Aug 6 22:32:59 2025
|
||||
368 sps_tcl_fsdbDumpflush_vd_main
|
||||
369 *Verdi* : Flush all FSDB Files at 365,000 ps.
|
||||
370 End of simulation at 365000
|
||||
371 Wed Aug 6 22:41:15 2025
|
||||
372 Begin FSDB profile info:
|
||||
373 FSDB Writer : bc1(202) bcn(288) mtf/stf(0/5)
|
||||
FSDB Writer elapsed time : flush(0.014706) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
512 End FSDB profile info
|
||||
513 Parallel profile - Flush:22 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
|
||||
514 ProduceTime:0.212615372 ConsumerTime:0.000000000 Buffer:64MB
|
||||
515 SimExit
|
||||
516 Sim process exit
|
||||
374 End FSDB profile info
|
||||
375 Parallel profile - Flush:10 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
|
||||
376 ProduceTime:0.262536335 ConsumerTime:0.000000000 Buffer:64MB
|
||||
377 SimExit
|
||||
378 Sim process exit
|
||||
|
||||
@@ -1,13 +1,10 @@
|
||||
0
|
||||
39
|
||||
+cli+4
|
||||
33
|
||||
+itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
+memcbk
|
||||
+v2k
|
||||
+vc
|
||||
+vcsd1
|
||||
+vpi
|
||||
+vpi
|
||||
-Mamsrun=
|
||||
-Masflags=
|
||||
-Mcc=gcc
|
||||
@@ -25,22 +22,19 @@
|
||||
-Mvcsaceobjs=
|
||||
-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
-P
|
||||
-Xcbug=0x1
|
||||
-Xvcs_run_simv=1
|
||||
-debug=3
|
||||
-debug_access+all
|
||||
-f filelist.f
|
||||
-fsdb
|
||||
-full64
|
||||
-gen_obj
|
||||
-o simv
|
||||
-picarchive
|
||||
-sverilog
|
||||
-timescale=1ns/1ps
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
90
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/mc/sim
|
||||
88
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
XMODIFIERS=@im=ibus
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
XDG_VTNR=1
|
||||
@@ -52,7 +46,7 @@ XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JizYR8/database
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JLN4Y3/database
|
||||
WINDOWPATH=1
|
||||
VTE_VERSION=5204
|
||||
VMR_MODE_FLAG=64
|
||||
@@ -69,11 +63,11 @@ UNAME=/bin/uname
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
SSH_AGENT_PID=3332
|
||||
SSH_AGENT_PID=3826
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3198,unix/unix:/tmp/.ICE-unix/3198
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3690,unix/unix:/tmp/.ICE-unix/3690
|
||||
SCRNAME=vcs
|
||||
SCRIPT_NAME=vcs
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
@@ -95,8 +89,8 @@ MGC_HOME=/home/mentor/
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
MFLAGS=
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
MAKE_TERMOUT=/dev/pts/0
|
||||
MAKE_TERMERR=/dev/pts/0
|
||||
MAKELEVEL=1
|
||||
MAKEFLAGS=
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
@@ -113,8 +107,8 @@ IMSETTINGS_MODULE=none
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
HISTCONTROL=ignoredups
|
||||
GNOME_TERMINAL_SERVICE=:1.106
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/7d23cc48_b012_4cdb_8880_be742bbb5377
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/83465594_02bf_4b80_a6ef_1d361b15e756
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
@@ -122,9 +116,7 @@ GDMSESSION=gnome-classic
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHgGhBeuRa,guid=7d1e6d39d9cd21f19b7c928468920612
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-LHuevZztAf,guid=55ddfa7976bc586b8b8ee131689354d9
|
||||
COLORTERM=truecolor
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
CDSHOME=/home/cadence/IC617
|
||||
@@ -132,11 +124,11 @@ CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
CADHOME=/home/cadence
|
||||
0
|
||||
7
|
||||
1754401710 ../tb/tb_rchannel.v
|
||||
1754402050 ../rtl/rchannel.v
|
||||
1754372349 ../rtl/sync_fifo.v
|
||||
1754381818 ../rtl/sync_fifo_128_to_64.v
|
||||
1754401741 filelist.f
|
||||
1754471014 ../tb/tb_rchannel.v
|
||||
1754490726 ../rtl/rchannel.v
|
||||
1754471014 ../rtl/sync_fifo.v
|
||||
1754489537 ../rtl/sync_fifo_128_to_64.v
|
||||
1754489266 filelist.f
|
||||
1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
4
|
||||
@@ -144,5 +136,5 @@ CADHOME=/home/cadence
|
||||
1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
|
||||
1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
|
||||
1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
1754402058 simv.daidir
|
||||
1754490739 simv.daidir
|
||||
-1 partitionlib
|
||||
|
||||
Binary file not shown.
@@ -1,4 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1
|
||||
|
||||
@@ -3,8 +3,8 @@ bcid 0 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET
|
||||
bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU CALL_ARG_VAL,6,0 NOT AND AND RET
|
||||
bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND AND RET
|
||||
bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_EQU OR AND RET
|
||||
bcid 5 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU WIDTH,6 CALL_ARG_VAL,5,0 OPT_CONST,63 WIDTH,1 M_EQU OR AND RET
|
||||
bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 5 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND RET
|
||||
bcid 6 6 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 XOR WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,1 M_EQU AND RET
|
||||
bcid 7 7 WIDTH,3 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
bcid 8 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 PAD SUBTRACT OPT_CONST,8 WIDTH,1 M_EQU RET
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
O-2018.09-1_Full64
|
||||
Build Date = Oct 12 2018 20:38:10
|
||||
RedHat
|
||||
Compile Location: /home/ICer/ic_prjs/mc/sim
|
||||
Compile Location: /home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -5,5 +5,5 @@ PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_h3ehMU.xml.gz" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_9Anw8J.xml.gz" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
#!/bin/sh -h
|
||||
|
||||
FILE_PATH="/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch"
|
||||
FILE_PATH="/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch"
|
||||
lockfile="${FILE_PATH}"/lock
|
||||
|
||||
FSearch_lock_release() {
|
||||
@@ -28,17 +28,17 @@ if [ "${dir_name}" = "." ]; then
|
||||
cd $dir_name
|
||||
dir_name=`/bin/pwd`
|
||||
fi
|
||||
if [ -d "$dir_name"/../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../..
|
||||
if [ -d "$dir_name"/../../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../../..
|
||||
fi
|
||||
|
||||
if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
||||
trap FSearch_lock_release EXIT
|
||||
(
|
||||
flock 193
|
||||
create_fsearch_db_ctrl "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
create_fsearch_db_ctrl "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
exit 193
|
||||
) 193> "$lockfile"
|
||||
rstat=$?
|
||||
@@ -46,12 +46,12 @@ if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearc
|
||||
exit $rstat
|
||||
fi
|
||||
else
|
||||
"/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
"/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
elif [ -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
elif [ -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
|
||||
Binary file not shown.
@@ -1,4 +1,4 @@
|
||||
/home/ICer/ic_prjs/mc/rtl/rchannel.v
|
||||
/home/ICer/ic_prjs/mc/rtl/sync_fifo.v
|
||||
/home/ICer/ic_prjs/mc/rtl/sync_fifo_128_to_64.v
|
||||
/home/ICer/ic_prjs/mc/tb/tb_rchannel.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/rchannel.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo_128_to_64.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v
|
||||
|
||||
@@ -1 +1 @@
|
||||
~<7E>
|
||||
}<7D>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,15 +1,15 @@
|
||||
rc file Version 1.0
|
||||
|
||||
[Design]
|
||||
COMPILE_PATH=/home/ICer/ic_prjs/mc/sim
|
||||
COMPILE_PATH=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
SystemC=FALSE
|
||||
UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=tb_rchannel
|
||||
OPTION=-ssz -ssv -ssy
|
||||
ELAB_OPTION=-ssz -ssv -ssy
|
||||
OPTION=-ssv -ssy
|
||||
ELAB_OPTION=-ssv -ssy
|
||||
|
||||
[Value]
|
||||
WREALX=ffff534e50535f58
|
||||
|
||||
Binary file not shown.
@@ -1,4 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-debug' '-o' 'simv' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1
|
||||
vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
psSimBaseName simv
|
||||
psLogFileName NULL
|
||||
pDaiDir /home/ICer/ic_prjs/mc/sim/simv.daidir
|
||||
pDaiDir /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir
|
||||
destPath csrc/
|
||||
fSharedMaster 0
|
||||
fHsimPCSharedLibSpecified 0
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,6 +1,3 @@
|
||||
vcselab_misc_midd.db 445
|
||||
vcselab_misc_mnmn.db 24
|
||||
vcselab_misc_hsim_name.db 181
|
||||
vcselab_misc_midd.db 445
|
||||
vcselab_misc_mnmn.db 24
|
||||
vcselab_misc_hsim_name.db 181
|
||||
|
||||
Binary file not shown.
BIN
sim/tb.fsdb
BIN
sim/tb.fsdb
Binary file not shown.
@@ -1,6 +1,6 @@
|
||||
synUtils::getArch
|
||||
loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd
|
||||
config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/sim/inter.fsdb} ;fsdbDumpflush ;
|
||||
config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb} ;fsdbDumpflush ;
|
||||
sps_interactive
|
||||
ucliCore::getToolPID
|
||||
ucliCore::getToolPID
|
||||
@@ -8,7 +8,7 @@ if {[catch {ucliCore::setFocus tool}]} {}
|
||||
puts $ucliCore::nativeUcliMode
|
||||
ucliCore::getToolTopPID
|
||||
pid
|
||||
synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.12621 }
|
||||
synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.26345 }
|
||||
if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024}
|
||||
info command stateVerdiChangeCB
|
||||
proc stateVerdiChangeCB args { if {$ucliGUI::state eq "terminated"} {puts "\nVERDI_SIM_Terminated\n";catch {setVerdiSimTerminated}}}
|
||||
@@ -25,7 +25,7 @@ save::getUserdefinedProcs
|
||||
info procs
|
||||
lappend ucliCore::resultTagsForVerdi <?special_verdi_begin?> <?special_verdi_end?>
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
|
||||
fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
|
||||
fsdbDumpflush
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
fsdbDumpflush
|
||||
@@ -34,7 +34,6 @@ synUtils::resolveSourceFilename ../tb/tb_rchannel.v
|
||||
puts $::ucliCore::cbug_active
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
checkpoint -list -all
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
stop
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
run
|
||||
|
||||
38
sim/vcs.log
38
sim/vcs.log
@@ -1,5 +1,5 @@
|
||||
Chronologic VCS (TM)
|
||||
Version O-2018.09-1_Full64 -- Wed Aug 6 15:11:28 2025
|
||||
Version O-2018.09-1_Full64 -- Wed Aug 6 22:32:17 2025
|
||||
Copyright (c) 1991-2018 by Synopsys Inc.
|
||||
ALL RIGHTS RESERVED
|
||||
|
||||
@@ -7,4 +7,38 @@ This program is proprietary and confidential information of Synopsys Inc.
|
||||
and may be used and disclosed only as authorized in a license agreement
|
||||
controlling such use and disclosure.
|
||||
|
||||
CPU time: .262 seconds to compile
|
||||
Parsing design file '../rtl/sync_fifo_128_to_64.v'
|
||||
Parsing design file '../rtl/sync_fifo.v'
|
||||
Parsing design file '../rtl/rchannel.v'
|
||||
Parsing design file '../tb/tb_rchannel.v'
|
||||
Top Level Modules:
|
||||
tb_rchannel
|
||||
TimeScale is 1 ns / 1 ps
|
||||
Starting vcs inline pass...
|
||||
1 module and 0 UDP read.
|
||||
recompiling module tb_rchannel
|
||||
make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
||||
if [ -x ../simv ]; then chmod -x ../simv; fi
|
||||
g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _25796_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
../simv up to date
|
||||
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* : Create FSDB file 'tb.fsdb'
|
||||
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
*Verdi* : Enable +all dumping.
|
||||
*Verdi* : End of traversing.
|
||||
$finish called from file "../tb/tb_rchannel.v", line 64.
|
||||
$finish at simulation time 365000
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 365000 ps
|
||||
CPU Time: 0.480 seconds; Data structure size: 0.0Mb
|
||||
Wed Aug 6 22:32:19 2025
|
||||
CPU time: .521 seconds to compile + .480 seconds to elab + .391 seconds to link + .525 seconds in simulation
|
||||
|
||||
@@ -7,10 +7,7 @@ Command arguments:
|
||||
../rtl/rchannel.v
|
||||
../tb/tb_rchannel.v
|
||||
|
||||
|
||||
*Error* non-constant instance parameter
|
||||
"../rtl/sync_fifo_128_to_64.v", 5:
|
||||
Highest level modules:
|
||||
tb_rchannel
|
||||
|
||||
Total 1 error(s), 0 warning(s)
|
||||
Total 0 error(s), 0 warning(s)
|
||||
|
||||
@@ -10,9 +10,3 @@ All other use, reproduction, or distribution of this software is strictly prohib
|
||||
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
|
||||
@@ -15,12 +15,12 @@ ConstrViewShow = 0
|
||||
InherViewShow = 0
|
||||
FSDBMsgShow = 0
|
||||
AnnotationShow = 0
|
||||
Console = TRUE
|
||||
Console = FALSE
|
||||
powerDumped = 0
|
||||
[hb]
|
||||
postSimFile = /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
syncTime = 170000
|
||||
viewport = 0 27 1918 778 0 0 127 798
|
||||
postSimFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
syncTime = 90000
|
||||
viewport = 0 20 1914 774 0 0 265 1912
|
||||
activeNode = "tb_rchannel"
|
||||
activeScope = "tb_rchannel"
|
||||
activeFile = "../tb/tb_rchannel.v"
|
||||
@@ -50,19 +50,19 @@ sdfCheckUndef = FALSE
|
||||
simFlow = FALSE
|
||||
[hb.design]
|
||||
importCmd = "-f" "filelist.f"
|
||||
invokeDir = /home/ICer/ic_prjs/mc/sim
|
||||
invokeDir = /home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
[hb.sourceTab.1]
|
||||
scope = tb_rchannel
|
||||
File = /home/ICer/ic_prjs/mc/tb/tb_rchannel.v
|
||||
File = /home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v
|
||||
Line = 1
|
||||
[nMemoryManager]
|
||||
WaveformFile = /home/ICer/ic_prjs/mc/sim/inter.fsdb
|
||||
WaveformFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
UserActionNum = 0
|
||||
nMemWindowNum = 0
|
||||
[wave.0]
|
||||
viewPort = 0 27 1293 439 181 244
|
||||
viewPort = 0 27 1914 615 285 195
|
||||
primaryWindow = TRUE
|
||||
SessionFile = /home/ICer/ic_prjs/mc/sim/verdiLog/novas_autosave.ses.wave.0
|
||||
SessionFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/novas_autosave.ses.wave.0
|
||||
displayGrid = FALSE
|
||||
hierarchicalName = FALSE
|
||||
snap = TRUE
|
||||
|
||||
File diff suppressed because one or more lines are too long
Binary file not shown.
|
Before Width: | Height: | Size: 143 KiB After Width: | Height: | Size: 121 KiB |
@@ -2,11 +2,11 @@ Magic 271485
|
||||
Revision Verdi_O-2018.09-SP2
|
||||
|
||||
; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
|
||||
viewPort 0 27 1293 439 181 244
|
||||
viewPort 0 27 1914 615 285 195
|
||||
|
||||
; File list:
|
||||
; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
|
||||
openDirFile -d / "" "/home/ICer/ic_prjs/mc/sim/inter.fsdb"
|
||||
openDirFile -d / "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
|
||||
; file time scale:
|
||||
; fileTimeScale ### s|ms|us|ns|ps
|
||||
@@ -16,14 +16,14 @@ signalSpacing 5
|
||||
|
||||
; windowTimeUnit is used for zoom, cursor & marker
|
||||
; waveform viewport range
|
||||
zoom 0.000000 301138.907620
|
||||
cursor 170000.000000
|
||||
zoom 0.000000 659986.290231
|
||||
cursor 90000.000000
|
||||
marker 0.000000
|
||||
|
||||
; user define markers
|
||||
; userMarker time_pos marker_name color linestyle
|
||||
; visible top row signal index
|
||||
top 0
|
||||
top 16
|
||||
; marker line index
|
||||
markerPos 44
|
||||
|
||||
@@ -46,7 +46,7 @@ curSTATUS ByChange
|
||||
|
||||
|
||||
addGroup "G1"
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/sim/inter.fsdb"
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arcaddr[5:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arlen[7:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arraddr[15:0]
|
||||
@@ -95,12 +95,13 @@ addGroup "G2"
|
||||
|
||||
; getSignalForm Scope Hierarchy Status
|
||||
; active file of getSignalForm
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/sim/inter.fsdb"
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
|
||||
GETSIGNALFORM_SCOPE_HIERARCHY_BEGIN
|
||||
getSignalForm close
|
||||
|
||||
"/tb_rchannel"
|
||||
"/tb_rchannel/u_rchannel"
|
||||
|
||||
SCOPE_LIST_BEGIN
|
||||
"/tb_rchannel"
|
||||
|
||||
@@ -1,30 +1,18 @@
|
||||
Invoking simulator...
|
||||
|
||||
Verdi>simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
|
||||
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
*Verdi* : Enable RPC Server(12621)
|
||||
*Verdi* : Enable RPC Server(26345)
|
||||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
|
||||
Verdi>fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
|
||||
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.clk).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_data).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rst_n).
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
|
||||
Verdi>fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
|
||||
*Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
|
||||
*Verdi* : End of dumping.
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
Verdi>run
|
||||
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
@@ -36,6 +24,6 @@ Simulation complete, time is 365000 ps.
|
||||
tb_rchannel.v, 1 : module tb_rchannel;
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 365000 ps
|
||||
CPU Time: 0.200 seconds; Data structure size: 0.0Mb
|
||||
Tue Aug 5 22:01:50 2025
|
||||
CPU Time: 0.250 seconds; Data structure size: 0.0Mb
|
||||
Wed Aug 6 22:41:15 2025
|
||||
debExit
|
||||
|
||||
Binary file not shown.
@@ -1,36 +1,36 @@
|
||||
Command: /home/ICer/ic_prjs/mc/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
Command: /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
|
||||
|
||||
ucli% synUtils::getArch
|
||||
linux64
|
||||
ucli% loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd
|
||||
LoadFSDBDumpCmd success
|
||||
ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/sim/inter.fsdb} ;fsdbDumpflush ;
|
||||
ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb} ;fsdbDumpflush ;
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/sim/inter.fsdb'
|
||||
*Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
|
||||
ucli% sps_interactive
|
||||
*Verdi* : Enable RPC Server(12621)
|
||||
*Verdi* : Enable RPC Server(26345)
|
||||
|
||||
ucli% ucliCore::getToolPID
|
||||
12621
|
||||
26345
|
||||
ucli% ucliCore::getToolPID
|
||||
12621
|
||||
26345
|
||||
ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
|
||||
ucli% puts $ucliCore::nativeUcliMode
|
||||
0
|
||||
|
||||
ucli% ucliCore::getToolTopPID
|
||||
12621
|
||||
26345
|
||||
ucli% pid
|
||||
12635
|
||||
ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.12621 }
|
||||
26359
|
||||
ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.26345 }
|
||||
|
||||
ucli% if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024}
|
||||
1024
|
||||
@@ -64,21 +64,10 @@ ucli% lappend ucliCore::resultTagsForVerdi <?special_verdi_begin?> <?special_ver
|
||||
<?special_verdi_begin?> <?special_verdi_end?>
|
||||
ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
|
||||
ucli% fsdbDumpvars 0 "tb_rchannel.array2axi_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.array2axi_rdata_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_araddr" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arlen" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_arvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rdata" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rlast" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.axi_s_rvalid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.clk" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_data" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_ready" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rframe_valid" +all +trace_process;fsdbDumpvars 0 "tb_rchannel.rst_n" +all +trace_process
|
||||
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.array2axi_rdata_valid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_araddr).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arlen).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arready).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_arvalid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rdata).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rlast).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.axi_s_rvalid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.clk).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_data).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_ready).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rframe_valid).
|
||||
*Verdi* : Dumping the signal (tb_rchannel.rst_n).
|
||||
ucli% fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
|
||||
*Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
|
||||
*Verdi* : End of dumping.
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
|
||||
ucli% fsdbDumpflush
|
||||
*Verdi* : Flush all FSDB Files at 0 ps.
|
||||
@@ -103,10 +92,10 @@ hasTB: 0
|
||||
inputFilename:
|
||||
keyFilename: ucli.key
|
||||
line: 1
|
||||
logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
macroIndex: -1
|
||||
macroOffset: -1
|
||||
pid: 12621
|
||||
pid: 26345
|
||||
scope: tb_rchannel
|
||||
startCol: 0
|
||||
state: stopped
|
||||
@@ -124,8 +113,6 @@ ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
|
||||
ucli% checkpoint -list -all
|
||||
There are no checkpoints present.
|
||||
ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
|
||||
ucli% stop
|
||||
No stop points are set
|
||||
ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
@@ -142,7 +129,7 @@ tb_rchannel.v, 1 : module tb_rchannel;
|
||||
ucli% synEnv::hasFataled
|
||||
0
|
||||
ucli% ucliCore::getToolPID
|
||||
12621
|
||||
26345
|
||||
ucli% save::getUserdefinedProcs
|
||||
::stateVerdiChangeCB ::LoadFSDBDumpCmd
|
||||
ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
@@ -165,10 +152,10 @@ hasTB: 0
|
||||
inputFilename:
|
||||
keyFilename: ucli.key
|
||||
line: 1
|
||||
logFilename: /home/ICer/ic_prjs/mc/sim/verdiLog/sim.log
|
||||
logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
macroIndex: -1
|
||||
macroOffset: -1
|
||||
pid: 12621
|
||||
pid: 26345
|
||||
scope: tb_rchannel
|
||||
startCol: 0
|
||||
state: stopped
|
||||
@@ -195,8 +182,8 @@ ucli% if {[catch {ucliCore::setFocus tool}]} {}
|
||||
ucli% finish; quit
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 365000 ps
|
||||
CPU Time: 0.200 seconds; Data structure size: 0.0Mb
|
||||
Tue Aug 5 22:01:50 2025
|
||||
CPU Time: 0.250 seconds; Data structure size: 0.0Mb
|
||||
Wed Aug 6 22:41:15 2025
|
||||
|
||||
VERDI_SIM_Terminated
|
||||
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -f filelist.f -ssf tb.fsdb
|
||||
uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64)
|
||||
au time 747.691216 57.029531 29.788219 delta 619401216 619401216 total 1044484096 1044484096
|
||||
au time 532.936489 24.438809 15.829228 delta 612864000 612864000 total 1037946880 1037946880
|
||||
|
||||
@@ -1,88 +1,8 @@
|
||||
debImport "-f" "filelist.f"
|
||||
debLoadSimResult /home/ICer/ic_prjs/mc/sim/tb.fsdb
|
||||
debLoadSimResult /home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb
|
||||
wvCreateWindow
|
||||
wvGetSignalOpen -win $_nWave2
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel"
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvAddSignal -win $_nWave2 -clear
|
||||
wvAddSignal -win $_nWave2 -group {"G1" \
|
||||
{/tb_rchannel/array2axi_rdata\[127:0\]} \
|
||||
{/tb_rchannel/array2axi_rdata_valid} \
|
||||
{/tb_rchannel/axi_s_araddr\[25:0\]} \
|
||||
{/tb_rchannel/axi_s_arlen\[7:0\]} \
|
||||
{/tb_rchannel/axi_s_arready} \
|
||||
{/tb_rchannel/axi_s_arvalid} \
|
||||
{/tb_rchannel/axi_s_rdata\[63:0\]} \
|
||||
{/tb_rchannel/axi_s_rlast} \
|
||||
{/tb_rchannel/axi_s_rvalid} \
|
||||
{/tb_rchannel/clk} \
|
||||
{/tb_rchannel/rframe_data\[159:0\]} \
|
||||
{/tb_rchannel/rframe_ready} \
|
||||
{/tb_rchannel/rframe_valid} \
|
||||
{/tb_rchannel/rst_n} \
|
||||
}
|
||||
wvAddSignal -win $_nWave2 -group {"G2" \
|
||||
}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvAddSignal -win $_nWave2 -clear
|
||||
wvAddSignal -win $_nWave2 -group {"G1" \
|
||||
{/tb_rchannel/array2axi_rdata\[127:0\]} \
|
||||
{/tb_rchannel/array2axi_rdata_valid} \
|
||||
{/tb_rchannel/axi_s_araddr\[25:0\]} \
|
||||
{/tb_rchannel/axi_s_arlen\[7:0\]} \
|
||||
{/tb_rchannel/axi_s_arready} \
|
||||
{/tb_rchannel/axi_s_arvalid} \
|
||||
{/tb_rchannel/axi_s_rdata\[63:0\]} \
|
||||
{/tb_rchannel/axi_s_rlast} \
|
||||
{/tb_rchannel/axi_s_rvalid} \
|
||||
{/tb_rchannel/clk} \
|
||||
{/tb_rchannel/rframe_data\[159:0\]} \
|
||||
{/tb_rchannel/rframe_ready} \
|
||||
{/tb_rchannel/rframe_valid} \
|
||||
{/tb_rchannel/rst_n} \
|
||||
}
|
||||
wvAddSignal -win $_nWave2 -group {"G2" \
|
||||
}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 14)}
|
||||
wvGetSignalClose -win $_nWave2
|
||||
srcTBInvokeSim
|
||||
srcTBRunSim
|
||||
verdiDockWidgetSetCurTab -dock windowDock_nWave_2
|
||||
verdiDockWidgetMaximize -dock windowDock_nWave_2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
verdiDockWidgetRestore -dock windowDock_nWave_2
|
||||
wvSetCursor -win $_nWave2 124423.457480 -snap {("G1" 1)}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 8 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 7 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 9 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 8 )}
|
||||
srcTBRunSim
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 9 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 2 )}
|
||||
wvGetSignalOpen -win $_nWave2
|
||||
wvGetSignalClose -win $_nWave2
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 )}
|
||||
wvCut -win $_nWave2
|
||||
wvSetPosition -win $_nWave2 {("G1" 0)}
|
||||
wvGetSignalOpen -win $_nWave2
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel"
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel"
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel/u_rchannel"
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
@@ -206,6 +126,13 @@ wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
@@ -221,18 +148,38 @@ wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 2182.373767 -snap {("G1" 16)}
|
||||
srcTBInvokeSim
|
||||
srcTBRunSim
|
||||
verdiDockWidgetSetCurTab -dock windowDock_nWave_2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
verdiDockWidgetMaximize -dock windowDock_nWave_2
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 24 )}
|
||||
wvSetCursor -win $_nWave2 169335.416349 -snap {("G1" 18)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
@@ -247,6 +194,27 @@ wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 22
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 20 )}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
@@ -255,29 +223,12 @@ wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSetCursor -win $_nWave2 115310.104685 -snap {("G1" 14)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
@@ -307,8 +258,10 @@ wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSetCursor -win $_nWave2 129149.284254 -snap {("G1" 43)}
|
||||
wvSetCursor -win $_nWave2 93313.905930 -snap {("G1" 43)}
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
@@ -316,31 +269,48 @@ wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 44 )}
|
||||
wvExpandBus -win $_nWave2 {("G1" 44)}
|
||||
wvScrollUp -win $_nWave2 118
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 44 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvCollapseBus -win $_nWave2 {("G1" 44)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
verdiDockWidgetRestore -dock windowDock_nWave_2
|
||||
wvSetCursor -win $_nWave2 46874.026295 -snap {("G1" 39)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSetCursor -win $_nWave2 191246.027283 -snap {("G1" 3)}
|
||||
wvSetCursor -win $_nWave2 235776.352263 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 283119.118821 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 305149.911179 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 353430.158263 -snap {("G1" 4)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
@@ -350,56 +320,6 @@ wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
@@ -413,6 +333,43 @@ wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 144372.000988 -snap {("G1" 37)}
|
||||
wvSetCursor -win $_nWave2 195464.689649 -snap {("G1" 40)}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 40 )}
|
||||
wvSetCursor -win $_nWave2 201089.572805 -snap {("G1" 40)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 20 )}
|
||||
wvSetCursor -win $_nWave2 61404.974446 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 63748.675761 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 82029.546016 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 101247.896797 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 117185.065737 -snap {("G1" 20)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
@@ -434,49 +391,6 @@ wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 9
|
||||
wvScrollUp -win $_nWave2 5
|
||||
wvScrollUp -win $_nWave2 5
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 18 )}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 14 )}
|
||||
wvSetCursor -win $_nWave2 119811.798162 -snap {("G1" 14)}
|
||||
wvSetCursor -win $_nWave2 169882.400379 -snap {("G1" 14)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 38 )}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
@@ -484,11 +398,13 @@ wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 19 )}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 17 )}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
@@ -505,6 +421,20 @@ wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
debExit
|
||||
|
||||
101
tb/tb_frame_arbiter.v
Normal file
101
tb/tb_frame_arbiter.v
Normal file
@@ -0,0 +1,101 @@
|
||||
module tb_frame_arbiter;
|
||||
reg clk;
|
||||
reg rst_n;
|
||||
reg [159:0] wframe_data;
|
||||
reg wframe_valid;
|
||||
wire wframe_ready;
|
||||
|
||||
reg [159:0] rframe_data;
|
||||
reg rframe_valid;
|
||||
wire rframe_ready;
|
||||
|
||||
wire [152:0] axi2array_frame_data;
|
||||
wire axi2array_frame_valid;
|
||||
reg axi2array_frame_ready;
|
||||
|
||||
reg mc_work_en;
|
||||
reg [1:0] axi_bus_rw_priority;
|
||||
|
||||
frame_arbiter u_frame_arbiter(
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.wframe_data (wframe_data),
|
||||
.wframe_valid (wframe_valid),
|
||||
.wframe_ready (wframe_ready),
|
||||
.rframe_data (rframe_data),
|
||||
.rframe_valid (rframe_valid),
|
||||
.rframe_ready (rframe_ready),
|
||||
.axi2array_frame_data(axi2array_frame_data),
|
||||
.axi2array_frame_valid(axi2array_frame_valid),
|
||||
.axi2array_frame_ready(axi2array_frame_ready),
|
||||
.mc_work_en(mc_work_en),
|
||||
.axi_bus_rw_priority(axi_bus_rw_priority)
|
||||
);
|
||||
|
||||
task wframe;
|
||||
input [159:0] wdata;
|
||||
begin
|
||||
@(posedge clk) begin
|
||||
wframe_data <= wdata;
|
||||
wframe_valid <= 1'b1;
|
||||
end
|
||||
#0.1;
|
||||
wait(wframe_ready);
|
||||
@(posedge clk) begin
|
||||
wframe_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task rframe;
|
||||
input [159:0] rdata;
|
||||
begin
|
||||
@(posedge clk) begin
|
||||
rframe_data <= rdata;
|
||||
rframe_valid <= 1'b1;
|
||||
end
|
||||
#0.1;
|
||||
wait(rframe_ready);
|
||||
@(posedge clk) begin
|
||||
rframe_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever begin
|
||||
#10; clk = ~clk;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
rst_n = 'd0;
|
||||
wframe_data = 'd0;
|
||||
wframe_valid = 'd0;
|
||||
rframe_data = 'd0;
|
||||
rframe_valid = 'd0;
|
||||
axi2array_frame_ready = 1'b1;
|
||||
mc_work_en = 1'b1;
|
||||
axi_bus_rw_priority = 2'b01;
|
||||
@(posedge clk) begin
|
||||
rst_n <= 1'b1;
|
||||
end
|
||||
wframe({152'd3,8'd5});
|
||||
wframe({152'd4,8'd5});
|
||||
wframe({152'd5,8'd5});
|
||||
rframe({152'd6,8'd1});
|
||||
fork
|
||||
wframe({152'd7,8'd1});
|
||||
rframe({152'd8,8'd1});
|
||||
join
|
||||
$fsdbDumpfile("tb.fsdb");
|
||||
$fsdbDumpvars(0,tb_frame_arbiter,"+all");
|
||||
#10
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user