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Finish top-module(axi_slave array_ctrl apb_cfg): 2025-08-13 16:39:12

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2025-08-13 16:39:12 +08:00
parent c84096d1f9
commit de5211af62
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rtl/axi_slv.v Normal file
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module axi_slv(
input clk,
input rst_n,
input axi_s_awvalid,
input [7:0] axi_s_awlen,
input [25:0] axi_s_awaddr,
output axi_s_awready,
input axi_s_wvalid,
input axi_s_wlast,
input [63:0] axi_s_wdata,
output axi_s_wready,
input axi_s_arvalid,
input [7:0] axi_s_arlen,
input [25:0] axi_s_araddr,
output axi_s_arready,
output axi_s_rvalid,
output axi_s_rlast,
output [63:0] axi_s_rdata,
output axi2array_frame_valid,
output [152:0] axi2array_frame_data,
input axi2array_frame_ready,
input array2axi_rdata_valid,
input [127:0] array2axi_rdata,
input [1:0] axi_bus_rw_priority,
input mc_work_en
);
wire wframe_valid;
wire [159:0] wframe_data;
wire wframe_ready;
wire rframe_valid;
wire [159:0] rframe_data;
wire rframe_ready;
wchannel u_wchannel(
.clk (clk),
.rst_n (rst_n),
.axi_s_awvalid (axi_s_awvalid),
.axi_s_awlen (axi_s_awlen),
.axi_s_awaddr (axi_s_awaddr),
.axi_s_awready (axi_s_awready),
.axi_s_wvalid (axi_s_wvalid),
.axi_s_wlast (axi_s_wlast),
.axi_s_wdata (axi_s_wdata),
.axi_s_wready (axi_s_wready),
.wframe_valid (wframe_valid),
.wframe_data (wframe_data),
.wframe_ready (wframe_ready)
);
rchannel u_rchannel(
.clk (clk),
.rst_n (rst_n),
.axi_s_arvalid (axi_s_rvalid),
.axi_s_arlen (axi_s_arlen),
.axi_s_araddr (axi_s_araddr),
.axi_s_arready (axi_s_arready),
.axi_s_rvalid (axi_s_rvalid),
.axi_s_rlast (axi_s_rlast),
.axi_s_rdata (axi_s_rdata),
.rframe_valid (rframe_valid),
.rframe_data (rframe_data),
.rframe_ready (rframe_ready),
.array2axi_rdata_valid(array2axi_rdata_valid),
.array2axi_rdata(array2axi_rdata)
);
frame_arbiter u_frame_arbiter(
.clk (clk),
.rst_n (rst_n),
.wframe_valid (wframe_valid),
.wframe_data (wframe_data),
.wframe_ready (wframe_ready),
.rframe_valid (rframe_valid),
.rframe_data (rframe_data),
.rframe_ready (rframe_ready),
.axi2array_frame_valid(axi2array_frame_valid),
.axi2array_frame_data (axi2array_frame_data),
.axi2array_frame_ready(axi2array_frame_ready),
.mc_work_en (mc_work_en),
.axi_bus_rw_priority(axi_bus_rw_priority)
);
endmodule