Finish top-module(axi_slave array_ctrl apb_cfg): 2025-08-13 16:39:12
This commit is contained in:
Core_kingdom
Binary file not shown.
@@ -1,34 +1,52 @@
|
||||
{
|
||||
"cycles_program_begin": 8954854280857,
|
||||
"cycles_program_begin": 437497044141,
|
||||
"PrevCompiledModules": {},
|
||||
"MlibObjs": {},
|
||||
"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir",
|
||||
"master_pid": 5573,
|
||||
"csrc": "csrc",
|
||||
"cwd": "/home/ICer/ic_prjs/mc/IC_PRJ/sim",
|
||||
"archive_dir": "archive.0",
|
||||
"default_output_dir": "csrc",
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"hostname": "IC_EDA",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc",
|
||||
"daidir": "simv.daidir"
|
||||
},
|
||||
"CompileStrategy": "fullobj",
|
||||
"CurCompileUdps": {},
|
||||
"perf": [
|
||||
{
|
||||
"stat": [
|
||||
"main",
|
||||
"entry",
|
||||
0.029060840606689453,
|
||||
0.066163,
|
||||
0.018252000000000001,
|
||||
211376,
|
||||
211376,
|
||||
0.20096111297607422,
|
||||
0.067087999999999995,
|
||||
0.52233399999999996,
|
||||
211384,
|
||||
211384,
|
||||
0.0,
|
||||
0.0,
|
||||
1754490737.7184789,
|
||||
8954854534841
|
||||
1755073857.1317911,
|
||||
437497361461
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"entry",
|
||||
0.051290988922119141,
|
||||
0.073860999999999996,
|
||||
0.030481999999999999,
|
||||
267268,
|
||||
268068,
|
||||
0.24745011329650879,
|
||||
0.070399000000000003,
|
||||
0.55381000000000002,
|
||||
267276,
|
||||
268076,
|
||||
0.0,
|
||||
0.0,
|
||||
1754490737.7407091,
|
||||
8954898700876
|
||||
1755073857.1782801,
|
||||
437581053845
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -36,15 +54,15 @@
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"exit",
|
||||
0.07045292854309082,
|
||||
0.093826999999999994,
|
||||
0.031666,
|
||||
268308,
|
||||
268956,
|
||||
0.29336905479431152,
|
||||
0.083322999999999994,
|
||||
0.57871700000000004,
|
||||
268356,
|
||||
269004,
|
||||
0.0,
|
||||
0.0,
|
||||
1754490737.759871,
|
||||
8954936774690
|
||||
1755073857.2241991,
|
||||
437663665281
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -52,30 +70,30 @@
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"entry",
|
||||
0.071467876434326172,
|
||||
0.094949000000000006,
|
||||
0.031666,
|
||||
268308,
|
||||
268956,
|
||||
0.29522991180419922,
|
||||
0.084689,
|
||||
0.57921299999999998,
|
||||
268512,
|
||||
269004,
|
||||
0.0,
|
||||
0.0,
|
||||
1754490737.760886,
|
||||
8954938740821
|
||||
1755073857.2260599,
|
||||
437667009444
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"entry",
|
||||
0.078627824783325195,
|
||||
0.10172299999999999,
|
||||
0.032797,
|
||||
273476,
|
||||
273480,
|
||||
0.30358695983886719,
|
||||
0.092725000000000002,
|
||||
0.57953299999999996,
|
||||
269644,
|
||||
269648,
|
||||
0.0,
|
||||
0.0,
|
||||
1754490737.7680459,
|
||||
8954952970863
|
||||
1755073857.234417,
|
||||
437682071500
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -83,15 +101,15 @@
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"exit",
|
||||
0.17286086082458496,
|
||||
0.14609,
|
||||
0.045580000000000002,
|
||||
269720,
|
||||
283444,
|
||||
0.010106,
|
||||
0.037125999999999999,
|
||||
1754490737.8622789,
|
||||
8955140243036
|
||||
0.43445897102355957,
|
||||
0.14114599999999999,
|
||||
0.62018899999999999,
|
||||
271988,
|
||||
284336,
|
||||
0.0053299999999999997,
|
||||
0.036021999999999998,
|
||||
1755073857.365289,
|
||||
437917615769
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -99,15 +117,15 @@
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"entry",
|
||||
0.17300200462341309,
|
||||
0.14621100000000001,
|
||||
0.045616999999999998,
|
||||
269720,
|
||||
283444,
|
||||
0.010106,
|
||||
0.037125999999999999,
|
||||
1754490737.8624201,
|
||||
8955140472311
|
||||
0.43466401100158691,
|
||||
0.141351,
|
||||
0.62018899999999999,
|
||||
271988,
|
||||
284336,
|
||||
0.0053299999999999997,
|
||||
0.036021999999999998,
|
||||
1755073857.365494,
|
||||
437917940077
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -115,15 +133,15 @@
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"exit",
|
||||
0.18115901947021484,
|
||||
0.15395200000000001,
|
||||
0.046651999999999999,
|
||||
271704,
|
||||
283444,
|
||||
0.010106,
|
||||
0.037125999999999999,
|
||||
1754490737.8705771,
|
||||
8955156828996
|
||||
0.44249606132507324,
|
||||
0.14918100000000001,
|
||||
0.62018899999999999,
|
||||
272132,
|
||||
284336,
|
||||
0.0053299999999999997,
|
||||
0.036021999999999998,
|
||||
1755073857.3733261,
|
||||
437932095480
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
@@ -133,15 +151,15 @@
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"exit",
|
||||
0.1812889575958252,
|
||||
0.15409800000000001,
|
||||
0.046651999999999999,
|
||||
271704,
|
||||
283444,
|
||||
0.010106,
|
||||
0.037125999999999999,
|
||||
1754490737.870707,
|
||||
8955156931612
|
||||
0.44256496429443359,
|
||||
0.149253,
|
||||
0.62018899999999999,
|
||||
272132,
|
||||
284336,
|
||||
0.0053299999999999997,
|
||||
0.036021999999999998,
|
||||
1755073857.373395,
|
||||
437932153070
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -149,30 +167,30 @@
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"entry",
|
||||
0.18133783340454102,
|
||||
0.15415200000000001,
|
||||
0.046651999999999999,
|
||||
271704,
|
||||
283444,
|
||||
0.010106,
|
||||
0.037125999999999999,
|
||||
1754490737.8707559,
|
||||
8955157006414
|
||||
0.442626953125,
|
||||
0.149314,
|
||||
0.62018899999999999,
|
||||
272132,
|
||||
284336,
|
||||
0.0053299999999999997,
|
||||
0.036021999999999998,
|
||||
1755073857.373457,
|
||||
437932273635
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"entry",
|
||||
0.22916483879089355,
|
||||
0.15607299999999999,
|
||||
0.047752999999999997,
|
||||
270148,
|
||||
283444,
|
||||
0.047620999999999997,
|
||||
0.045328,
|
||||
1754490737.9185829,
|
||||
8955252100471
|
||||
0.82204389572143555,
|
||||
0.15271999999999999,
|
||||
0.62018899999999999,
|
||||
270576,
|
||||
284336,
|
||||
0.052364000000000001,
|
||||
0.337287,
|
||||
1755073857.7528739,
|
||||
438615263732
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
@@ -180,15 +198,15 @@
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"exit",
|
||||
0.35467386245727539,
|
||||
0.288551,
|
||||
0.053816999999999997,
|
||||
282948,
|
||||
283444,
|
||||
0.047620999999999997,
|
||||
0.045328,
|
||||
1754490738.0440919,
|
||||
8955501455464
|
||||
1.0632719993591309,
|
||||
0.252332,
|
||||
0.75963899999999995,
|
||||
284212,
|
||||
284336,
|
||||
0.052364000000000001,
|
||||
0.337287,
|
||||
1755073857.994102,
|
||||
439049403609
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
@@ -198,15 +216,15 @@
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"exit",
|
||||
0.36036086082458496,
|
||||
0.29200700000000002,
|
||||
0.055891999999999997,
|
||||
282948,
|
||||
283444,
|
||||
0.047620999999999997,
|
||||
0.045328,
|
||||
1754490738.0497789,
|
||||
8955512767538
|
||||
1.0722420215606689,
|
||||
0.25439000000000001,
|
||||
0.76580700000000002,
|
||||
284212,
|
||||
284336,
|
||||
0.052364000000000001,
|
||||
0.337287,
|
||||
1755073858.003072,
|
||||
439065550163
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
@@ -216,29 +234,72 @@
|
||||
"stat": [
|
||||
"main",
|
||||
"exit",
|
||||
0.36082696914672852,
|
||||
0.29243799999999998,
|
||||
0.055974000000000003,
|
||||
282940,
|
||||
283444,
|
||||
0.047620999999999997,
|
||||
0.045328,
|
||||
1754490738.050245,
|
||||
8955513659928
|
||||
1.0725901126861572,
|
||||
0.25447700000000001,
|
||||
0.766069,
|
||||
284204,
|
||||
284336,
|
||||
0.052364000000000001,
|
||||
0.337287,
|
||||
1755073858.0034201,
|
||||
439066145641
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
],
|
||||
"cpu_cycles_pass2_start": 8955252115017,
|
||||
"incremental": "on",
|
||||
"MlibObjs": {},
|
||||
"PEModules": [],
|
||||
"rlimit": {
|
||||
"data": -1,
|
||||
"stack": -1
|
||||
"stat": {
|
||||
"ru_self_cgstart": {
|
||||
"ru_minflt": 26443,
|
||||
"ru_utime_sec": 0.15285399999999999,
|
||||
"ru_stime_sec": 0.62018899999999999,
|
||||
"ru_maxrss_kb": 76788,
|
||||
"ru_nvcsw": 112,
|
||||
"ru_majflt": 54,
|
||||
"ru_nivcsw": 7
|
||||
},
|
||||
"outputSizePerQuad": 68.894213197969549,
|
||||
"mop/quad": 2.3480203045685277,
|
||||
"nMops": 11564,
|
||||
"ru_childs_cgstart": {
|
||||
"ru_minflt": 10711,
|
||||
"ru_utime_sec": 0.052364000000000001,
|
||||
"ru_stime_sec": 0.337287,
|
||||
"ru_maxrss_kb": 26184,
|
||||
"ru_nvcsw": 53,
|
||||
"ru_majflt": 8,
|
||||
"ru_nivcsw": 26
|
||||
},
|
||||
"mopSpeed": 113777.46293180627,
|
||||
"ru_childs_end": {
|
||||
"ru_minflt": 10711,
|
||||
"ru_utime_sec": 0.052364000000000001,
|
||||
"ru_stime_sec": 0.337287,
|
||||
"ru_maxrss_kb": 26184,
|
||||
"ru_nvcsw": 53,
|
||||
"ru_majflt": 8,
|
||||
"ru_nivcsw": 26
|
||||
},
|
||||
"cpu_cycles_cgstart": 438615384880,
|
||||
"totalObjSize": 339304,
|
||||
"Frontend(%)": 66.877841325707564,
|
||||
"nQuads": 4925,
|
||||
"ru_self_end": {
|
||||
"ru_minflt": 30811,
|
||||
"ru_utime_sec": 0.25449100000000002,
|
||||
"ru_stime_sec": 0.76610999999999996,
|
||||
"ru_maxrss_kb": 90064,
|
||||
"ru_nvcsw": 116,
|
||||
"ru_majflt": 54,
|
||||
"ru_nivcsw": 7
|
||||
},
|
||||
"cpu_cycles_end": 439066199134,
|
||||
"cpu_cycles_total": 1569154993,
|
||||
"quadSpeed": 48456.762793077294,
|
||||
"CodeGen(%)": 33.122158674292429,
|
||||
"peak_mem_kb": 284336,
|
||||
"realTime": 1.0726790428161621
|
||||
},
|
||||
"CompileStrategy": "fullobj",
|
||||
"PrevCompiledModules": {},
|
||||
"PEModules": [],
|
||||
"NameTable": {
|
||||
"std": [
|
||||
"std",
|
||||
@@ -246,9 +307,9 @@
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"tb_rchannel": [
|
||||
"tb_rchannel",
|
||||
"TJvMf",
|
||||
"tb_array_ctrl": [
|
||||
"tb_array_ctrl",
|
||||
"S2s5w",
|
||||
"module",
|
||||
2
|
||||
],
|
||||
@@ -259,92 +320,31 @@
|
||||
3
|
||||
]
|
||||
},
|
||||
"stat": {
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.047620999999999997,
|
||||
"ru_nvcsw": 25,
|
||||
"ru_stime_sec": 0.045328,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 30316,
|
||||
"ru_minflt": 10693,
|
||||
"ru_nivcsw": 23
|
||||
},
|
||||
"realTime": 0.36095094680786133,
|
||||
"ru_self_cgstart": {
|
||||
"ru_utime_sec": 0.15615299999999999,
|
||||
"ru_nvcsw": 30,
|
||||
"ru_stime_sec": 0.047778000000000001,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 79444,
|
||||
"ru_minflt": 26640,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"mopSpeed": 51555.842384329379,
|
||||
"mop/quad": 2.7503912363067293,
|
||||
"cpu_cycles_cgstart": 8955252168395,
|
||||
"ru_childs_cgstart": {
|
||||
"ru_utime_sec": 0.047620999999999997,
|
||||
"ru_nvcsw": 25,
|
||||
"ru_stime_sec": 0.045328,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 30316,
|
||||
"ru_minflt": 10693,
|
||||
"ru_nivcsw": 23
|
||||
},
|
||||
"CodeGen(%)": 40.089553730768436,
|
||||
"nMops": 7030,
|
||||
"cpu_cycles_total": 659455284,
|
||||
"nQuads": 2556,
|
||||
"totalObjSize": 262988,
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.29250999999999999,
|
||||
"ru_nvcsw": 32,
|
||||
"ru_stime_sec": 0.055988000000000003,
|
||||
"ru_majflt": 0,
|
||||
"ru_maxrss_kb": 88536,
|
||||
"ru_minflt": 30657,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"cpu_cycles_end": 8955513736141,
|
||||
"quadSpeed": 18744.912252396287,
|
||||
"outputSizePerQuad": 102.8904538341158,
|
||||
"Frontend(%)": 59.910446269231564,
|
||||
"peak_mem_kb": 283444
|
||||
"cpu_cycles_pass2_start": 438615277851,
|
||||
"rlimit": {
|
||||
"stack": -1,
|
||||
"data": -1
|
||||
},
|
||||
"SIMBData": {
|
||||
"bytes": 120018,
|
||||
"out": "amcQwB.o",
|
||||
"text": 0,
|
||||
"archive": "archive.0/_5573_archive_1.a"
|
||||
},
|
||||
"incremental": "on",
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
],
|
||||
"CurCompileModules": [
|
||||
"...MASTER...",
|
||||
"...MASTER...",
|
||||
"std",
|
||||
"std",
|
||||
"tb_rchannel",
|
||||
"tb_rchannel"
|
||||
],
|
||||
"CurCompileUdps": {},
|
||||
"SIMBData": {
|
||||
"out": "amcQwB.o",
|
||||
"bytes": 117874,
|
||||
"text": 0,
|
||||
"archive": "archive.0/_25796_archive_1.a"
|
||||
},
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
"tb_array_ctrl",
|
||||
"tb_array_ctrl"
|
||||
],
|
||||
"CompileStatus": "Successful",
|
||||
"CompileProcesses": [
|
||||
"cgproc.25796.json"
|
||||
],
|
||||
"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"archive_dir": "archive.0",
|
||||
"csrc": "csrc",
|
||||
"master_pid": 25796,
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"hostname": "IC_EDA",
|
||||
"cwd": "/home/ICer/ic_prjs/mc/IC_PRJ/sim",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc",
|
||||
"daidir": "simv.daidir",
|
||||
"default_output_dir": "csrc"
|
||||
},
|
||||
"CompileStatus": "Successful"
|
||||
"cgproc.5573.json"
|
||||
]
|
||||
}
|
||||
@@ -1,12 +1,12 @@
|
||||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _25796_archive_1.so
|
||||
_25796_archive_1.so : archive.0/_25796_archive_1.a
|
||||
ARCHIVE_OBJS += _5573_archive_1.so
|
||||
_5573_archive_1.so : archive.0/_5573_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_25796_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_5573_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_25796_archive_1.so $@
|
||||
@ln -sf .//../simv.daidir//_5573_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,14 +1,30 @@
|
||||
../rtl/sync_fifo_128_to_64.v
|
||||
#../rtl/sync_fifo_64_to_128.v
|
||||
#../rtl/async_fifo.v
|
||||
#../rtl/wchannel.v
|
||||
../rtl/sync_fifo.v
|
||||
../rtl/rchannel.v
|
||||
#../rtl/frame_arbiter.v
|
||||
#../tb/tb_sync_fifo_128_to_64.v
|
||||
#../tb/tb_async_fifo.v
|
||||
#../tb/tb_sync_fifo_64_to_128.v
|
||||
#../tb/tb_sync_fifo.v
|
||||
#../tb/tb_wchannel.v
|
||||
../tb/tb_rchannel.v
|
||||
#../tb/tb_frame_arbiter.v
|
||||
../rtl/async_fifo.v
|
||||
// ../rtl/sync_fifo.v
|
||||
// ../rtl/wchannel.v
|
||||
// ../rtl/frame_arbiter.v
|
||||
// ../rtl/sync_fifo_64_to_128.v
|
||||
// ../rtl/sync_fifo_128_to_64.v
|
||||
// ../rtl/rchannel.v
|
||||
// ../rtl/axi_slv.v
|
||||
../rtl/array_ctrl.v
|
||||
../rtl/array_status_ctrl.v
|
||||
../rtl/array_wr.v
|
||||
../rtl/array_rd.v
|
||||
../rtl/array_ref.v
|
||||
../rtl/array_mux.v
|
||||
//../rtl/apb_cfg.v
|
||||
// ../tb/tb_async_fifo.v
|
||||
// ../tb/tb_rchannel.v
|
||||
// ../tb/tb_sync_fifo.v
|
||||
// ../tb/tb_sync_fifo_128_to_64.v
|
||||
// ../tb/tb_sync_fifo_64_to_128.v
|
||||
// ../tb/tb_wchannel.v
|
||||
// ../tb/tb_frame_arbiter.v
|
||||
// ../tb/tb_axi_slv.v
|
||||
// ../tb/tb_array_status_ctrl.v
|
||||
// ../tb/tb_array_wr.v
|
||||
// ../tb/tb_array_rd.v
|
||||
// ../tb/tb_array_ref.v
|
||||
// ../tb/tb_array_mux.v
|
||||
../tb/tb_array_ctrl.v
|
||||
//../tb/tb_apb_cfg.v
|
||||
|
||||
444
sim/novas.conf
444
sim/novas.conf
File diff suppressed because one or more lines are too long
101
sim/novas.rc
101
sim/novas.rc
@@ -275,14 +275,6 @@ bScpecifyCellNameCase = False
|
||||
bSpecifyPinNameCase = False
|
||||
CellNameToCase =
|
||||
PinNameToCase =
|
||||
[InteractiveDebug]
|
||||
tbvLocalWatchArrayLimit = 50
|
||||
Watch_0 = 150 80 80 0
|
||||
Watch_1 = 150 80 80 306
|
||||
Watch_2 = 150 80 80 200
|
||||
Watch_3 = 150 80 80 200
|
||||
Watch_4 = 150 80 80 200
|
||||
Watch_5 = 150 80 80 200
|
||||
[Language]
|
||||
EditWindow_Font = COURIER12
|
||||
Background = ID_WHITE
|
||||
@@ -376,8 +368,8 @@ saveWaveformStat = TRUE
|
||||
savePropStat = FALSE
|
||||
savePropDtl = TRUE
|
||||
[QtDialog]
|
||||
qWaveSignalDialog = 547,204,800,479
|
||||
QwUserAskDlg = 795,385,324,134
|
||||
qWaveSignalDialog = 549,206,800,479
|
||||
QwUserAskDlg = 797,387,324,134
|
||||
[Relationship]
|
||||
hideRecursiceNode = FALSE
|
||||
[Session Cache]
|
||||
@@ -442,6 +434,7 @@ vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd"
|
||||
scs_mixPath = scsim
|
||||
scs_mixOption = -vhpi debussy:FSDBDumpCmd
|
||||
vcs_svPath = simv
|
||||
vcs_svOption =
|
||||
simType = vcssv
|
||||
thirdpartyIdx = -1
|
||||
interactiveDebugging = FALSE
|
||||
@@ -450,11 +443,8 @@ iscCmdSep = FALSE
|
||||
ScsDebugAll = FALSE
|
||||
NoAppendOption = FALSE
|
||||
invokeSimPath = work
|
||||
smartlog = TRUE
|
||||
vcs_svOption = -sml=verdi
|
||||
[SimulationPlus2]
|
||||
eventDumpUnfinish = FALSE
|
||||
dumpPowerRoot = FALSE
|
||||
[Source]
|
||||
wordWrapOn = TRUE
|
||||
viewReuse = TRUE
|
||||
@@ -483,7 +473,6 @@ nLineSize = 1024
|
||||
verbose_progress = FALSE
|
||||
[TestBenchBrowser]
|
||||
-showUVMDynamicHierTreeWin = FALSE
|
||||
DataViewTooltip = TRUE
|
||||
[Text]
|
||||
hdlTypeName = blue4
|
||||
hdlLibrary = blue4
|
||||
@@ -567,7 +556,7 @@ pdmlMacro = ID_BLACK
|
||||
font = COURIER12
|
||||
annotFont = Helvetica_M_R_10
|
||||
[Text.1]
|
||||
viewport = -10 20 1914 774 45
|
||||
viewport = -10 20 1918 778 45
|
||||
[TextPrinter]
|
||||
Orientation = Landscape
|
||||
Indicator = FALSE
|
||||
@@ -650,44 +639,6 @@ Button2 = "Next 1000 Time" "#1000 $stop;.\n"
|
||||
Button1 = "Dump All Signals" "$fsdbDumpvars;\n"
|
||||
[VIA]
|
||||
viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc"
|
||||
viaLogViewerDefaultRuleInterForm = "share/VIA/Apps/PredefinedRules/UVM_OVM_i_rule.rc"
|
||||
[VIA.interactiveDebug.preference]
|
||||
DefaultDisplayTimeUnit = "1.000000ns"
|
||||
DefaultLogTimeUnit = "1.000000ns"
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC]
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0]
|
||||
parRuleSets = "/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_OVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_UVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRule\
|
||||
s/par_rule_LP.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_VCS.rc "
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column0]
|
||||
name = Time
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column1]
|
||||
name = Type
|
||||
width = 60
|
||||
visualIndex = 3
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column3]
|
||||
name = Code
|
||||
width = 60
|
||||
visualIndex = 2
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column4]
|
||||
name = Severity
|
||||
width = 60
|
||||
visualIndex = 1
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference]
|
||||
DefaultDisplayTimeUnit = "1.000000ns"
|
||||
DefaultLogTimeUnit = "1.000000ns"
|
||||
@@ -701,31 +652,29 @@ visualIndex = 1
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1]
|
||||
name = Type
|
||||
width = 60
|
||||
visualIndex = 3
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3]
|
||||
name = Time
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4]
|
||||
name = Code
|
||||
width = 60
|
||||
visualIndex = 2
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.parRule]
|
||||
parRulePathInterForm = ""
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2]
|
||||
name = Type
|
||||
width = 60
|
||||
visualIndex = 3
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3]
|
||||
name = Message
|
||||
width = 2000
|
||||
visualIndex = 4
|
||||
isHidden = FALSE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4]
|
||||
name = Time
|
||||
width = 60
|
||||
visualIndex = 0
|
||||
isHidden = TRUE
|
||||
isUserChangeColumnVisible = FALSE
|
||||
[Vi]
|
||||
ViFont = "Clean 14"
|
||||
ViBG = white
|
||||
@@ -741,8 +690,8 @@ ovaForbidSuccessColor = -c ID_GREEN5
|
||||
SigGroupRuleFile =
|
||||
DisplayFileName = FALSE
|
||||
waveform_vertical_scroll_bar = TRUE
|
||||
getSignalForm = 547 167 800 479 164 381 390 89
|
||||
viewPort = 0 27 1914 590 285 195
|
||||
getSignalForm = 549 169 800 479 164 381 390 89
|
||||
viewPort = 0 27 1918 673 227 36
|
||||
signalSpacing = 5
|
||||
digitalSignalHeight = 15
|
||||
analogSignalHeight = 98
|
||||
@@ -1342,7 +1291,7 @@ AddImportArgument = FALSE
|
||||
LineBreakWithScope = TRUE
|
||||
StopAfterCompileOption = -s
|
||||
[wave.0]
|
||||
viewPort = 0 27 1914 590 285 195
|
||||
viewPort = 0 27 1918 673 227 36
|
||||
[wave.1]
|
||||
viewPort = 127 219 960 332 100 65
|
||||
[wave.2]
|
||||
|
||||
@@ -2,158 +2,154 @@
|
||||
# log primitive debug message of FSDB dumping #
|
||||
# This is for R&D to analyze when there are issues happening when FSDB dump #
|
||||
#######################################################################################
|
||||
ANF: vcsd_get_serial_mode_status('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
ANF: vcsd_get_serial_mode_status('simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
VCS compile option:
|
||||
option[0]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv
|
||||
option[1]: -sml=verdi
|
||||
option[2]: +fsdb+gate=off
|
||||
option[3]: -ucli2Proc
|
||||
option[4]: -ucli
|
||||
option[5]: -l
|
||||
option[6]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
option[7]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
option[8]: -Mcc=gcc
|
||||
option[9]: -Mcplusplus=g++
|
||||
option[10]: -Masflags=
|
||||
option[11]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[12]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[13]: -Mldflags= -rdynamic
|
||||
option[14]: -Mout=simv
|
||||
option[15]: -Mamsrun=
|
||||
option[16]: -Mvcsaceobjs=
|
||||
option[17]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
option[18]: -Mexternalobj=
|
||||
option[19]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
option[20]: -Mcrt0=
|
||||
option[21]: -Mcrtn=
|
||||
option[22]: -Mcsrc=
|
||||
option[23]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[24]: -Xvcs_run_simv=1
|
||||
option[25]: -timescale=1ns/1ps
|
||||
option[26]: -full64
|
||||
option[27]: +vc
|
||||
option[28]: +v2k
|
||||
option[29]: -debug_access+all
|
||||
option[30]: +vpi
|
||||
option[31]: +vcsd1
|
||||
option[32]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[33]: -picarchive
|
||||
option[34]: -P
|
||||
option[35]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[36]: -fsdb
|
||||
option[37]: -sverilog
|
||||
option[38]: -gen_obj
|
||||
option[39]: -f
|
||||
option[40]: filelist.f
|
||||
option[41]: -load
|
||||
option[42]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[43]: timescale=1ns/1ps
|
||||
option[0]: simv
|
||||
option[1]: +vc
|
||||
option[2]: +v2k
|
||||
option[3]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
option[4]: -Mcc=gcc
|
||||
option[5]: -Mcplusplus=g++
|
||||
option[6]: -Masflags=
|
||||
option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[9]: -Mldflags= -rdynamic
|
||||
option[10]: -Mout=simv
|
||||
option[11]: -Mamsrun=
|
||||
option[12]: -Mvcsaceobjs=
|
||||
option[13]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
option[14]: -Mexternalobj=
|
||||
option[15]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
option[16]: -Mcrt0=
|
||||
option[17]: -Mcrtn=
|
||||
option[18]: -Mcsrc=
|
||||
option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[20]: -Xvcs_run_simv=1
|
||||
option[21]: -timescale=1ns/1ps
|
||||
option[22]: -full64
|
||||
option[23]: +vc
|
||||
option[24]: +v2k
|
||||
option[25]: -debug_access+all
|
||||
option[26]: +vpi
|
||||
option[27]: +vcsd1
|
||||
option[28]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[29]: -picarchive
|
||||
option[30]: -P
|
||||
option[31]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[32]: -fsdb
|
||||
option[33]: -sverilog
|
||||
option[34]: -gen_obj
|
||||
option[35]: -f
|
||||
option[36]: filelist.f
|
||||
option[37]: -load
|
||||
option[38]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[39]: timescale=1ns/1ps
|
||||
Chronologic Simulation VCS Release O-2018.09-1_Full64
|
||||
Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
|
||||
CPU cores: 8
|
||||
@@ -173,255 +169,163 @@ maxproc 4096
|
||||
(Special)Runtime environment variables:
|
||||
|
||||
Runtime environment variables:
|
||||
XDG_VTNR=1
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
SSH_AGENT_PID=3826
|
||||
XDG_SESSION_ID=1
|
||||
XDG_SESSION_ID=2
|
||||
HOSTNAME=IC_EDA
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
NOVAS_SYNC_MOTIF_DISP=
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
TERM_PROGRAM=vscode
|
||||
UNAME=/bin/uname
|
||||
SELINUX_ROLE_REQUESTED=
|
||||
SCRNAME=vcs
|
||||
VCS_DEPTH=0
|
||||
SHELL=/bin/bash
|
||||
VTE_VERSION=5204
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
TERM=xterm-256color
|
||||
MAKEFLAGS=
|
||||
HISTSIZE=1000
|
||||
SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font
|
||||
SSH_CLIENT=192.168.223.1 52776 22
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/83465594_02bf_4b80_a6ef_1d361b15e756
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont
|
||||
SELINUX_USE_CURRENT_RANGE=
|
||||
TERM_PROGRAM_VERSION=1.85.2
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
LC_ALL=C
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
IMSETTINGS_MODULE=none
|
||||
USER=ICer
|
||||
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
|
||||
LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib::/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
SCRIPT_NAME=vcs
|
||||
MAKE_TERMOUT=/dev/pts/0
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
VCS_MX_HOME_INTERNAL=1
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SNPSLMD_LICENSE_FILE=27000@IC_EDA
|
||||
USERNAME=ICer
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3690,unix/unix:/tmp/.ICE-unix/3690
|
||||
MAKELEVEL=1
|
||||
OVA_UUM=0
|
||||
MFLAGS=
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
PATH=/bin:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
|
||||
VCS_MODE_FLAG=64
|
||||
PATH=.:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/remote-cli:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/bin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user:/usr/local/sbin:/usr/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
|
||||
MAIL=/var/spool/mail/ICer
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
QT_IM_MODULE=ibus
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
XDG_SESSION_TYPE=x11
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
PWD=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
XMODIFIERS=@im=none
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SYS_PROG_NAME=verdi
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
LANG=C
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
LANG=zh_CN.UTF-8
|
||||
KDEDIRS=/usr
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
VSCODE_GIT_ASKPASS_EXTRA_ARGS=
|
||||
VMR_MODE_FLAG=64
|
||||
SELINUX_LEVEL_REQUESTED=
|
||||
CDSHOME=/home/cadence/IC617
|
||||
SYS_INST_DIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
GDMSESSION=gnome-classic
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
HISTCONTROL=ignoredups
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
SNPS_VCS_TMPDIR=/tmp/vcs_20250813083055_5256
|
||||
HOME=/home/ICer
|
||||
XDG_SEAT=seat0
|
||||
RISCV=/home/Riscv_Tools
|
||||
SHLVL=3
|
||||
SHLVL=7
|
||||
VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js
|
||||
MGC_HOME=/home/mentor/
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
VERDI_ORIGNAL_LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
MGC_LICENSE_FILE=/home/mentor//license/license.dat
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
CADHOME=/home/cadence
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
VCS_COM=/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
LOGNAME=ICer
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
MAKE_TERMERR=/dev/pts/0
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-LHuevZztAf,guid=55ddfa7976bc586b8b8ee131689354d9
|
||||
NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc
|
||||
SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
|
||||
SSH_CONNECTION=192.168.223.1 52776 192.168.223.129 22
|
||||
VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock
|
||||
VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-e469d87e-6fcb-418d-9f59-455493644d33.sock
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
BROWSER=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/helpers/browser.sh
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
WINDOWPATH=1
|
||||
LD_NOVERSION=1
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node
|
||||
GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
DISPLAY=:0
|
||||
QT_PLUGIN_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/plugins
|
||||
VCS_ARCH=linux64
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JLN4Y3/database
|
||||
COLORTERM=truecolor
|
||||
PS_HWPC=OFF
|
||||
NOVAS_LC_ALL=C
|
||||
NOVAS_SIGNAL_BASE_EXTRACTION=1
|
||||
SIGNAL_BASE_EXTRACTION=1
|
||||
NOVAS_VERDI_SVTB_BETA=1
|
||||
VERDI_SVTB_BETA=1
|
||||
NOVAS_VERDI_SVTB_ALPHA=1
|
||||
VERDI_SVTB_ALPHA=1
|
||||
NOVAS_VERDI_TB_HT=1
|
||||
VERDI_TB_HT=1
|
||||
NOVAS_WAVE_REDRAW_ALLVC=1
|
||||
WAVE_REDRAW_ALLVC=1
|
||||
NOVAS_TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
|
||||
TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library
|
||||
XKEYSYMDB=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/XKeysymDB2.1
|
||||
XLOCALEDIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/locale
|
||||
NOVAS_SIGNAL_BASED_BA=0
|
||||
SIGNAL_BASED_BA=0
|
||||
SYNOPSYS_SIM=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DISABLE_LIBRARY_MAP_CHECK=1
|
||||
SNPS_SIM_DEFAULT_GUI=verdi
|
||||
FSDB_FILE=/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
VCS_UCLI_STDIN_BLOCKING=1
|
||||
FSDB_VHDL_PROTECTED=1
|
||||
FSDB_RD_IR_ENABLE=1
|
||||
FSDB_SVA_STATUS=1
|
||||
_=./simv
|
||||
OLDPWD=/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch
|
||||
VCS_HEAP_EXEC=true
|
||||
VCS_PATHMAP_PRELOAD_DONE=1
|
||||
VCS_STACK_EXEC=true
|
||||
VCS_EXEC_DONE=1
|
||||
VCS_STOP_SAFE=1
|
||||
DVE_SIM_SELECT_LOOP=on
|
||||
DVE=/home/synopsys/vcs-mx/O-2018.09-1/gui/dve
|
||||
SPECMAN_OUTPUT_TO_TTY=1
|
||||
Runtime command line arguments:
|
||||
argv[0]=/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv
|
||||
argv[1]=-sml=verdi
|
||||
argv[2]=+fsdb+gate=off
|
||||
argv[3]=-ucli2Proc
|
||||
argv[4]=-ucli
|
||||
argv[5]=-l
|
||||
argv[6]=/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log
|
||||
317 profile - 100
|
||||
CPU/Mem usage: 0.030 sys, 0.110 user, 236.15M mem
|
||||
318 Wed Aug 6 22:32:55 2025
|
||||
319 pliAppInit
|
||||
320 ndpGetenv(FSDB_FILE): /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
321 ndpGetenv(FSDB_SVA_STATUS): 1
|
||||
322 ndpGetenv(FSDB_VHDL_PROTECTED): 1
|
||||
323 FSDB_GATE & FSDB_RTL is disabled.
|
||||
324 Enable Parallel Dumping.
|
||||
325 pliAppMiscSet: New Sim Round
|
||||
326 pliEntryInit
|
||||
327 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
328 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
329 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
330 sps_tcl_fsdbDumpfile_main at 0
|
||||
331 argv[0]: /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
332 *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb'
|
||||
333 compile option from '/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/vcs_rebuild'.
|
||||
334 "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
335 sps_tcl_fsdbDumpflush_vd_main
|
||||
336 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
337 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
338 sps_tcl_fsdbDumpvarsByFile_vd_main at 0 : N/A(0)
|
||||
339 *Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file).
|
||||
340 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
341 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
342 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 329.39M mem
|
||||
incr: 0.000 sys, 0.000 user, 2.65M mem
|
||||
accu: 0.000 sys, 0.000 user, 2.65M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 2.65M mem
|
||||
argv[0]=simv
|
||||
argv[1]=+vc
|
||||
argv[2]=+v2k
|
||||
271 profile - 100
|
||||
CPU/Mem usage: 0.920 sys, 0.370 user, 245.56M mem
|
||||
272 Wed Aug 13 16:31:00 2025
|
||||
273 pliAppInit
|
||||
274 FSDB_GATE is set.
|
||||
275 FSDB_RTL is set.
|
||||
276 Enable Parallel Dumping.
|
||||
277 pliAppMiscSet: New Sim Round
|
||||
278 pliEntryInit
|
||||
279 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
280 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
281 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
282 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_array_ctrl.v(212)
|
||||
283 argv[0]: (tb.fsdb)
|
||||
284 *Verdi* : Create FSDB file 'tb.fsdb'
|
||||
285 compile option from '/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/vcs_rebuild'.
|
||||
286 "vcs '-f' 'filelist.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
287 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
288 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_array_ctrl.v(213)
|
||||
289 argv[0]: (0)
|
||||
290 argv[1]: (handle) tb_array_ctrl
|
||||
291 argv[2]: (+all)
|
||||
292 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
293 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
294 *Verdi* : Begin traversing the scope (tb_array_ctrl), layer (0).
|
||||
295 *Verdi* : Enable +all dumping.
|
||||
296 *Verdi* : End of traversing.
|
||||
297 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 1.570 sys, 0.370 user, 342.00M mem
|
||||
incr: 0.060 sys, 0.000 user, 8.61M mem
|
||||
accu: 0.060 sys, 0.000 user, 8.61M mem
|
||||
accu incr: 0.060 sys, 0.000 user, 8.61M mem
|
||||
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
incr: 44 var, 44 idcode, 44 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu incr: 44 var, 44 idcode, 44 callback
|
||||
343 Wed Aug 6 22:32:57 2025
|
||||
344 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 330.44M mem
|
||||
Count usage: 221 var, 140 idcode, 71 callback
|
||||
incr: 221 var, 140 idcode, 71 callback
|
||||
accu: 221 var, 140 idcode, 71 callback
|
||||
accu incr: 221 var, 140 idcode, 71 callback
|
||||
298 Wed Aug 13 16:31:01 2025
|
||||
299 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 1.570 sys, 0.370 user, 343.05M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu: 0.060 sys, 0.000 user, 9.66M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
Count usage: 221 var, 140 idcode, 71 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu: 221 var, 140 idcode, 71 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
345 Wed Aug 6 22:32:57 2025
|
||||
346 *Verdi* : End of dumping.
|
||||
347 fsdbDumpvarsByFile: profile -
|
||||
CPU/Mem usage: 0.110 sys, 0.110 user, 330.44M mem
|
||||
incr: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu: 0.000 sys, 0.000 user, 3.70M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 3.70M mem
|
||||
|
||||
Count usage: 44 var, 44 idcode, 44 callback
|
||||
incr: 44 var, 44 idcode, 44 callback
|
||||
accu: 44 var, 44 idcode, 44 callback
|
||||
accu incr: 44 var, 44 idcode, 44 callback
|
||||
348 Wed Aug 6 22:32:57 2025
|
||||
349 sps_tcl_fsdbDumpflush_vd_main
|
||||
350 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
351 sps_tcl_fsdbDumpflush_vd_main
|
||||
352 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
353 sps_tcl_fsdbDumpflush_vd_main
|
||||
354 *Verdi* : Flush all FSDB Files at 0 ps.
|
||||
355 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_rchannel.v(98)
|
||||
356 argv[0]: (tb.fsdb)
|
||||
357 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_rchannel.v(99)
|
||||
358 argv[0]: (0)
|
||||
359 argv[1]: (handle) tb_rchannel
|
||||
360 argv[2]: (+all)
|
||||
361 *Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
362 *Verdi* : Enable +all dumping.
|
||||
363 *Verdi* : End of traversing.
|
||||
364 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.120 sys, 0.110 user, 333.21M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 159 var, 85 idcode, 72 callback
|
||||
incr: 115 var, 41 idcode, 28 callback
|
||||
accu: 115 var, 41 idcode, 28 callback
|
||||
accu incr: 115 var, 41 idcode, 28 callback
|
||||
365 Wed Aug 6 22:32:59 2025
|
||||
366 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.130 sys, 0.110 user, 333.21M mem
|
||||
incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 1.05M mem
|
||||
accu incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 159 var, 85 idcode, 72 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 115 var, 41 idcode, 28 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
367 Wed Aug 6 22:32:59 2025
|
||||
368 sps_tcl_fsdbDumpflush_vd_main
|
||||
369 *Verdi* : Flush all FSDB Files at 365,000 ps.
|
||||
370 End of simulation at 365000
|
||||
371 Wed Aug 6 22:41:15 2025
|
||||
372 Begin FSDB profile info:
|
||||
373 FSDB Writer : bc1(202) bcn(288) mtf/stf(0/5)
|
||||
FSDB Writer elapsed time : flush(0.014706) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
300 Wed Aug 13 16:31:01 2025
|
||||
301 End of simulation at 3648750
|
||||
302 Wed Aug 13 16:31:01 2025
|
||||
303 Begin FSDB profile info:
|
||||
304 FSDB Writer : bc1(3057) bcn(590) mtf/stf(0/0)
|
||||
FSDB Writer elapsed time : flush(0.034176) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
374 End FSDB profile info
|
||||
375 Parallel profile - Flush:10 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
|
||||
376 ProduceTime:0.262536335 ConsumerTime:0.000000000 Buffer:64MB
|
||||
377 SimExit
|
||||
378 Sim process exit
|
||||
305 End FSDB profile info
|
||||
306 Parallel profile - Flush:3 Expand:0 ProduceWait:0 ConsumerWait:0 BlockUsed:0
|
||||
307 ProduceTime:2.059042140 ConsumerTime:0.000000000 Buffer:64MB
|
||||
308 SimExit
|
||||
309 Sim process exit
|
||||
|
||||
@@ -33,22 +33,17 @@
|
||||
-timescale=1ns/1ps
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
88
|
||||
71
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
XMODIFIERS=@im=ibus
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
XDG_VTNR=1
|
||||
XDG_SESSION_TYPE=x11
|
||||
XDG_SESSION_ID=1
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
XDG_SEAT=seat0
|
||||
XDG_SESSION_ID=2
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-JLN4Y3/database
|
||||
WINDOWPATH=1
|
||||
VTE_VERSION=5204
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
|
||||
VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-e469d87e-6fcb-418d-9f59-455493644d33.sock
|
||||
VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock
|
||||
VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node
|
||||
VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js
|
||||
VSCODE_GIT_ASKPASS_EXTRA_ARGS=
|
||||
VMR_MODE_FLAG=64
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
VCS_MX_HOME_INTERNAL=1
|
||||
@@ -58,23 +53,25 @@ VCS_DEPTH=0
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
VCS_ARCH=linux64
|
||||
USERNAME=ICer
|
||||
UNAME=/bin/uname
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
TERM_PROGRAM_VERSION=1.85.2
|
||||
TERM_PROGRAM=vscode
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
SSH_AGENT_PID=3826
|
||||
SSH_CONNECTION=192.168.223.1 52776 192.168.223.129 22
|
||||
SSH_CLIENT=192.168.223.1 52776 22
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/3690,unix/unix:/tmp/.ICE-unix/3690
|
||||
SELINUX_USE_CURRENT_RANGE=
|
||||
SELINUX_ROLE_REQUESTED=
|
||||
SELINUX_LEVEL_REQUESTED=
|
||||
SCRNAME=vcs
|
||||
SCRIPT_NAME=vcs
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
RISCV=/home/Riscv_Tools
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
QT_IM_MODULE=ibus
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
@@ -94,41 +91,31 @@ MAKE_TERMERR=/dev/pts/0
|
||||
MAKELEVEL=1
|
||||
MAKEFLAGS=
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
LC_ALL=C
|
||||
KDEDIRS=/usr
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
IMSETTINGS_MODULE=none
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
HISTCONTROL=ignoredups
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/83465594_02bf_4b80_a6ef_1d361b15e756
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
GDMSESSION=gnome-classic
|
||||
GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-LHuevZztAf,guid=55ddfa7976bc586b8b8ee131689354d9
|
||||
COLORTERM=truecolor
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
CDSHOME=/home/cadence/IC617
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
CADHOME=/home/cadence
|
||||
0
|
||||
7
|
||||
1754471014 ../tb/tb_rchannel.v
|
||||
1754490726 ../rtl/rchannel.v
|
||||
1754471014 ../rtl/sync_fifo.v
|
||||
1754489537 ../rtl/sync_fifo_128_to_64.v
|
||||
1754489266 filelist.f
|
||||
11
|
||||
1755056699 ../tb/tb_array_ctrl.v
|
||||
1754836477 ../rtl/array_mux.v
|
||||
1754835004 ../rtl/array_ref.v
|
||||
1754838848 ../rtl/array_rd.v
|
||||
1754824141 ../rtl/array_wr.v
|
||||
1755053675 ../rtl/array_status_ctrl.v
|
||||
1754838855 ../rtl/array_ctrl.v
|
||||
1754471014 ../rtl/async_fifo.v
|
||||
1755073833 filelist.f
|
||||
1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
4
|
||||
@@ -136,5 +123,5 @@ CADHOME=/home/cadence
|
||||
1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
|
||||
1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
|
||||
1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
1754490739 simv.daidir
|
||||
1755073861 simv.daidir
|
||||
-1 partitionlib
|
||||
|
||||
Binary file not shown.
@@ -1,11 +1,17 @@
|
||||
sid tb_rchannel
|
||||
bcid 0 0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET
|
||||
bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU CALL_ARG_VAL,6,0 NOT AND AND RET
|
||||
bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,7 CALL_ARG_VAL,4,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND AND RET
|
||||
bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 5 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,7 CALL_ARG_VAL,3,0 WIDTH,8 PAD WIDTH,30 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 WIDTH,1 OPT_CONST,1 WIDTH,8 SHIFT_R WIDTH,1 M_EQU AND RET
|
||||
bcid 6 6 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 XOR WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,1 M_EQU AND RET
|
||||
bcid 7 7 WIDTH,3 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
bcid 8 8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 PAD SUBTRACT OPT_CONST,8 WIDTH,1 M_EQU RET
|
||||
bcid 9 9 WIDTH,4 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
sid tb_array_ctrl
|
||||
bcid 0 0 WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,5,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,2 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,3 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,1 MITECONDNOINSTR,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 1 1 WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 WIDTH,152 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,151 WIDTH,1 SLICE,1 AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 OPT_CONST,0 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,3 OPT_CONST,2 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,3 OPT_CONST,3 OPT_CONST,2 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,4 OPT_CONST,5 MITECONDNOINSTR,4 OPT_CONST,4 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,3 OPT_CONST,6 OPT_CONST,5 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,6 OPT_CONST,5 MITECONDNOINSTR,4 OPT_CONST,6 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,8 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 M_EQU AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,7 OPT_CONST,6 MITECONDNOINSTR,4 OPT_CONST,7 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,10,0 OPT_CONST,0 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 OPT_CONST,7 MITECONDNOINSTR,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 2 2 WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 OPT_CONST,0 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,2 OPT_CONST,2 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 OPT_CONST,2 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,6,0 OPT_CONST,65535 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 OPT_CONST,1 MITECONDNOINSTR,4 OPT_CONST,3 MITECONDNOINSTR,4 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 3 3 WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 4 4 WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,4,0 WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,5,0 OPT_CONST,1 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 5 5 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND OR RET
|
||||
bcid 6 6 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET
|
||||
bcid 7 7 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET
|
||||
bcid 8 8 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET
|
||||
bcid 9 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET
|
||||
bcid 10 10 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 NOT AND OR RET
|
||||
bcid 11 11 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 PAD OPT_CONST,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 12 12 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU WIDTH,8 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET
|
||||
bcid 13 13 WIDTH,3 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,3 SHIFT_R XOR RET
|
||||
bcid 14 14 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,65535 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET
|
||||
bcid 15 15 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_NEQU RET
|
||||
|
||||
@@ -5,9 +5,9 @@
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"tb_rchannel": [
|
||||
"tb_rchannel",
|
||||
"TJvMf",
|
||||
"tb_array_ctrl": [
|
||||
"tb_array_ctrl",
|
||||
"S2s5w",
|
||||
"module",
|
||||
2
|
||||
],
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -5,5 +5,5 @@ PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_9Anw8J.xml.gz" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_HGElac.xml.gz" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
|
||||
Binary file not shown.
@@ -1,4 +1,8 @@
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/rchannel.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo_128_to_64.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_ctrl.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_mux.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_rd.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_ref.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_status_ctrl.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_wr.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/async_fifo.v
|
||||
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_array_ctrl.v
|
||||
|
||||
@@ -1 +1 @@
|
||||
}<7D>
|
||||
<EFBFBD>4U
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -7,7 +7,7 @@ UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=tb_rchannel
|
||||
TOP=tb_array_ctrl
|
||||
OPTION=-ssv -ssy
|
||||
ELAB_OPTION=-ssv -ssy
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,3 +1,4 @@
|
||||
vcselab_misc_midd.db 445
|
||||
vcselab_misc_mnmn.db 24
|
||||
vcselab_misc_hsim_name.db 181
|
||||
vcselab_misc_midd.db 693
|
||||
vcselab_misc_mnmn.db 26
|
||||
vcselab_misc_hsim_name.db 209
|
||||
vcselab_misc_hsim_merge.db 19304
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
sim/tb.fsdb
BIN
sim/tb.fsdb
Binary file not shown.
53
sim/ucli.key
53
sim/ucli.key
@@ -1,53 +0,0 @@
|
||||
synUtils::getArch
|
||||
loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd
|
||||
config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP {<ucli_break_bp_status_begin> <ucli_break_bp_status_end>};cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb} ;fsdbDumpflush ;
|
||||
sps_interactive
|
||||
ucliCore::getToolPID
|
||||
ucliCore::getToolPID
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
puts $ucliCore::nativeUcliMode
|
||||
ucliCore::getToolTopPID
|
||||
pid
|
||||
synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.26345 }
|
||||
if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024}
|
||||
info command stateVerdiChangeCB
|
||||
proc stateVerdiChangeCB args { if {$ucliGUI::state eq "terminated"} {puts "\nVERDI_SIM_Terminated\n";catch {setVerdiSimTerminated}}}
|
||||
trace variable ucliGUI::state wu stateVerdiChangeCB
|
||||
if {[catch {rename synopsys::restore verdiHack::restore} ]} {puts "0"}
|
||||
proc synopsys::restore {args} { verdiHack::restore $args; puts "\nVERDI_SIM_RESTORE\n"}
|
||||
if {[catch {rename quit verdiHack::quit} ]} {puts "0"}
|
||||
proc quit {args} { if {[string length $args] == 0} { verdiHack::quit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n quit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::quit $args; } }
|
||||
if {[catch {rename exit verdiHack::exit} ]} {puts "0"}
|
||||
proc exit {args} { if {[string length $args] == 0} { verdiHack::exit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n exit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::exit $args; } }
|
||||
proc checkpoint::beforeRecreate {} { sps_interactive }
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
save::getUserdefinedProcs
|
||||
info procs
|
||||
lappend ucliCore::resultTagsForVerdi <?special_verdi_begin?> <?special_verdi_end?>
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush
|
||||
fsdbDumpflush
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
fsdbDumpflush
|
||||
senv
|
||||
synUtils::resolveSourceFilename ../tb/tb_rchannel.v
|
||||
puts $::ucliCore::cbug_active
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
checkpoint -list -all
|
||||
stop
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
run
|
||||
synEnv::hasFataled
|
||||
ucliCore::getToolPID
|
||||
save::getUserdefinedProcs
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
fsdbDumpflush
|
||||
senv
|
||||
synUtils::resolveSourceFilename ../tb/tb_rchannel.v
|
||||
puts $::ucliCore::cbug_active
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
checkpoint -list -all
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
stop
|
||||
if {[catch {ucliCore::setFocus tool}]} {}
|
||||
finish; quit
|
||||
|
||||
93
sim/vcs.log
93
sim/vcs.log
@@ -1,5 +1,5 @@
|
||||
Chronologic VCS (TM)
|
||||
Version O-2018.09-1_Full64 -- Wed Aug 6 22:32:17 2025
|
||||
Version O-2018.09-1_Full64 -- Wed Aug 13 16:30:57 2025
|
||||
Copyright (c) 1991-2018 by Synopsys Inc.
|
||||
ALL RIGHTS RESERVED
|
||||
|
||||
@@ -7,38 +7,99 @@ This program is proprietary and confidential information of Synopsys Inc.
|
||||
and may be used and disclosed only as authorized in a license agreement
|
||||
controlling such use and disclosure.
|
||||
|
||||
Parsing design file '../rtl/sync_fifo_128_to_64.v'
|
||||
Parsing design file '../rtl/sync_fifo.v'
|
||||
Parsing design file '../rtl/rchannel.v'
|
||||
Parsing design file '../tb/tb_rchannel.v'
|
||||
Parsing design file '../rtl/async_fifo.v'
|
||||
Parsing design file '../rtl/array_ctrl.v'
|
||||
Parsing design file '../rtl/array_status_ctrl.v'
|
||||
Parsing design file '../rtl/array_wr.v'
|
||||
Parsing design file '../rtl/array_rd.v'
|
||||
Parsing design file '../rtl/array_ref.v'
|
||||
Parsing design file '../rtl/array_mux.v'
|
||||
Parsing design file '../tb/tb_array_ctrl.v'
|
||||
Top Level Modules:
|
||||
tb_rchannel
|
||||
tb_array_ctrl
|
||||
TimeScale is 1 ns / 1 ps
|
||||
Starting vcs inline pass...
|
||||
1 module and 0 UDP read.
|
||||
recompiling module tb_rchannel
|
||||
recompiling module tb_array_ctrl
|
||||
make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
make[1]: Entering directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
||||
if [ -x ../simv ]; then chmod -x ../simv; fi
|
||||
g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _25796_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _5573_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
../simv up to date
|
||||
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/IC_PRJ/sim/csrc'
|
||||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025
|
||||
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 13 16:31 2025
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* : Create FSDB file 'tb.fsdb'
|
||||
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
|
||||
*Verdi* : Begin traversing the scope (tb_array_ctrl), layer (0).
|
||||
*Verdi* : Enable +all dumping.
|
||||
*Verdi* : End of traversing.
|
||||
$finish called from file "../tb/tb_rchannel.v", line 64.
|
||||
$finish at simulation time 365000
|
||||
VCD+ Writer O-2018.09-1_Full64 Copyright (c) 1991-2018 by Synopsys Inc.
|
||||
Time: 0, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 00, 列地址(读): 00
|
||||
Time: 354000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 5678, 列地址(写): 0b, 列地址(读): 00
|
||||
Time: 359000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0b, 列地址(读): 00
|
||||
Time: 376000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0b, 列地址(读): 00
|
||||
Time: 379000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0b, 列地址(读): 00
|
||||
Time: 381000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0c, 列地址(读): 00
|
||||
Time: 384000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0c, 列地址(读): 00
|
||||
Time: 386000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0d, 列地址(读): 00
|
||||
Time: 389000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 5678, 列地址(写): 0d, 列地址(读): 00
|
||||
Time: 404000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 5678, 列地址(写): 0d, 列地址(读): 00
|
||||
Time: 419000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 0d, 列地址(读): 00
|
||||
Time: 421000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 5678, 列地址(写): 0d, 列地址(读): 00
|
||||
Time: 721000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 1234, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 726000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 1234, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 744000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 1234, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 746000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 1234, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 766000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 1234, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 781000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 0a, 列地址(读): 00
|
||||
Time: 1004000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1009000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1026000, 写有效: 1, 读有效: 1, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1029000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1049000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1064000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1066000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 1234, 列地址(写): 0a, 列地址(读): 0e
|
||||
Time: 1166000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1169000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1186000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1189000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1209000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1224000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1226000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1446000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1696000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1796000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0e
|
||||
Time: 1846000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 1, 行地址: def0, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1849000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 0, 行地址: def0, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1866000, 写有效: 1, 读有效: 1, 刷新使能: 1, CSN: 0, 行地址: def0, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1869000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 0, 行地址: def0, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1889000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 1, 行地址: def0, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1904000, 写有效: 1, 读有效: 0, 刷新使能: 1, CSN: 1, 行地址: 0000, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 1906000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 9abc, 列地址(写): 0e, 列地址(读): 0f
|
||||
Time: 2106000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2111000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2129000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2131000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2151000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2166000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2169000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2371000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2389000, 写有效: 0, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2391000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 0, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2411000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: ffff, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2426000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: 0000, 列地址(写): 3f, 列地址(读): 0f
|
||||
Time: 2429000, 写有效: 1, 读有效: 0, 刷新使能: 0, CSN: 1, 行地址: def0, 列地址(写): 3f, 列地址(读): 0f
|
||||
所有测试场景完成！
|
||||
$finish called from file "../tb/tb_array_ctrl.v", line 207.
|
||||
$finish at simulation time 3648750
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 365000 ps
|
||||
CPU Time: 0.480 seconds; Data structure size: 0.0Mb
|
||||
Wed Aug 6 22:32:19 2025
|
||||
CPU time: .521 seconds to compile + .480 seconds to elab + .391 seconds to link + .525 seconds in simulation
|
||||
Time: 3648750 ps
|
||||
CPU Time: 2.050 seconds; Data structure size: 0.0Mb
|
||||
Wed Aug 13 16:31:01 2025
|
||||
CPU time: 1.470 seconds to compile + 1.041 seconds to elab + .287 seconds to link + 2.081 seconds in simulation
|
||||
|
||||
@@ -2,12 +2,28 @@
|
||||
Command arguments:
|
||||
+define+verilog
|
||||
-f filelist.f
|
||||
../rtl/sync_fifo_128_to_64.v
|
||||
../rtl/sync_fifo.v
|
||||
../rtl/rchannel.v
|
||||
../tb/tb_rchannel.v
|
||||
../rtl/async_fifo.v
|
||||
../rtl/array_ctrl.v
|
||||
../rtl/array_status_ctrl.v
|
||||
../rtl/array_wr.v
|
||||
../rtl/array_rd.v
|
||||
../rtl/array_ref.v
|
||||
../rtl/array_mux.v
|
||||
../tb/tb_array_ctrl.v
|
||||
|
||||
|
||||
*Error* nonconstant index
|
||||
"../rtl/async_fifo.v", 79:
|
||||
|
||||
*Error* nonconstant index
|
||||
"../rtl/async_fifo.v", 80:
|
||||
|
||||
*Error* nonconstant index
|
||||
"../rtl/async_fifo.v", 82:
|
||||
|
||||
*Error* nonconstant index
|
||||
"../rtl/async_fifo.v", 83:
|
||||
Highest level modules:
|
||||
tb_rchannel
|
||||
tb_array_ctrl
|
||||
|
||||
Total 0 error(s), 0 warning(s)
|
||||
Total 4 error(s), 0 warning(s)
|
||||
|
||||
@@ -8,5 +8,3 @@ This software may only be used in accordance with the terms and conditions of a
|
||||
All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
|
||||
Info: Running in interactive mode.
|
||||
Info: Running in interactive mode.
|
||||
|
||||
@@ -18,16 +18,16 @@ AnnotationShow = 0
|
||||
Console = FALSE
|
||||
powerDumped = 0
|
||||
[hb]
|
||||
postSimFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
syncTime = 90000
|
||||
viewport = 0 20 1914 774 0 0 265 1912
|
||||
activeNode = "tb_rchannel"
|
||||
activeScope = "tb_rchannel"
|
||||
activeFile = "../tb/tb_rchannel.v"
|
||||
postSimFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb
|
||||
syncTime = 2168750
|
||||
viewport = 0 20 1918 778 0 0 253 898
|
||||
activeNode = "tb_array_ctrl"
|
||||
activeScope = "tb_array_ctrl"
|
||||
activeFile = "../tb/tb_array_ctrl.v"
|
||||
interactiveMode = False
|
||||
viewType = Source
|
||||
simulatorMode = False
|
||||
sourceBeginLine = 0
|
||||
sourceBeginLine = 2
|
||||
baMode = False
|
||||
srcLineNum = True
|
||||
AutoWrap = True
|
||||
@@ -44,23 +44,23 @@ DnDtraceCrossHierOnly = True
|
||||
traceIncTopPort = False
|
||||
leadingZero = False
|
||||
signalPane = False
|
||||
Scope1 = "tb_rchannel"
|
||||
rangeSelection = 1 1 1 5 1 1
|
||||
Scope1 = "tb_array_ctrl"
|
||||
multipleSelection = 1 2 2 0 0
|
||||
sdfCheckUndef = FALSE
|
||||
simFlow = FALSE
|
||||
[hb.design]
|
||||
importCmd = "-f" "filelist.f"
|
||||
invokeDir = /home/ICer/ic_prjs/mc/IC_PRJ/sim
|
||||
[hb.sourceTab.1]
|
||||
scope = tb_rchannel
|
||||
File = /home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v
|
||||
Line = 1
|
||||
scope = tb_array_ctrl
|
||||
File = /home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_array_ctrl.v
|
||||
Line = 3
|
||||
[nMemoryManager]
|
||||
WaveformFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb
|
||||
WaveformFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb
|
||||
UserActionNum = 0
|
||||
nMemWindowNum = 0
|
||||
[wave.0]
|
||||
viewPort = 0 27 1914 615 285 195
|
||||
viewPort = 0 27 1918 673 227 36
|
||||
primaryWindow = TRUE
|
||||
SessionFile = /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/novas_autosave.ses.wave.0
|
||||
displayGrid = FALSE
|
||||
|
||||
File diff suppressed because one or more lines are too long
Binary file not shown.
|
Before Width: | Height: | Size: 121 KiB After Width: | Height: | Size: 107 KiB |
@@ -2,11 +2,11 @@ Magic 271485
|
||||
Revision Verdi_O-2018.09-SP2
|
||||
|
||||
; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
|
||||
viewPort 0 27 1914 615 285 195
|
||||
viewPort 0 27 1918 673 227 36
|
||||
|
||||
; File list:
|
||||
; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
|
||||
openDirFile -d / "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
openDirFile -d / "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb"
|
||||
|
||||
; file time scale:
|
||||
; fileTimeScale ### s|ms|us|ns|ps
|
||||
@@ -16,16 +16,16 @@ signalSpacing 5
|
||||
|
||||
; windowTimeUnit is used for zoom, cursor & marker
|
||||
; waveform viewport range
|
||||
zoom 0.000000 659986.290231
|
||||
cursor 90000.000000
|
||||
zoom 0.000000 3478035.391566
|
||||
cursor 2168750.000000
|
||||
marker 0.000000
|
||||
|
||||
; user define markers
|
||||
; userMarker time_pos marker_name color linestyle
|
||||
; visible top row signal index
|
||||
top 16
|
||||
top 1
|
||||
; marker line index
|
||||
markerPos 44
|
||||
markerPos 28
|
||||
|
||||
; event list
|
||||
; addEvent event_name event_expression
|
||||
@@ -46,66 +46,48 @@ curSTATUS ByChange
|
||||
|
||||
|
||||
addGroup "G1"
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arcaddr[5:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arlen[7:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/arraddr[15:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/array2axi_rdata[127:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/array2axi_rdata_valid
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/axi_s_araddr[25:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/axi_s_arlen[7:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/axi_s_arready
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/axi_s_arvalid
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/axi_s_rdata[63:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/axi_s_rlast
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/axi_s_rvalid
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/clk
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/cur_state[1:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/next_state[1:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/rcaddr[5:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/rdata_cnt[7:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/reof
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/rframe_cnt[6:0]
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/rframe_data[159:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/rframe_ready
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/rframe_valid
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/rraddr[15:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/rsof
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/rst_n
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_ar_empty
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_ar_full
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_ar_rd_data[29:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_ar_rd_en
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_ar_wr_data[29:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_ar_wr_en
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_arlen_empty
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_arlen_full
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_arlen_rd_data[7:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_arlen_rd_en
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_arlen_wr_data[7:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_arlen_wr_en
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_r_empty
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_r_full
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_r_rd_data[63:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_r_rd_en
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/sync_fifo_r_wr_data[127:0]
|
||||
addSignal -h 15 /tb_rchannel/u_rchannel/sync_fifo_r_wr_en
|
||||
addSignal -h 15 -UNSIGNED -HEX /tb_rchannel/u_rchannel/wdata[127:0]
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb"
|
||||
addSignal -h 15 /tb_array_ctrl/array2axi_rdata[127:0]
|
||||
addSignal -h 15 -holdScope array2axi_rdata_valid
|
||||
addSignal -h 15 -holdScope array_caddr_rd[5:0]
|
||||
addSignal -h 15 -holdScope array_caddr_vld_rd
|
||||
addSignal -h 15 -holdScope array_caddr_vld_wr
|
||||
addSignal -h 15 -holdScope array_caddr_wr[5:0]
|
||||
addSignal -h 15 -holdScope array_csn
|
||||
addSignal -h 15 -holdScope array_inner_ref_sel
|
||||
addSignal -h 15 -holdScope array_inner_tras[7:0]
|
||||
addSignal -h 15 -holdScope array_inner_trcd_rd[7:0]
|
||||
addSignal -h 15 -holdScope array_inner_trcd_wr[7:0]
|
||||
addSignal -h 15 -holdScope array_inner_tref0[24:0]
|
||||
addSignal -h 15 -holdScope array_inner_tref1[24:0]
|
||||
addSignal -h 15 -holdScope array_inner_trp[7:0]
|
||||
addSignal -h 15 -holdScope array_inner_trtp[7:0]
|
||||
addSignal -h 15 -holdScope array_inner_twr[7:0]
|
||||
addSignal -h 15 -holdScope array_raddr[15:0]
|
||||
addSignal -h 15 -holdScope array_rdata[127:0]
|
||||
addSignal -h 15 -holdScope array_rdata_vld
|
||||
addSignal -h 15 -holdScope array_ref_en
|
||||
addSignal -h 15 -holdScope array_wdata[127:0]
|
||||
addSignal -h 15 -holdScope array_wdata_vld
|
||||
addSignal -h 15 -holdScope axi2array_frame_data[152:0]
|
||||
addSignal -h 15 -holdScope axi2array_frame_ready
|
||||
addSignal -h 15 -holdScope axi2array_frame_valid
|
||||
addSignal -h 15 -holdScope clk
|
||||
addSignal -h 15 -holdScope mc_work_en
|
||||
addSignal -h 15 -holdScope rst_n
|
||||
addGroup "G2"
|
||||
|
||||
; getSignalForm Scope Hierarchy Status
|
||||
; active file of getSignalForm
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb"
|
||||
activeDirFile "" "/home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb"
|
||||
|
||||
GETSIGNALFORM_SCOPE_HIERARCHY_BEGIN
|
||||
getSignalForm close
|
||||
|
||||
"/tb_rchannel"
|
||||
"/tb_rchannel/u_rchannel"
|
||||
"/tb_array_ctrl"
|
||||
|
||||
SCOPE_LIST_BEGIN
|
||||
"/tb_rchannel"
|
||||
"/tb_rchannel/u_rchannel"
|
||||
"/tb_array_ctrl"
|
||||
SCOPE_LIST_END
|
||||
|
||||
GETSIGNALFORM_SCOPE_HIERARCHY_END
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -f filelist.f -ssf tb.fsdb
|
||||
uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64)
|
||||
au time 532.936489 24.438809 15.829228 delta 612864000 612864000 total 1037946880 1037946880
|
||||
au time 232.879158 5.609200 4.987353 delta 605061120 605061120 total 1030144000 1030144000
|
||||
|
||||
@@ -2,224 +2,87 @@ debImport "-f" "filelist.f"
|
||||
debLoadSimResult /home/ICer/ic_prjs/mc/IC_PRJ/sim/tb.fsdb
|
||||
wvCreateWindow
|
||||
wvGetSignalOpen -win $_nWave2
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel"
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_rchannel/u_rchannel"
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvGetSignalSetScope -win $_nWave2 "/tb_array_ctrl"
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvAddSignal -win $_nWave2 -clear
|
||||
wvAddSignal -win $_nWave2 -group {"G1" \
|
||||
{/tb_rchannel/u_rchannel/arcaddr\[5:0\]} \
|
||||
{/tb_rchannel/u_rchannel/arlen\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/arraddr\[15:0\]} \
|
||||
{/tb_rchannel/u_rchannel/array2axi_rdata\[127:0\]} \
|
||||
{/tb_rchannel/u_rchannel/array2axi_rdata_valid} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_araddr\[25:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arlen\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arready} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arvalid} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rdata\[63:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rlast} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rvalid} \
|
||||
{/tb_rchannel/u_rchannel/clk} \
|
||||
{/tb_rchannel/u_rchannel/cur_state\[1:0\]} \
|
||||
{/tb_rchannel/u_rchannel/next_state\[1:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rcaddr\[5:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rdata_cnt\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/reof} \
|
||||
{/tb_rchannel/u_rchannel/rframe_cnt\[6:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rframe_data\[159:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rframe_ready} \
|
||||
{/tb_rchannel/u_rchannel/rframe_valid} \
|
||||
{/tb_rchannel/u_rchannel/rraddr\[15:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rsof} \
|
||||
{/tb_rchannel/u_rchannel/rst_n} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_rd_data\[29:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_wr_data\[29:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_rd_data\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_wr_data\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_rd_data\[63:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_wr_data\[127:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/wdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array2axi_rdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array2axi_rdata_valid} \
|
||||
{/tb_array_ctrl/array_caddr_rd\[5:0\]} \
|
||||
{/tb_array_ctrl/array_caddr_vld_rd} \
|
||||
{/tb_array_ctrl/array_caddr_vld_wr} \
|
||||
{/tb_array_ctrl/array_caddr_wr\[5:0\]} \
|
||||
{/tb_array_ctrl/array_csn} \
|
||||
{/tb_array_ctrl/array_inner_ref_sel} \
|
||||
{/tb_array_ctrl/array_inner_tras\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trcd_rd\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trcd_wr\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_tref0\[24:0\]} \
|
||||
{/tb_array_ctrl/array_inner_tref1\[24:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trp\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trtp\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_twr\[7:0\]} \
|
||||
{/tb_array_ctrl/array_raddr\[15:0\]} \
|
||||
{/tb_array_ctrl/array_rdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array_rdata_vld} \
|
||||
{/tb_array_ctrl/array_ref_en} \
|
||||
{/tb_array_ctrl/array_wdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array_wdata_vld} \
|
||||
{/tb_array_ctrl/axi2array_frame_data\[152:0\]} \
|
||||
{/tb_array_ctrl/axi2array_frame_ready} \
|
||||
{/tb_array_ctrl/axi2array_frame_valid} \
|
||||
{/tb_array_ctrl/clk} \
|
||||
{/tb_array_ctrl/mc_work_en} \
|
||||
{/tb_array_ctrl/rst_n} \
|
||||
}
|
||||
wvAddSignal -win $_nWave2 -group {"G2" \
|
||||
}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 \
|
||||
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 \
|
||||
40 41 42 43 44 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
18 19 20 21 22 23 24 25 26 27 28 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvAddSignal -win $_nWave2 -clear
|
||||
wvAddSignal -win $_nWave2 -group {"G1" \
|
||||
{/tb_rchannel/u_rchannel/arcaddr\[5:0\]} \
|
||||
{/tb_rchannel/u_rchannel/arlen\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/arraddr\[15:0\]} \
|
||||
{/tb_rchannel/u_rchannel/array2axi_rdata\[127:0\]} \
|
||||
{/tb_rchannel/u_rchannel/array2axi_rdata_valid} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_araddr\[25:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arlen\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arready} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_arvalid} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rdata\[63:0\]} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rlast} \
|
||||
{/tb_rchannel/u_rchannel/axi_s_rvalid} \
|
||||
{/tb_rchannel/u_rchannel/clk} \
|
||||
{/tb_rchannel/u_rchannel/cur_state\[1:0\]} \
|
||||
{/tb_rchannel/u_rchannel/next_state\[1:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rcaddr\[5:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rdata_cnt\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/reof} \
|
||||
{/tb_rchannel/u_rchannel/rframe_cnt\[6:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rframe_data\[159:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rframe_ready} \
|
||||
{/tb_rchannel/u_rchannel/rframe_valid} \
|
||||
{/tb_rchannel/u_rchannel/rraddr\[15:0\]} \
|
||||
{/tb_rchannel/u_rchannel/rsof} \
|
||||
{/tb_rchannel/u_rchannel/rst_n} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_rd_data\[29:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_wr_data\[29:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_ar_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_rd_data\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_wr_data\[7:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_arlen_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_empty} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_full} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_rd_data\[63:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_rd_en} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_wr_data\[127:0\]} \
|
||||
{/tb_rchannel/u_rchannel/sync_fifo_r_wr_en} \
|
||||
{/tb_rchannel/u_rchannel/wdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array2axi_rdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array2axi_rdata_valid} \
|
||||
{/tb_array_ctrl/array_caddr_rd\[5:0\]} \
|
||||
{/tb_array_ctrl/array_caddr_vld_rd} \
|
||||
{/tb_array_ctrl/array_caddr_vld_wr} \
|
||||
{/tb_array_ctrl/array_caddr_wr\[5:0\]} \
|
||||
{/tb_array_ctrl/array_csn} \
|
||||
{/tb_array_ctrl/array_inner_ref_sel} \
|
||||
{/tb_array_ctrl/array_inner_tras\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trcd_rd\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trcd_wr\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_tref0\[24:0\]} \
|
||||
{/tb_array_ctrl/array_inner_tref1\[24:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trp\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_trtp\[7:0\]} \
|
||||
{/tb_array_ctrl/array_inner_twr\[7:0\]} \
|
||||
{/tb_array_ctrl/array_raddr\[15:0\]} \
|
||||
{/tb_array_ctrl/array_rdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array_rdata_vld} \
|
||||
{/tb_array_ctrl/array_ref_en} \
|
||||
{/tb_array_ctrl/array_wdata\[127:0\]} \
|
||||
{/tb_array_ctrl/array_wdata_vld} \
|
||||
{/tb_array_ctrl/axi2array_frame_data\[152:0\]} \
|
||||
{/tb_array_ctrl/axi2array_frame_ready} \
|
||||
{/tb_array_ctrl/axi2array_frame_valid} \
|
||||
{/tb_array_ctrl/clk} \
|
||||
{/tb_array_ctrl/mc_work_en} \
|
||||
{/tb_array_ctrl/rst_n} \
|
||||
}
|
||||
wvAddSignal -win $_nWave2 -group {"G2" \
|
||||
}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 \
|
||||
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 \
|
||||
40 41 42 43 44 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 44)}
|
||||
18 19 20 21 22 23 24 25 26 27 28 )}
|
||||
wvSetPosition -win $_nWave2 {("G1" 28)}
|
||||
wvGetSignalClose -win $_nWave2
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 2182.373767 -snap {("G1" 16)}
|
||||
srcTBInvokeSim
|
||||
srcTBRunSim
|
||||
verdiDockWidgetSetCurTab -dock windowDock_nWave_2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
verdiDockWidgetMaximize -dock windowDock_nWave_2
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 24 )}
|
||||
wvSetCursor -win $_nWave2 169335.416349 -snap {("G1" 18)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 22
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 20 )}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
@@ -227,214 +90,60 @@ wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSetCursor -win $_nWave2 115310.104685 -snap {("G1" 14)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvZoomIn -win $_nWave2
|
||||
wvZoomIn -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvZoomOut -win $_nWave2
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 44 )}
|
||||
wvSetCursor -win $_nWave2 46874.026295 -snap {("G1" 39)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvSetCursor -win $_nWave2 191246.027283 -snap {("G1" 3)}
|
||||
wvSetCursor -win $_nWave2 235776.352263 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 283119.118821 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 305149.911179 -snap {("G1" 4)}
|
||||
wvSetCursor -win $_nWave2 353430.158263 -snap {("G1" 4)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 144372.000988 -snap {("G1" 37)}
|
||||
wvSetCursor -win $_nWave2 195464.689649 -snap {("G1" 40)}
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 40 )}
|
||||
wvSetCursor -win $_nWave2 201089.572805 -snap {("G1" 40)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 20 )}
|
||||
wvSetCursor -win $_nWave2 61404.974446 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 63748.675761 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 82029.546016 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 101247.896797 -snap {("G1" 20)}
|
||||
wvSetCursor -win $_nWave2 117185.065737 -snap {("G1" 20)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 815148.074696 -snap {("G1" 1)}
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSetCursor -win $_nWave2 2125359.901563 -snap {("G1" 17)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 19 )}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvSelectSignal -win $_nWave2 {( "G1" 17 )}
|
||||
wvSetCursor -win $_nWave2 1560739.024699 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 1556468.876889 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 1866054.593142 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 1891675.480005 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 2053941.096800 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 2132938.831292 -snap {("G1" 17)}
|
||||
wvSetCursor -win $_nWave2 2235422.378741 -snap {("G1" 17)}
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollUp -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 0
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
wvScrollDown -win $_nWave2 1
|
||||
debExit
|
||||
|
||||
Reference in New Issue
Block a user