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Finish top-module(axi_slave array_ctrl apb_cfg): 2025-08-13 16:39:12

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Core_kingdom
2025-08-13 16:39:12 +08:00
parent c84096d1f9
commit de5211af62
69 changed files with 3355 additions and 1631 deletions
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12
sim/simv.daidir/debug_dump/src_files_verilog
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@@ -1,4 +1,8 @@
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/rchannel.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/sync_fifo_128_to_64.v
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_rchannel.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_ctrl.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_mux.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_rd.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_ref.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_status_ctrl.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/array_wr.v
/home/ICer/ic_prjs/mc/IC_PRJ/rtl/async_fifo.v
/home/ICer/ic_prjs/mc/IC_PRJ/tb/tb_array_ctrl.v