Finish top-module(axi_slave array_ctrl apb_cfg): 2025-08-13 16:39:12

sim/verdiLog/compiler.log

@@ -2,12 +2,28 @@
 Command arguments:
     +define+verilog
     -f filelist.f
-        ../rtl/sync_fifo_128_to_64.v
-        ../rtl/sync_fifo.v
-        ../rtl/rchannel.v
-        ../tb/tb_rchannel.v
+        ../rtl/async_fifo.v
+        ../rtl/array_ctrl.v
+        ../rtl/array_status_ctrl.v
+        ../rtl/array_wr.v
+        ../rtl/array_rd.v
+        ../rtl/array_ref.v
+        ../rtl/array_mux.v
+        ../tb/tb_array_ctrl.v
 
+
+*Error* nonconstant index
+"../rtl/async_fifo.v", 79: 
+
+*Error* nonconstant index
+"../rtl/async_fifo.v", 80: 
+
+*Error* nonconstant index
+"../rtl/async_fifo.v", 82: 
+
+*Error* nonconstant index
+"../rtl/async_fifo.v", 83: 
 Highest level modules:
-tb_rchannel
+tb_array_ctrl
 
-Total	0 error(s),   0 warning(s)
+Total	4 error(s),   0 warning(s)