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Core_kingdom
2025-08-06 15:23:07 +08:00
parent 027a9ee17a
commit ef832709eb
4 changed files with 121 additions and 49 deletions
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114
rtl/frame_arbiter.v Normal file
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@@ -0,0 +1,114 @@
module frame_arbiter(
input clk,
input rst_n,
input wframe_valid,
input [159:0] wframe_data,
output wframe_ready,
input rframe_valid,
input [159:0] rframe_data,
output rframe_ready,
output axi2array_frame_valid,
output [152:0] axi2array_frame_data,
input axi2array_frame_ready,
input mc_work_en,
input [1:0] axi_bus_rw_priority
);
reg [1:0] cur_state,next_state;
localparam [1:0] FARB_IDLE = 2'b00;
localparam [1:0] FARB_WR = 2'b01;
localparam [1:0] FARB_RD = 2'b10;
reg rw_round_robin;
reg [6:0] frame_cnt;
wire rw_flag;
wire [151:0] frame;
wire [7:0] len;
assign axi2array_frame_valid = (cur_state == FARB_WR) && wframe_valid ||
(cur_state == FARB_RD) && rframe_valid;
assign axi2array_frame_data = {rw_frag,frame};
assign wframe_ready = (cur_state == FARB_WR) && axi2array_frame_ready;
assign rframe_ready = (cur_state == FARB_RD) && axi2array_frame_ready;
assign rwflag = (cur_state == FARB_WR);
assign frame = (cur_state == FARB_WR) ? wframe_data[159:8]:
rframe_data[159:8];
assign len = (cur_state == FARB_WR) ? wframe_data[7:0]:
rframe_data[7:0];
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cur_state <= 'd0;
end else begin
cur_state <= next_state;
end
end
always@(*) begin
case(cur_state)
FARB_IDLE : begin
if(wframe_valid && rframe_valid) begin
case(axi_bus_rw_priority)
2'b00: begin
next_state = FARB_RD;
end
2'b01: begin
next_state = FARB_WR;
end
2'b10: begin
next_state = rw_round_robin ? FARB_WR : FARB_RD;
end
endcase
end else if (wframe_valid) begin
next_state = FARB_WR;
end else if (rframe_valid) begin
next_state = FARB_RD;
end else begin
next_state = FARB_IDLE;
end
end
FARB_WR : begin if (axi2array_frame_valid && axi2array_frame_ready &&
(frame_cnt == (len>>1))) begin
next_state = FARB_IDLE;
end else begin
next_state = FARB_WR;
end
end
FARB_RD :begin if (axi2array_frame_valid && axi2array_frame_ready &&
(frame_cnt == (len>>1))) begin
next_state = FARB_IDLE;
end else begin
next_state = FARB_RD;
end
end
default : begin
next_state = FARB_IDLE;
end
endcase
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rw_round_robin <= 1'b1;
end else if(wframe_valid && rframe_valid && (cur_state == FARB_IDLE)) begin
rw_round_robin <= ~rw_round_robin;
end
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
frame_cnt <= 'd0;
end else if (axi2array_frame_valid && axi2array_frame_ready) begin
if(frame_cnt == (len >> 1)) begin
frame_cnt <= 'd0;
end else begin
frame_cnt <= frame_cnt + 1'b1;
end
end
end
endmodule

1
sim/Makefile
View File

@@ -8,7 +8,6 @@ vcs :
vcs \ vcs \
-f filelist.f \ -f filelist.f \
-timescale=1ns/1ps \ -timescale=1ns/1ps \
-debug -o simv\
-full64 -R +vc +v2k -sverilog -debug_access+all\ -full64 -R +vc +v2k -sverilog -debug_access+all\
| tee vcs.log | tee vcs.log
#------------------------------------------------------------------------------------------------------- #-------------------------------------------------------------------------------------------------------

9
sim/filelist.f
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@@ -1,12 +1,13 @@
../rtl/sync_fifo_128_to_64.v #../rtl/sync_fifo_128_to_64.v
#../rtl/sync_fifo_64_to_128.v #../rtl/sync_fifo_64_to_128.v
#../rtl/async_fifo.v #../rtl/async_fifo.v
#../rtl/wchannel.v #../rtl/wchannel.v
../rtl/sync_fifo.v #../rtl/sync_fifo.v
../rtl/rchannel.v #../rtl/rchannel.v
../rtl/frame_arbiter.v
#../tb/tb_sync_fifo_128_to_64.v #../tb/tb_sync_fifo_128_to_64.v
#../tb/tb_async_fifo.v #../tb/tb_async_fifo.v
#../tb/tb_sync_fifo_64_to_128.v #../tb/tb_sync_fifo_64_to_128.v
#../tb/tb_sync_fifo.v #../tb/tb_sync_fifo.v
#../tb/tb_wchannel.v #../tb/tb_wchannel.v
../tb/tb_rchannel.v #../tb/tb_rchannel.v

46
sim/vcs.log
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@@ -1,10 +1,5 @@
Warning-[DBGACC_DBG] Multiple debug options being used
The debug switches '-debug_access' and '-debug*' are being used together.
For better performance, consider using only '-debug_access'.
Chronologic VCS (TM) Chronologic VCS (TM)
Version O-2018.09-1_Full64 -- Tue Aug 5 21:54:17 2025 Version O-2018.09-1_Full64 -- Wed Aug 6 15:11:28 2025
Copyright (c) 1991-2018 by Synopsys Inc. Copyright (c) 1991-2018 by Synopsys Inc.
ALL RIGHTS RESERVED ALL RIGHTS RESERVED
@@ -12,41 +7,4 @@ This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure. controlling such use and disclosure.
Parsing design file '../rtl/sync_fifo_128_to_64.v' CPU time: .262 seconds to compile
Parsing design file '../rtl/sync_fifo.v'
Parsing design file '../rtl/rchannel.v'
Parsing design file '../tb/tb_rchannel.v'
Top Level Modules:
tb_rchannel
TimeScale is 1 ns / 1 ps
Starting vcs inline pass...
1 module and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
rm -f _csrc0.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib _12247_archive_1.so _prev_archive_1.so _csrc0.so SIM_l.o _csrc0.so rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
../simv up to date
make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi* : Create FSDB file 'tb.fsdb'
*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
*Verdi* : Enable +all dumping.
*Verdi* : End of traversing.
$finish called from file "../tb/tb_rchannel.v", line 64.
$finish at simulation time 365000
V C S S i m u l a t i o n R e p o r t
Time: 365000 ps
CPU Time: 0.570 seconds; Data structure size: 0.0Mb
Tue Aug 5 21:54:18 2025
CPU time: .334 seconds to compile + .316 seconds to elab + .256 seconds to link + .607 seconds in simulation