Auto-commit: 2025-08-06 15:23:07
This commit is contained in:
Core_kingdom
114
rtl/frame_arbiter.v
Normal file
114
rtl/frame_arbiter.v
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@@ -0,0 +1,114 @@
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module frame_arbiter(
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input clk,
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input rst_n,
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input wframe_valid,
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input [159:0] wframe_data,
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output wframe_ready,
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input rframe_valid,
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input [159:0] rframe_data,
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output rframe_ready,
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output axi2array_frame_valid,
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output [152:0] axi2array_frame_data,
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input axi2array_frame_ready,
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input mc_work_en,
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input [1:0] axi_bus_rw_priority
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);
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reg [1:0] cur_state,next_state;
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localparam [1:0] FARB_IDLE = 2'b00;
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localparam [1:0] FARB_WR = 2'b01;
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localparam [1:0] FARB_RD = 2'b10;
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reg rw_round_robin;
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reg [6:0] frame_cnt;
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wire rw_flag;
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wire [151:0] frame;
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wire [7:0] len;
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assign axi2array_frame_valid = (cur_state == FARB_WR) && wframe_valid ||
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(cur_state == FARB_RD) && rframe_valid;
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assign axi2array_frame_data = {rw_frag,frame};
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assign wframe_ready = (cur_state == FARB_WR) && axi2array_frame_ready;
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assign rframe_ready = (cur_state == FARB_RD) && axi2array_frame_ready;
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assign rwflag = (cur_state == FARB_WR);
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assign frame = (cur_state == FARB_WR) ? wframe_data[159:8]:
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rframe_data[159:8];
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assign len = (cur_state == FARB_WR) ? wframe_data[7:0]:
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rframe_data[7:0];
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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cur_state <= 'd0;
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end else begin
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cur_state <= next_state;
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end
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end
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always@(*) begin
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case(cur_state)
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FARB_IDLE : begin
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if(wframe_valid && rframe_valid) begin
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case(axi_bus_rw_priority)
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2'b00: begin
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next_state = FARB_RD;
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end
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2'b01: begin
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next_state = FARB_WR;
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end
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2'b10: begin
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next_state = rw_round_robin ? FARB_WR : FARB_RD;
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end
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endcase
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end else if (wframe_valid) begin
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next_state = FARB_WR;
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end else if (rframe_valid) begin
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next_state = FARB_RD;
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end else begin
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next_state = FARB_IDLE;
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end
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end
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FARB_WR : begin if (axi2array_frame_valid && axi2array_frame_ready &&
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(frame_cnt == (len>>1))) begin
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next_state = FARB_IDLE;
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end else begin
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next_state = FARB_WR;
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end
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end
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FARB_RD :begin if (axi2array_frame_valid && axi2array_frame_ready &&
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(frame_cnt == (len>>1))) begin
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next_state = FARB_IDLE;
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end else begin
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next_state = FARB_RD;
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end
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end
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default : begin
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next_state = FARB_IDLE;
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end
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endcase
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rw_round_robin <= 1'b1;
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end else if(wframe_valid && rframe_valid && (cur_state == FARB_IDLE)) begin
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rw_round_robin <= ~rw_round_robin;
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end
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end
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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frame_cnt <= 'd0;
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end else if (axi2array_frame_valid && axi2array_frame_ready) begin
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if(frame_cnt == (len >> 1)) begin
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frame_cnt <= 'd0;
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end else begin
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frame_cnt <= frame_cnt + 1'b1;
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end
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end
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end
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endmodule
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@@ -8,7 +8,6 @@ vcs :
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vcs \
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-f filelist.f \
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-timescale=1ns/1ps \
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-debug -o simv\
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-full64 -R +vc +v2k -sverilog -debug_access+all\
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| tee vcs.log
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#-------------------------------------------------------------------------------------------------------
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@@ -1,12 +1,13 @@
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../rtl/sync_fifo_128_to_64.v
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#../rtl/sync_fifo_128_to_64.v
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#../rtl/sync_fifo_64_to_128.v
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#../rtl/async_fifo.v
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#../rtl/wchannel.v
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../rtl/sync_fifo.v
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../rtl/rchannel.v
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#../rtl/sync_fifo.v
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#../rtl/rchannel.v
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../rtl/frame_arbiter.v
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#../tb/tb_sync_fifo_128_to_64.v
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#../tb/tb_async_fifo.v
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#../tb/tb_sync_fifo_64_to_128.v
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#../tb/tb_sync_fifo.v
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#../tb/tb_wchannel.v
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../tb/tb_rchannel.v
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#../tb/tb_rchannel.v
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46
sim/vcs.log
46
sim/vcs.log
@@ -1,10 +1,5 @@
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Warning-[DBGACC_DBG] Multiple debug options being used
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The debug switches '-debug_access' and '-debug*' are being used together.
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For better performance, consider using only '-debug_access'.
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Chronologic VCS (TM)
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Version O-2018.09-1_Full64 -- Tue Aug 5 21:54:17 2025
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Version O-2018.09-1_Full64 -- Wed Aug 6 15:11:28 2025
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Copyright (c) 1991-2018 by Synopsys Inc.
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ALL RIGHTS RESERVED
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@@ -12,41 +7,4 @@ This program is proprietary and confidential information of Synopsys Inc.
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and may be used and disclosed only as authorized in a license agreement
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controlling such use and disclosure.
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Parsing design file '../rtl/sync_fifo_128_to_64.v'
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Parsing design file '../rtl/sync_fifo.v'
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Parsing design file '../rtl/rchannel.v'
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Parsing design file '../tb/tb_rchannel.v'
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Top Level Modules:
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tb_rchannel
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TimeScale is 1 ns / 1 ps
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Starting vcs inline pass...
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1 module and 0 UDP read.
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However, due to incremental compilation, no re-compilation is necessary.
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make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
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make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
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make[1]: Entering directory '/home/ICer/ic_prjs/mc/sim/csrc'
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rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
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ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
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rm -f _csrc0.so
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if [ -x ../simv ]; then chmod -x ../simv; fi
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g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib _12247_archive_1.so _prev_archive_1.so _csrc0.so SIM_l.o _csrc0.so rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
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../simv up to date
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make[1]: Leaving directory '/home/ICer/ic_prjs/mc/sim/csrc'
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Chronologic VCS simulator copyright 1991-2018
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Contains Synopsys proprietary information.
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Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 5 21:54 2025
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*Verdi* Loading libsscore_vcs201809.so
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FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
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(C) 1996 - 2019 by Synopsys, Inc.
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*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
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*Verdi* : Create FSDB file 'tb.fsdb'
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*Verdi* : Begin traversing the scope (tb_rchannel), layer (0).
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*Verdi* : Enable +all dumping.
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*Verdi* : End of traversing.
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$finish called from file "../tb/tb_rchannel.v", line 64.
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$finish at simulation time 365000
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V C S S i m u l a t i o n R e p o r t
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Time: 365000 ps
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CPU Time: 0.570 seconds; Data structure size: 0.0Mb
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Tue Aug 5 21:54:18 2025
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CPU time: .334 seconds to compile + .316 seconds to elab + .256 seconds to link + .607 seconds in simulation
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CPU time: .262 seconds to compile
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