module tb_frame_arbiter;
reg clk;
reg rst_n;
reg [159:0] wframe_data;
reg         wframe_valid;
wire        wframe_ready;

reg [159:0] rframe_data;
reg         rframe_valid;
wire        rframe_ready;

wire [152:0] axi2array_frame_data;
wire         axi2array_frame_valid;
reg          axi2array_frame_ready;

reg         mc_work_en;
reg [1:0]   axi_bus_rw_priority;

frame_arbiter u_frame_arbiter(
    .clk            (clk),
    .rst_n          (rst_n),
    .wframe_data    (wframe_data),
    .wframe_valid   (wframe_valid),
    .wframe_ready   (wframe_ready),
    .rframe_data    (rframe_data),
    .rframe_valid   (rframe_valid),
    .rframe_ready   (rframe_ready),
    .axi2array_frame_data(axi2array_frame_data),
    .axi2array_frame_valid(axi2array_frame_valid),
    .axi2array_frame_ready(axi2array_frame_ready),
    .mc_work_en(mc_work_en),
    .axi_bus_rw_priority(axi_bus_rw_priority)
);

task wframe;
input [159:0] wdata;
begin
    @(posedge clk) begin
        wframe_data <= wdata;
        wframe_valid <= 1'b1;
    end
    #0.1;
    wait(wframe_ready);
    @(posedge clk) begin
        wframe_valid <= 1'b0;
    end
end
endtask

task rframe;
input [159:0] rdata;
begin
    @(posedge clk) begin
        rframe_data <= rdata;
        rframe_valid <= 1'b1;
    end
    #0.1;
    wait(rframe_ready);
    @(posedge clk) begin
        rframe_valid <= 1'b0;
    end
end
endtask

initial begin
    clk = 0;
    forever begin
        #10; clk = ~clk;
    end
end

initial begin
    rst_n = 'd0;
    wframe_data = 'd0;
    wframe_valid = 'd0;
    rframe_data = 'd0;
    rframe_valid = 'd0;
    axi2array_frame_ready = 1'b1;
    mc_work_en = 1'b1;
    axi_bus_rw_priority = 2'b01;
    @(posedge clk) begin
        rst_n <= 1'b1;
    end
    wframe({152'd3,8'd5});
    wframe({152'd4,8'd5});
    wframe({152'd5,8'd5});
    rframe({152'd6,8'd1});
    fork
        wframe({152'd7,8'd1});
        rframe({152'd8,8'd1});
    join
    $fsdbDumpfile("tb.fsdb");
    $fsdbDumpvars(0,tb_frame_arbiter,"+all");
        #10
    $finish;

end



endmodule