Command: /home/ICer/ic_prjs/mc/IC_PRJ/sim/simv -sml=verdi +fsdb+gate=off -ucli2Proc -ucli -l /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log Chronologic VCS simulator copyright 1991-2018 Contains Synopsys proprietary information. Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 6 22:32 2025 ucli% synUtils::getArch linux64 ucli% loaddl -simv /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUXAMD64/libnovas.so LoadFSDBDumpCmd;LoadFSDBDumpCmd LoadFSDBDumpCmd success ucli% config ckptfsdbcheck off;config endofsim noexit;config onfail {enable all};config followactivescope on;catch {setUcliVerdiConnected};set watch::resultTagsForVerdiBP { };cbug::config pretty_print auto;fsdbDumpfile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb} ;fsdbDumpflush ; *Verdi* Loading libsscore_vcs201809.so FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 (C) 1996 - 2019 by Synopsys, Inc. *Verdi* : Create FSDB file '/home/ICer/ic_prjs/mc/IC_PRJ/sim/inter.fsdb' *Verdi* : Flush all FSDB Files at 0 ps. ucli% sps_interactive *Verdi* : Enable RPC Server(26345) ucli% ucliCore::getToolPID 26345 ucli% ucliCore::getToolPID 26345 ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% puts $ucliCore::nativeUcliMode 0 ucli% ucliCore::getToolTopPID 26345 ucli% pid 26359 ucli% synUtils::sendTool -active {_icl_createSharedMemory /tmp/vcs_dve_general.ICer.26345 } ucli% if { [info vars watch::vcbp_str_len_limit_of_get_value] != ""} {set watch::vcbp_str_len_limit_of_get_value 1024} 1024 ucli% info command stateVerdiChangeCB ucli% proc stateVerdiChangeCB args { if {$ucliGUI::state eq "terminated"} {puts "\nVERDI_SIM_Terminated\n";catch {setVerdiSimTerminated}}} ucli% trace variable ucliGUI::state wu stateVerdiChangeCB ucli% if {[catch {rename synopsys::restore verdiHack::restore} ]} {puts "0"} ucli% proc synopsys::restore {args} { verdiHack::restore $args; puts "\nVERDI_SIM_RESTORE\n"} ucli% if {[catch {rename quit verdiHack::quit} ]} {puts "0"} ucli% proc quit {args} { if {[string length $args] == 0} { verdiHack::quit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n quit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::quit $args; } } ucli% if {[catch {rename exit verdiHack::exit} ]} {puts "0"} ucli% proc exit {args} { if {[string length $args] == 0} { verdiHack::exit; } elseif {([string equal "-h" $args] == 1)||([string equal "-he" $args] == 1)||([string equal "-hel" $args] == 1)||([string equal "-help" $args] == 1)} { puts "\n exit # Exit the simulation.\n \[-noprompt\] (Exit the simulation and Verdi.)\n"} elseif {([string equal "-n" $args] == 1)||([string equal "-no" $args] == 1)||([string equal "-nop" $args] == 1)||([string equal "-nopr" $args] == 1)||([string equal "-nopro" $args] == 1)||([string equal "-noprom" $args] == 1)||([string equal "-nopromp" $args] == 1)||([string equal "-noprompt" $args] == 1)} { puts "\nVERDI_EXIT_N\n" } else { verdiHack::exit $args; } } ucli% proc checkpoint::beforeRecreate {} { sps_interactive } ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% save::getUserdefinedProcs ::stateVerdiChangeCB ::LoadFSDBDumpCmd ucli% info procs ipi_get_str fsdbDumpMDAByFile fsdbDumpMDA echo fsdbDumpMemNow fsdbAutoSwitchDumpfile unknown sps_interactive auto_import stat fsdbDumpfile setenv auto_execok pkg_mkIndex stateVerdiChangeCB fsdbDumpSingle proc_body ipi_begin fsdbDumpoff getenv fsdbDumplimit fsdbDumpPattern ipi_handle fsdbDumpvarsByFile fsdbDumpMDAInScope lminus ipi_sim_get interp ls auto_load_index proc_args fsdbAddRuntimeSignal fsdbDumpSC print_message_info ridbDump fsdbDumpSVAoff fsdbSuppress fsdbDumpvars help fsdbDumpMDAOnChange ipi_control auto_qualify fsdbDumpMem tclPkgUnknown printenv ipi_handle_by_name helpdoc fsdbDumpMemInScope fsdbDumpFinish is_true fsdbDumpon sh fsdbQueryInfo puts LoadFSDBDumpCmd fsdbDumpPSL fsdbDumpSVA ipi_end wrapperSpecmanSn fsdbDumpSVAon fsdbDumpClassObjectByFile is_false auto_load fsdbDumpPSLon ipi_get_int64 fsdbSubstituteHier ipi_get_value ipi_iterate exit fsdbDumpMemInFile tclLog fsdbDumpflush get_unix_variable mem_debug ipi_scan fsdbDumpPSLoff fsdbDumpClassObject fsdbDumpvarsToFile set_unix_variable bgerror fsdbDumpStrength clock add_group fsdbSwitchDumpfile source add_wave unsetenv fsdbDumpvarsES readline fsdbDisplay ipi_handle_free set_group ipi_get quit define_proc_attributes tclPkgSetup fsdbDumpMDANow ipi_init_play_tcl fsdbDumpIO ucli% lappend ucliCore::resultTagsForVerdi ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% fsdbDumpvarsByFile {/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file};fsdbDumpflush *Verdi* : Begin dumping the scopes by file (/home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/.tbsimDump_var_file). *Verdi* : End of dumping. *Verdi* : Flush all FSDB Files at 0 ps. ucli% fsdbDumpflush *Verdi* : Flush all FSDB Files at 0 ps. ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% fsdbDumpflush *Verdi* : Flush all FSDB Files at 0 ps. ucli% senv activeDomain: Verilog activeFile: ../tb/tb_rchannel.v activeFrame: activeLine: 1 activeScope: tb_rchannel activeThread: endCol: 0 file: ../tb/tb_rchannel.v frame: fsdbFilename: hasTB: 0 inputFilename: keyFilename: ucli.key line: 1 logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log macroIndex: -1 macroOffset: -1 pid: 26345 scope: tb_rchannel startCol: 0 state: stopped thread: time: 0 timePrecision: 1 ps vcdFilename: vpdFilename: ucli% synUtils::resolveSourceFilename ../tb/tb_rchannel.v ../tb/tb_rchannel.v ucli% puts $::ucliCore::cbug_active 0 ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% checkpoint -list -all There are no checkpoints present. ucli% stop No stop points are set ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% run *Verdi* : Begin traversing the scope (tb_rchannel), layer (0). *Verdi* : Enable +all dumping. *Verdi* : End of traversing. $finish called from file "../tb/tb_rchannel.v", line 64. $finish at simulation time 365000 Simulation complete, time is 365000 ps. tb_rchannel.v, 1 : module tb_rchannel; ucli% synEnv::hasFataled 0 ucli% ucliCore::getToolPID 26345 ucli% save::getUserdefinedProcs ::stateVerdiChangeCB ::LoadFSDBDumpCmd ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% fsdbDumpflush *Verdi* : Flush all FSDB Files at 365,000 ps. ucli% senv activeDomain: Verilog activeFile: ../tb/tb_rchannel.v activeFrame: activeLine: 1 activeScope: tb_rchannel activeThread: endCol: 0 file: ../tb/tb_rchannel.v frame: fsdbFilename: hasTB: 0 inputFilename: keyFilename: ucli.key line: 1 logFilename: /home/ICer/ic_prjs/mc/IC_PRJ/sim/verdiLog/sim.log macroIndex: -1 macroOffset: -1 pid: 26345 scope: tb_rchannel startCol: 0 state: stopped thread: time: 365000 timePrecision: 1 ps vcdFilename: vpdFilename: ucli% synUtils::resolveSourceFilename ../tb/tb_rchannel.v ../tb/tb_rchannel.v ucli% puts $::ucliCore::cbug_active 0 ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% checkpoint -list -all There are no checkpoints present. ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% stop No stop points are set ucli% if {[catch {ucliCore::setFocus tool}]} {} ucli% finish; quit V C S S i m u l a t i o n R e p o r t Time: 365000 ps CPU Time: 0.250 seconds; Data structure size: 0.0Mb Wed Aug 6 22:41:15 2025 VERDI_SIM_Terminated