`timescale 1ns/1ps
module tb_wchannel;
reg clk;
reg rst_n;

reg axi_s_awvalid;
wire axi_s_awready;
reg [7:0] axi_s_awlen;
reg [25:0] axi_s_awaddr;

reg axi_s_wvalid;
wire axi_s_wready;

reg [63:0] axi_s_wdata;
reg axi_s_wlast;

wire wframe_valid;
wire [159:0] wframe_data;
reg wframe_ready;

wchannel u_wchannel(
    .clk(clk),
    .rst_n(rst_n),
    .axi_s_awvalid(axi_s_awvalid),
    .axi_s_awready(axi_s_awready),
    .axi_s_awlen(axi_s_awlen),
    .axi_s_awaddr(axi_s_awaddr),
    .axi_s_wvalid(axi_s_wvalid),
    .axi_s_wready(axi_s_wready),
    .axi_s_wdata(axi_s_wdata),
    .axi_s_wlast(axi_s_wlast),
    .wframe_valid(wframe_valid),
    .wframe_data(wframe_data),
    .wframe_ready(wframe_ready)
);

initial begin
    clk = 0;
    forever begin
        #10 clk = ~clk;
    end
end

initial begin
    rst_n = 1'b0;
    axi_s_awvalid = 1'b0;
    axi_s_awlen = 8'b0;
    axi_s_wvalid = 1'b0;
    axi_s_wdata = 64'b0;
    axi_s_wlast = 1'b0;
    wframe_ready = 1'b1;
    @(posedge clk) begin
        rst_n <= 1'b1;
    end
   aw(8'd5,{16'h0,6'h3f,4'h0});
    aw(8'd3,26'h20); 
    w(64'd1,0);
    w(64'd2,0);
    w(64'd3,0);
    w(64'd4,0);
    w(64'd5,0);
    w(64'd6,1);
    @(posedge clk) begin
        axi_s_wvalid <= 1'b0;
    end
    w(64'd6,0);
    w(64'd7,0);
    @(posedge clk) begin
        axi_s_wvalid <= 1'b0;
    end
    $display("end");
	#100;
    	$finish;
end

task aw;
input [7:0] awlen;
input [25:0] awaddr;
begin
@(posedge clk) begin
axi_s_awvalid <= 1'b1;
axi_s_awaddr <= awaddr;
axi_s_awlen <= awlen;
end
#1;
wait(axi_s_awready);
@(posedge clk) begin
    axi_s_awvalid <= 1'b0;
end
end
endtask

task w;
input [63:0] wdata;
input wlast;
begin
@(posedge clk) begin
    axi_s_wvalid <= 1'b1;
    axi_s_wdata <= wdata;
    axi_s_wlast <= wlast;
    $display("wdata is %0h",wdata);
end
#1;
wait(axi_s_wready);
@(posedge clk) begin
axi_s_wvalid <= 1'b0;
end
end
endtask

initial begin
  	$fsdbDumpfile("tb.fsdb");
	$fsdbDumpvars(0,tb_wchannel,"+all");

end
endmodule