102 lines
2.0 KiB
Verilog
102 lines
2.0 KiB
Verilog
module tb_frame_arbiter;
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reg clk;
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reg rst_n;
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reg [159:0] wframe_data;
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reg wframe_valid;
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wire wframe_ready;
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reg [159:0] rframe_data;
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reg rframe_valid;
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wire rframe_ready;
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wire [152:0] axi2array_frame_data;
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wire axi2array_frame_valid;
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reg axi2array_frame_ready;
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reg mc_work_en;
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reg [1:0] axi_bus_rw_priority;
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frame_arbiter u_frame_arbiter(
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.clk (clk),
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.rst_n (rst_n),
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.wframe_data (wframe_data),
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.wframe_valid (wframe_valid),
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.wframe_ready (wframe_ready),
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.rframe_data (rframe_data),
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.rframe_valid (rframe_valid),
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.rframe_ready (rframe_ready),
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.axi2array_frame_data(axi2array_frame_data),
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.axi2array_frame_valid(axi2array_frame_valid),
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.axi2array_frame_ready(axi2array_frame_ready),
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.mc_work_en(mc_work_en),
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.axi_bus_rw_priority(axi_bus_rw_priority)
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);
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task wframe;
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input [159:0] wdata;
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begin
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@(posedge clk) begin
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wframe_data <= wdata;
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wframe_valid <= 1'b1;
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end
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#0.1;
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wait(wframe_ready);
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@(posedge clk) begin
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wframe_valid <= 1'b0;
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end
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end
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endtask
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task rframe;
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input [159:0] rdata;
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begin
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@(posedge clk) begin
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rframe_data <= rdata;
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rframe_valid <= 1'b1;
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end
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#0.1;
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wait(rframe_ready);
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@(posedge clk) begin
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rframe_valid <= 1'b0;
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end
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end
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endtask
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initial begin
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clk = 0;
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forever begin
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#10; clk = ~clk;
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end
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end
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initial begin
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rst_n = 'd0;
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wframe_data = 'd0;
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wframe_valid = 'd0;
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rframe_data = 'd0;
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rframe_valid = 'd0;
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axi2array_frame_ready = 1'b1;
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mc_work_en = 1'b1;
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axi_bus_rw_priority = 2'b01;
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@(posedge clk) begin
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rst_n <= 1'b1;
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end
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wframe({152'd3,8'd5});
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wframe({152'd4,8'd5});
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wframe({152'd5,8'd5});
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rframe({152'd6,8'd1});
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fork
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wframe({152'd7,8'd1});
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rframe({152'd8,8'd1});
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join
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0,tb_frame_arbiter,"+all");
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#10
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$finish;
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end
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endmodule
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