98 lines
1.3 KiB
Verilog
98 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module tb_sync_fifo;
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parameter DATA_WIDTH = 30;
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parameter FIFO_DEPTH = 4;
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reg clk;
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reg rst_n;
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reg wr_en;
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reg [DATA_WIDTH -1:0] wr_data;
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wire full;
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reg rd_en;
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wire [DATA_WIDTH -1:0] rd_data;
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wire empty;
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sync_fifo #(
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.DATA_WIDTH(DATA_WIDTH),
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.FIFO_DEPTH(FIFO_DEPTH)
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) u_sync_fifo(
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.clk(clk),
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.rst_n(rst_n),
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.wr_en(wr_en),
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.wr_data(wr_data),
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.full(full),
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.rd_en(rd_en),
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.rd_data(rd_data),
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.empty(empty)
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);
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initial begin
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clk = 0;
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forever begin
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#10;
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clk = ~clk;
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end
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end
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initial begin
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init;
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push;
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pop;
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0,tb_sync_fifo);
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#100;
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$finish;
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end
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task init;
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begin
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rst_n = 0;
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#30;
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rst_n = 1'b1;
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wr_en = 'b0;
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wr_data = 'd0;
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rd_en = 'b0;
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end
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endtask
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integer i;
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task push;
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begin
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for(i=0;i<=20;i=i+1) begin
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@(posedge clk) begin
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wr_data <= {$random}%DATA_WIDTH + 5'd20;
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wr_en <= 1;
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if(!full) begin
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$display("write data is %0d",wr_data);
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end else begin
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$display("fifo is full!");
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end
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end
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end
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wr_en <= 0;
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end
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endtask
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task pop;
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begin
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for(i=0;i<=20;i=i+1) begin
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@(negedge clk) begin
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rd_en <= 1;
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if(!empty) begin
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$display("read data is %0d",rd_data);
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end else begin
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$display("fifo is empty!");
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end
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end
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end
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rd_en = 0;
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end
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endtask
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endmodule
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