299 lines
18 KiB
Plaintext
299 lines
18 KiB
Plaintext
SpyGlass run started at 11:06:16 on 8 05 2025
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SpyGlass Predictive Analyzer(R) - Version SpyGlass_vL-2016.06
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Last compiled on May 20 2016
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All Rights Reserved. Use, disclosure or duplication
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without prior written permission of Synopsys Inc. is prohibited.
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Technical support: email spyglass_support@synopsys.com.
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Running SpyGlass 64-bit Executable: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/obj/check.Linux4
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RULE-CHECKING IN MIXED MODE
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Loading Policy: spyglass (Version: SpyGlass_vL-2016.06) from path: /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/policies/spyglass
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Loading Shared library libspyglassrules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libspyglassrules-Linux4.spyso
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Loading Shared library libsdcInitRules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libsdcInitRules-Linux4.spyso
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Loading Shared library librmerules-Linux4.spyso from /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/librmerules-Linux4.spyso
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##build_id : SpyGlass_vL-2016.06
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##system : Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
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##cwd : /home/ICer/ic_prjs/mc/sim
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##lang : Verilog+VHDL
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##args : -mSpyGlass::Compatibility::v2_7_3 \
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-mSpyGlass::Compatibility::v2_7_3 \
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-mSpyGlass::Compatibility::v2_7_3 \
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-top 'tb_wchannel' \
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-lib WORK ./spyglass-1/tb_wchannel/WORK \
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-nl \
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-policy='none' \
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-mixed \
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-batch \
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-wdir './spyglass-1/tb_wchannel/Design_Read' \
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-templatedir '/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/auxi/policy_data/spyglass/design_read' \
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--goal_info 'Design_Read@' \
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--template_info 'Design_Read' \
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-projectwdir './spyglass-1' \
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-64bit \
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../rtl/sync_fifo_64_to_128.v \
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../rtl/sync_fifo.v \
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../rtl/wchannel.v \
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../tb/tb_wchannel.v
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##verbosity level : 2
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##exact cmdline arg : -batch -project spyglass-1.prj -designread -64bit
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##spyglass_run.csh begins :
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; cd /home/ICer/ic_prjs/mc/sim
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; setenv SPYGLASS_LD_PRELOAD /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/lib/libsgjemalloc-Linux4.so
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; setenv SPYGLASS_DW_PATH /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/dw_support
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; /home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/bin/spyglass -batch -project spyglass-1.prj -designread -64bit
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##spyglass_run.csh ends
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##files : ../rtl/sync_fifo_64_to_128.v \
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../rtl/sync_fifo.v \
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../rtl/wchannel.v \
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../tb/tb_wchannel.v
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INFO [6] Work Directory `./spyglass-1/tb_wchannel/WORK' does not exist.
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INFO [75] Creating the Work Directory `./spyglass-1/tb_wchannel/WORK/64' for 64bit precompiled dump.
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Checking Rule ZeroSizeFile (Rule 1 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule PrecompileLibCheck01 (Rule 2 of total 103) .... done (Time = 0.00s, Memory = 23.6K)
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Checking Rule PrecompileLibCheck02 (Rule 3 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule PrecompileLibCheck03 (Rule 4 of total 103) .... done (Time = 0.00s, Memory = -2.4K)
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Checking Rule PrecompileLibCheck04 (Rule 5 of total 103) .... done (Time = 0.00s, Memory = -24.0K)
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Checking Rule SGDC_assume_path01 (Rule 6 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_sdcschema02 (Rule 7 of total 103) .... done (Time = 0.00s, Memory = 0.1K)
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Checking Rule SGDC_clock05 (Rule 8 of total 103) .... done (Time = 0.00s, Memory = 63.0K)
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Checking Rule SGDC_clock09 (Rule 9 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_force_ta05 (Rule 10 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_require_path03 (Rule 11 of total 103) .... done (Time = 0.00s, Memory = -0.1K)
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Checking Rule SGDC_require_value03 (Rule 12 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_voltagedomain05 (Rule 13 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_voltagedomain06 (Rule 14 of total 103) .... done (Time = 0.00s, Memory = 7.4K)
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Checking Rule SGDC_voltagedomain07 (Rule 15 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_powerdomainoutputs02 (Rule 16 of total 103) .... done (Time = 0.00s, Memory = 12.0K)
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Checking Rule SGDC_supply01 (Rule 17 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive01 (Rule 18 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive02 (Rule 19 of total 103) .... done (Time = 0.00s, Memory = -7.1K)
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Checking Rule SGDC_waive03 (Rule 20 of total 103) .... done (Time = 0.00s, Memory = 7.3K)
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Checking Rule SGDC_waive04 (Rule 21 of total 103) .... done (Time = 0.00s, Memory = -8.0K)
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Checking Rule SGDC_waive05 (Rule 22 of total 103) .... done (Time = 0.00s, Memory = 8.0K)
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Checking Rule SGDC_waive06 (Rule 23 of total 103) .... done (Time = 0.00s, Memory = 3.5K)
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Checking Rule SGDC_waive07 (Rule 24 of total 103) .... done (Time = 0.00s, Memory = -0.8K)
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Checking Rule SGDC_waive08 (Rule 25 of total 103) .... done (Time = 0.00s, Memory = 0.1K)
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Checking Rule SGDC_waive09 (Rule 26 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive10 (Rule 27 of total 103) .... done (Time = 0.00s, Memory = 1.3K)
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Checking Rule SGDC_waive11 (Rule 28 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive12 (Rule 29 of total 103) .... done (Time = 0.00s, Memory = -1.2K)
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Checking Rule SGDC_waive13 (Rule 30 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive21 (Rule 31 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive22 (Rule 32 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive30 (Rule 33 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive32 (Rule 34 of total 103) .... done (Time = 0.00s, Memory = 0.2K)
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Checking Rule SGDC_waive33 (Rule 35 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive36 (Rule 36 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive38 (Rule 37 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_fifo01 (Rule 38 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_libgroup01 (Rule 39 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_libgroup02 (Rule 40 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_libgroup04 (Rule 41 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_power_data01 (Rule 42 of total 103) .... done (Time = 0.00s, Memory = 32.5K)
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Checking Rule SGDC_ungroup01 (Rule 43 of total 103) .... done (Time = 0.00s, Memory = 0.8K)
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Checking Rule SGDC_abstract_port06 (Rule 44 of total 103) .... done (Time = 0.00s, Memory = 141.9K)
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Checking Rule SGDC_abstract_port14 (Rule 45 of total 103) .... done (Time = 0.00s, Memory = -8.0K)
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Checking Rule SGDC_abstract_port15 (Rule 46 of total 103) .... done (Time = 0.00s, Memory = 32.0K)
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Checking Rule SGDC_abstract_port18 (Rule 47 of total 103) .... done (Time = 0.00s, Memory = -4.1K)
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Checking Rule sdc_init_rule (Rule 48 of total 103) .... done (Time = 0.00s, Memory = 81.4K)
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Checking Rule CMD_ignorelibs01 (Rule 49 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule ReportRuleNotRun (Rule 50 of total 103) .... done (Time = 0.00s, Memory = -8.0K)
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Checking Rule ReportStopSummary (Rule 51 of total 103) .... done (Time = 0.00s, Memory = 9.6K)
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Checking Rule ReportIgnoreSummary (Rule 52 of total 103) .... done (Time = 0.00s, Memory = 8.0K)
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##SGDEBUG [BENCHMARK_ABSOLUTE]: Analysis started: 1 sec, 473610 KB, 2271800 KB
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##SGDEBUG [BENCHMARK_INCR]: Analysis started: 1 sec, 473610 KB, 2271800 KB
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Analyzing source file "../rtl/sync_fifo_64_to_128.v" ....
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Analyzing source file "../rtl/sync_fifo.v" ....
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Analyzing source file "../rtl/wchannel.v" ....
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Analyzing source file "../tb/tb_wchannel.v" ....
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SYNTH_196 - - ERROR
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SYNTH_106 - - ERROR
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SYNTH_196 - - ERROR
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SYNTH_196 - - ERROR
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SYNTH_106 - - ERROR
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SYNTH_196 - - ERROR
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##SGDEBUG [BENCHMARK_ABSOLUTE]: Analysis finished: 1 sec, 541442 KB, 2339640 KB
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##SGDEBUG [BENCHMARK_INCR]: Analysis finished: 0 sec, 67832 KB, 67840 KB
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##SGDEBUG [BENCHMARK_ABSOLUTE]: Elaboration started: 1 sec, 541442 KB, 2339640 KB
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##SGDEBUG [BENCHMARK_INCR]: Elaboration started: 0 sec, 0 KB, 0 KB
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Elaborating Top Verilog Design Unit 'tb_wchannel' ..... done
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##SGDEBUG [BENCHMARK_ABSOLUTE]: Elaboration finished: 1 sec, 607363 KB, 2405432 KB
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##SGDEBUG [BENCHMARK_INCR]: Elaboration finished: 0 sec, 65921 KB, 65792 KB
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##SGDEBUG [BENCHMARK_ABSOLUTE]: RTL Semantic Checker started: 1 sec, 607363 KB, 2405432 KB
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##SGDEBUG [BENCHMARK_INCR]: RTL Semantic Checker started: 0 sec, 0 KB, 0 KB
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##SGDEBUG [BENCHMARK_ABSOLUTE]: RTL Semantic Checker finished: 1 sec, 607369 KB, 2405432 KB
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##SGDEBUG [BENCHMARK_INCR]: RTL Semantic Checker finished: 0 sec, 6 KB, 0 KB
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Checking Rule ElabSummary (Rule 53 of total 103)##FILEDEBUG[sgOpenFile]: Opening File './spyglass-1/tb_wchannel/Design_Read/spyglass_reports/SpyGlass/elab_summary.rpt' in "w" mode ...
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##FILEDEBUG[sgCloseFile]: File './spyglass-1/tb_wchannel/Design_Read/spyglass_reports/SpyGlass/elab_summary.rpt' closed.
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.... done (Time = 0.00s, Memory = 0.5K)
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Checking Rule ReportCheckDataSummary (Rule 54 of total 103) .... done (Time = 0.00s, Memory = 24.0K)
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Reading waiver file "./spyglass-1/tb_wchannel/Design_Read/spyglass_spysch/constraint/spg_autogenerated_waivers.sgdc" ...
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Generating SGDC file "./spyglass-1/tb_wchannel/Design_Read/spyglass_spysch/constraint/pragma2Constraint.sgdc" from pragmas in HDL source files ....
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Generating WAIVER file "./spyglass-1/tb_wchannel/Design_Read/spyglass_spysch/waiver/pragma2Waiver.swl" from pragmas in HDL source files ....
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Checking Rule SGDC_waive37 (Rule 55 of total 103) .... done (Time = 0.00s, Memory = 0.6K)
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Checking Rule SGDC_waive35 (Rule 56 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule DetectTopDesignUnits (Rule 57 of total 103) Detected 1 top level design units:
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tb_wchannel
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.... done (Time = 0.00s, Memory = 4.0K)
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Performing semantic checks on SGDC contents
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..... SGDC semantic checks completed. (Time = 0.00s, Memory = 76.0K)
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Checking Rule SGDC_testmode03 (Rule 58 of total 103) .... done (Time = 0.00s, Memory = 8.0K)
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Checking Rule ReportObsoletePragmas (Rule 59 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule GenerateConfMap (Rule 60 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule HdlLibDuCheck (Rule 61 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule RtlDesignInfo (Rule 62 of total 103)
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##SGDEBUG [BENCHMARK_DATA]: Number of RTL Design Units = 4
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##SGDEBUG: RTL statistics for Verilog design units:
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##SGDEBUG[BENCHMARK_DATA]: RTL Ports = 29 487 8
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##SGDEBUG[BENCHMARK_DATA]: RTL Insts = 27
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##SGDEBUG[BENCHMARK_DATA]: RTL Nets = 44 756 25
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##SGDEBUG[BENCHMARK_DATA]: RTL Terms = 77 487 8
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##SGDEBUG: NOTE: Following estimated data is applicable for structural designs only.
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##SGDEBUG: In case of RTL designs, this data may differ significantly from the actual figure.
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##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Insts = 2
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##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Nets = 720
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##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Terms = 220
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##SGDEBUG[BENCHMARK_DATA]: Estimated Flat Paths = 2
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.... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule CheckCelldefine (Rule 63 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive23 (Rule 64 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive26 (Rule 65 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive27 (Rule 66 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive29 (Rule 67 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule AnalyzeBBox (Rule 68 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule ReportCheckDataSummary (Rule 54 of total 103) .... done (Time = 0.00s, Memory = 24.0K)
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Checking Rule SGDC_waive24 (Rule 69 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive25 (Rule 70 of total 103) .... done (Time = 0.00s, Memory = 0.0K)
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Checking Rule SGDC_waive31 (Rule 71 of total 103) .... done (Time = 0.00s, Memory = 3.1K)
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Generating data for Console...
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##SGDEBUG [PEAK_MEMORY]: 2407196 KB for entire run at 'End of rule checking' stage
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##SGDEBUG [VMPEAK_MEMORY]: 2407200 KB for entire run
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##SGDEBUG [BENCHMARK_ABSOLUTE]: Rule checking finished: 1 sec, 608827 KB, 2407196 KB
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##SGDEBUG [BENCHMARK_INCR]: Rule checking finished: 0 sec, 1458 KB, 1764 KB
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=====================================================================================
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Rule Parameter Table
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=====================================================================================
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PARAMETER-NAME VALUE
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-------------------------------------------------------------------------------------
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-allow_clock_on_output_port no
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-check_clock_group_violations no
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-debug_proc no
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-force_genclk_for_txv no
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-library_gen_clock_naming yes
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-netlist_clock_polarity yes
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-populate_comboelements_for_minmax_in_fromto no
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-preserve_path no
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-pt no
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-show_all_sdc_violations no
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-show_sdc_progress no
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-suppress_sdc_violation_in_abstract no
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-tc_disable_caching no
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-tc_stop_parsing_ignored_commands no
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-truncate_through yes
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-write_sdc no
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=====================================================================================
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=====================================================================================
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Rule Status Table
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RULE-NAME POLICY-NAME ENABLED VIOL-CNT RULE-TYPE ERROR-MSG
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=====================================================================================
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SYNTH_196 (Verilog) SpyGlass Yes 4 SETUP -
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SYNTH_106 (Verilog) SpyGlass Yes 2 SETUP -
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ElabSummary SpyGlass Yes 1 SETUP -
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DetectTopDesignUnits SpyGlass Yes 1 RTLALLDULIST -
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-------------------------------------------------------------------------------------
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Note: VSDU type of rules (as seen in the above table) are not run on
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unsynthesized modules reported by 'ErrorAnalyzeBBox/InfoAnalyzeBBox' messages
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(Please see messages starting with keyword 'UnsynthesizedDU')
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##status : SpyGlass Rule Checking Complete.
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---------------------------------------------------------------------------------------------
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Results Summary:
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---------------------------------------------------------------------------------------------
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Goal Run : Design_Read
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Command-line read : 0 error, 0 warning, 0 information message
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** Design Read : 6 errors, 0 warning, 2 information messages
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Found 1 top module:
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tb_wchannel (file: ../tb/tb_wchannel.v)
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Blackbox Resolution: 0 error, 0 warning, 0 information message
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SGDC Checks : 0 error, 0 warning, 0 information message
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-------------------------------------------------------------------------------------
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Total : 6 errors, 0 warning, 2 information messages
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Total Number of Generated Messages : 8 (6 errors, 0 warning, 2 Infos)
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Number of Reported Messages : 8 (6 errors, 0 warning, 2 Infos)
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NOTE: It is recommended to first fix/reconcile fatals/errors reported on
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lines starting with ** as subsequent issues might be related to it.
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Please re-run SpyGlass once ** prefixed lines are fatal/error clean.
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---------------------------------------------------------------------------------------------
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SpyGlass Rule Checking Complete.
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Generating moresimple report from './spyglass-1/tb_wchannel/Design_Read/spyglass.vdb' to './spyglass-1/tb_wchannel/Design_Read/spyglass_reports/moresimple.rpt' ....
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Generating runsummary report from './spyglass-1/tb_wchannel/Design_Read/spyglass.vdb' ....
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Generating no_msg_reporting_rules report from './spyglass-1/tb_wchannel/Design_Read/spyglass.vdb' to './spyglass-1/tb_wchannel/Design_Read/spyglass_reports/no_msg_reporting_rules.rpt' ....
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Policy specific data (reports) are present in the directory './spyglass-1/tb_wchannel/Design_Read/spyglass_reports'.
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SpyGlass critical reports for the current run are present in directory './spyglass-1/consolidated_reports/tb_wchannel_Design_Read/'.
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---------------------------------------------------------------------------------------------------
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Results Summary:
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---------------------------------------------------------------------------------------------------
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Goal Run : Design_Read
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Top Module : tb_wchannel
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---------------------------------------------------------------------------------------------------
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Reports Directory:
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/home/ICer/ic_prjs/mc/sim/spyglass-1/consolidated_reports/tb_wchannel_Design_Read/
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SpyGlass LogFile:
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/home/ICer/ic_prjs/mc/sim/spyglass-1/tb_wchannel/Design_Read/spyglass.log
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Standard Reports:
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moresimple.rpt no_msg_reporting_rules.rpt
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HTML report:
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/home/ICer/ic_prjs/mc/sim/spyglass-1/html_reports/goals_summary.html
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Technology Reports:
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<Not Available>
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---------------------------------------------------------------------------------------------------
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Goal Violation Summary:
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Waived Messages: 0 Errors, 0 Warnings, 0 Infos
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Reported Messages: 0 Fatals, 6 Errors, 0 Warnings, 2 Infos
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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SpyGlass Exit Code 0 (Rule-checking completed with errors)
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SpyGlass total run-time is 0:0:1 (1 secs)
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SpyGlass run completed at 11:08:04 AM on Aug 05 2025
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