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IC_PRJ/sim/verdiLog/compiler.log

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*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
Command arguments:
+define+verilog
-f filelist.f
../rtl/sync_fifo_128_to_64.v
../rtl/sync_fifo.v
../rtl/rchannel.v
../tb/tb_rchannel.v
Highest level modules:
tb_rchannel
Total 0 error(s), 0 warning(s)