IC_PRJ/rtl/array_ctrl.v

module array_ctrl(
    input           clk,
    input           rst_n,

    //axi2array_frame bus
    input           axi2array_frame_valid,
    input [152:0]   axi2array_frame_data,
    output          axi2array_frame_ready,
    //array2axi_rdata bus
    output          array2axi_rdata_valid,
    output [127:0]  array2axi_rdata,
    //array if
    output          array_csn,
    output [15:0]   array_raddr,
    output          array_caddr_vld_wr,
    output [5:0]    array_caddr_wr,
    output          array_wdata_vld,
    output [127:0]  array_wdata,
    output          array_caddr_vld_rd,
    output [5:0]    array_caddr_rd,
    input           array_rdata_vld,
    input [127:0]   array_rdata,
    //apb_cfg
    input           mc_work_en,
    input [7:0]     array_inner_tras,
    input [7:0]     array_inner_trp,
    input [7:0]     array_inner_trcd_wr,
    input [7:0]     array_inner_twr,
    input [7:0]     array_inner_trcd_rd,
    input [7:0]     array_inner_trtp,
    input           array_ref_en,
    input [24:0]    array_inner_tref0,
    input [24:0]    array_inner_tref1,
    input           array_inner_ref_sel
    
);

    wire [1:0]      array_mux_sel;
    wire            array_wr_frame_valid;
    wire [151:0]    array_wr_frame_data;
    wire            array_rd_frame_valid;
    wire [151:0]    array_rd_frame_data;
    wire            array_ref_start;

    wire            array_wr_frame_ready;
    wire            array_wr_done;
    wire            array_wr_csn;
    wire [15:0]     array_wr_raddr;

    wire            array_rd_frame_ready;
    wire            array_rd_done;
    wire            array_rd_csn;
    wire [15:0]     array_rd_raddr;
    
    wire            array_ref_done;
    wire            array_ref_csn;
    wire [15:0]     array_ref_raddr;






array_status_ctrl u_array_status_ctrl (
    .clk                    (clk),
    .rst_n                  (rst_n),
    .axi2array_frame_valid  (axi2array_frame_valid),
    .axi2array_frame_data   (axi2array_frame_data),
    .axi2array_frame_ready  (axi2array_frame_ready),
    .array_wr_frame_valid   (array_wr_frame_valid),
    .array_wr_frame_data    (array_wr_frame_data),
    .array_wr_frame_ready   (array_wr_frame_ready),
    .array_wr_done          (array_wr_done),
    .array_rd_frame_valid   (array_rd_frame_valid),
    .array_rd_frame_data    (array_rd_frame_data),
    .array_rd_frame_ready   (array_rd_frame_ready),
    .array_rd_done          (array_rd_done),
    .array_ref_start        (array_ref_start),
    .array_ref_done         (array_ref_done),
    .array_mux_sel          (array_mux_sel),
    .mc_work_en             (mc_work_en),
    .array_ref_en           (array_ref_en),
    .array_inner_tref0      (array_inner_tref0),
    .array_inner_tref1      (array_inner_tref1),
    .array_inner_ref_sel    (array_inner_ref_sel)
);

    // 实例化被测试模块（DUT）
    array_wr u_array_wr(
        .clk                (clk),
        .rst_n              (rst_n),
        .array_wr_frame_valid(array_wr_frame_valid),
        .array_wr_frame_data(array_wr_frame_data),
        .array_wr_frame_ready(array_wr_frame_ready),
        .array_wr_done      (array_wr_done),
        .array_wr_csn       (array_wr_csn),
        .array_wr_raddr     (array_wr_raddr),
        .array_caddr_vld_wr (array_caddr_vld_wr),
        .array_caddr_wr     (array_caddr_wr),
        .array_wdata_vld    (array_wdata_vld),
        .array_wdata        (array_wdata),
        .array_inner_tras   (array_inner_tras),
        .array_inner_trp    (array_inner_trp),
        .array_inner_trcd_wr(array_inner_trcd_wr),
        .array_inner_twr    (array_inner_twr)
    );

    // 实例化被测试模块（DUT）
    array_rd u_array_rd(
        .clk                (clk),
        .rst_n              (rst_n),
        .array_rd_frame_valid(array_rd_frame_valid),
        .array_rd_frame_data(array_rd_frame_data),
        .array_rd_frame_ready(array_rd_frame_ready),
        .array_rd_done      (array_rd_done),
        .array_rd_csn       (array_rd_csn),
        .array_rd_raddr     (array_rd_raddr),
        .array_caddr_vld_rd (array_caddr_vld_rd),
        .array_caddr_rd     (array_caddr_rd),
        .array_rdata_vld    (array_rdata_vld),
        .array_rdata        (array_rdata),
        .array_inner_tras   (array_inner_tras),
        .array_inner_trp    (array_inner_trp),
        .array_inner_trcd_rd(array_inner_trcd_rd),
        .array_inner_trtp   (array_inner_trtp),
        .array2axi_rdata_valid(array2axi_rdata_valid),
        .array2axi_rdata    (array2axi_rdata)
    );

        // 实例化待测试模块
    array_ref u_array_ref (
        .clk                (clk),
        .rst_n              (rst_n),
        .array_ref_start    (array_ref_start),
        .array_ref_done     (array_ref_done),
        .array_ref_csn      (array_ref_csn),
        .array_ref_raddr    (array_ref_raddr),
        .array_inner_tras   (array_inner_tras),
        .array_inner_trp    (array_inner_trp)
    );

    array_mux u_array_mux (
        .array_wr_csn    (array_wr_csn),
        .array_wr_raddr  (array_wr_raddr),
        .array_rd_csn    (array_rd_csn),
        .array_rd_raddr  (array_rd_raddr),
        .array_ref_csn   (array_ref_csn),
        .array_ref_raddr (array_ref_raddr),
        .array_mux_sel   (array_mux_sel),
        .array_csn       (array_csn),
        .array_raddr     (array_raddr)
    );

endmodule