38 lines
944 B
Verilog
38 lines
944 B
Verilog
module array_mux (
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input array_wr_csn,
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input [15:0] array_wr_raddr,
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input array_rd_csn,
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input [15:0] array_rd_raddr,
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input array_ref_csn,
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input [15:0] array_ref_raddr,
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input [1:0] array_mux_sel,
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output reg array_csn,
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output reg [15:0] array_raddr
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);
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always @(*) begin
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case (array_mux_sel)
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2'b01: begin
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array_csn = array_ref_csn;
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array_raddr = array_ref_raddr;
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end
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2'b10: begin
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array_csn = array_wr_csn;
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array_raddr = array_wr_raddr;
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end
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2'b11: begin
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array_csn = array_rd_csn;
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array_raddr = array_rd_raddr;
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end
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default: begin
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array_csn = 1'b1;
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array_raddr = 16'd0;
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end
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endcase
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end
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endmodule |