233 lines
7.4 KiB
Verilog
233 lines
7.4 KiB
Verilog
module array_wr (
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input clk,
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input rst_n,
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input array_wr_frame_valid,
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input [151:0] array_wr_frame_data,
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output array_wr_frame_ready,
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output array_wr_done,
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output reg array_wr_csn,
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output reg [15:0] array_wr_raddr,
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output reg array_caddr_vld_wr,
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output reg [5:0] array_caddr_wr,
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output array_wdata_vld,
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output reg [127:0] array_wdata,
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input [7:0] array_inner_tras,
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input [7:0] array_inner_trp,
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input [7:0] array_inner_trcd_wr,
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input [7:0] array_inner_twr
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);
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reg [2:0] cur_state,next_state;
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localparam [2:0] ARR_WR_IDLE = 3'b000;
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localparam [2:0] ARR_WR_LOWCS = 3'b001;
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localparam [2:0] ARR_WR_RCD = 3'b010;
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localparam [2:0] ARR_WR_HIGHVLD = 3'b011;
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localparam [2:0] ARR_WR_WDATALAST = 3'b100;
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localparam [2:0] ARR_WR_WDATA = 3'b101;
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localparam [2:0] ARR_WR_WR = 3'b110;
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localparam [2:0] ARR_WR_RP = 3'b111;
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wire wsof,weof;
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wire [15:0] wraddr;
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wire [5:0] wcaddr;
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wire [127:0] wdata;
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reg [7:0] wr_ras_cnt;
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reg [7:0] wr_rcd_cnt;
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reg [7:0] wr_wr_cnt;
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reg [7:0] wr_rp_cnt;
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reg single_flag_wr;
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reg array_wdata_eof;
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assign {wsof,weof,wraddr,wcaddr,wdata} = array_wr_frame_data;
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assign array_wdata_vld = !array_caddr_vld_wr;
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assign array_wr_frame_ready = (cur_state==ARR_WR_IDLE) || ((cur_state == ARR_WR_WDATA) &&
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!array_caddr_vld_wr);
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assign array_wr_done = (cur_state == ARR_WR_RP) && !wr_rp_cnt;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cur_state <= ARR_WR_IDLE;
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end else begin
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cur_state <= next_state;
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end
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end
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always @(*) begin
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case (cur_state)
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ARR_WR_IDLE : begin
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if (array_wr_frame_valid && wsof) begin
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next_state = ARR_WR_LOWCS;
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end else begin
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next_state = ARR_WR_IDLE;
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end
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end
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ARR_WR_LOWCS : begin
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next_state = ARR_WR_RCD;
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end
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ARR_WR_RCD : begin
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if (wr_rcd_cnt == 'd0) begin
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next_state = ARR_WR_HIGHVLD;
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end else begin
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next_state = ARR_WR_RCD;
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end
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end
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ARR_WR_HIGHVLD : begin
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if (single_flag_wr) begin
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next_state = ARR_WR_WDATALAST;
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end else begin
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next_state = ARR_WR_WDATA;
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end
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end
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ARR_WR_WDATALAST: begin
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next_state = ARR_WR_WR;
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end
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ARR_WR_WDATA : begin
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if (array_wdata_eof) begin
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next_state = ARR_WR_WR;
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end else begin
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next_state = ARR_WR_WDATA;
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end
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end
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ARR_WR_WR : begin
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if (wr_ras_cnt == 'd0 && wr_wr_cnt == 'd0) begin
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next_state = ARR_WR_RP;
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end else begin
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next_state = ARR_WR_WR;
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end
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end
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ARR_WR_RP : begin
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if (wr_rp_cnt == 'd0) begin
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next_state = ARR_WR_IDLE;
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end else begin
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next_state = ARR_WR_RP;
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end
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end
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default: next_state = ARR_WR_IDLE;
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endcase
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_wr_csn <= 1'b1;
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end else if (cur_state == ARR_WR_LOWCS) begin
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array_wr_csn <= 1'b0;
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end else if ((cur_state == ARR_WR_WR) && (next_state == ARR_WR_RP)) begin
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array_wr_csn <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_wr_raddr <= 'd0;
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end else if (array_wr_frame_valid && array_wr_frame_ready) begin
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array_wr_raddr <= wraddr;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_caddr_wr <= 'd0;
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end else if (array_wr_frame_valid && array_wr_frame_ready) begin
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array_caddr_wr <= wcaddr;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_wdata <= 'd0;
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end else if (array_wr_frame_valid && array_wr_frame_ready) begin
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array_wdata <= wdata;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_caddr_vld_wr <= 'd0;
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end else if (array_caddr_vld_wr == 1'b1) begin
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array_caddr_vld_wr <= 'd0;
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end else if (cur_state == ARR_WR_HIGHVLD || (cur_state == ARR_WR_WDATA &&
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array_wr_frame_valid && array_wr_frame_ready)) begin
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array_caddr_vld_wr <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_ras_cnt <= 'd0;
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end else if (cur_state == ARR_WR_LOWCS) begin
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wr_ras_cnt <= array_inner_tras - 1'b1;
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end else if (wr_ras_cnt == 'd0) begin
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wr_ras_cnt <= wr_ras_cnt;
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end else begin
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wr_ras_cnt <= wr_ras_cnt - 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_rcd_cnt <= 'd0;
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end else if (cur_state == ARR_WR_LOWCS) begin
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wr_rcd_cnt <= array_inner_trcd_wr - 2'b10;
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end else if (cur_state == ARR_WR_RCD) begin
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if (wr_rcd_cnt == 'd0) begin
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wr_rcd_cnt <= wr_rcd_cnt;
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end else begin
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wr_rcd_cnt <= wr_rcd_cnt - 1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_wr_cnt <= 'd0;
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end else if (cur_state == ARR_WR_LOWCS) begin
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wr_wr_cnt <= array_inner_twr -1'b1;
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end else if (cur_state == ARR_WR_WR) begin
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if (wr_wr_cnt == 'd0) begin
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wr_wr_cnt <= wr_wr_cnt;
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end else begin
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wr_wr_cnt <= wr_wr_cnt -1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_rp_cnt <= 'd0;
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end else if (cur_state == ARR_WR_LOWCS) begin
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wr_rp_cnt <= array_inner_trp - 1'b1;
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end else if (cur_state == ARR_WR_RP) begin
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if (wr_rp_cnt == 'd0) begin
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wr_rp_cnt <= 'd0;
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end else begin
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wr_rp_cnt <= wr_rp_cnt - 1'b1;
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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single_flag_wr <= 1'b0;
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end else if (cur_state == ARR_WR_IDLE && array_wr_frame_valid && wsof) begin
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single_flag_wr <= weof;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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array_wdata_eof <= 'd0;
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end else if (array_wr_frame_valid && array_wr_frame_ready) begin
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array_wdata_eof <= weof;
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end else begin
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array_wdata_eof <= 'd0;
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end
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end
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endmodule |