111 lines
2.0 KiB
Verilog
111 lines
2.0 KiB
Verilog
module tb_apb_cfg;
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reg apb_pclk;
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reg apb_prstn;
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//from apb master
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reg apb_psel;
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reg apb_penable;
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reg apb_pwrite;
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reg [7:0] apb_paddr;
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reg [31:0] apb_wdata;
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//to apb master
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wire [31:0] apb_rdata;
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wire apb_pready;
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//cfg
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//mode ctrl
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wire mc_work_en;
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wire [1:0] axi_rw_priority;
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//
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wire [7:0] array_ras_cfg;
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wire [7:0] array_rp_cfg;
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wire [7:0] array_rc_cfg;
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//
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wire [7:0] array_rcd_wr_cfg;
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wire [7:0] array_wr_cfg;
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//
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wire [7:0] array_rcd_rd_cfg;
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wire [7:0] array_rtp_cfg;
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//
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wire [25:0] array_ref_period0;
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wire [25:0] array_ref_period1;
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wire array_ref_sel;
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apb_cfg u_apb_cfg(
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.apb_pclk(apb_pclk),
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.apb_prstn(apb_prstn),
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.apb_psel(apb_psel),
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.apb_penable(apb_penable),
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.apb_pwrite(apb_pwrite),
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.apb_paddr(apb_paddr),
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.apb_wdata(apb_wdata),
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.apb_rdata(apb_rdata),
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.apb_pready(apb_pready),
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.mc_work_en(mc_work_en),
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.axi_rw_priority(axi_rw_priority),
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.array_ras_cfg(array_ras_cfg),
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.array_rp_cfg(array_rp_cfg),
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.array_rc_cfg(array_rc_cfg),
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.array_rcd_wr_cfg(array_rcd_wr_cfg),
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.array_wr_cfg(array_wr_cfg),
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.array_rcd_rd_cfg(array_rcd_rd_cfg),
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.array_rtp_cfg(array_rtp_cfg),
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.array_ref_period0(array_ref_period0),
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.array_ref_period1(array_ref_period1),
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.array_ref_sel(array_ref_sel)
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);
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initial begin
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apb_pclk = 1'b0;
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apb_prstn = 1'b0;
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#20
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apb_prstn = 1'b1;
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end
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always #10 apb_pclk = ~apb_pclk;
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initial begin
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apb_psel = 1'b0;
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apb_penable = 1'b0;
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apb_pwrite = 1'b0;
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apb_paddr = 'b0;
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apb_wdata = 'b0;
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end
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//task wr
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task apb_wr;
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input apb_paddr_temp;
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input apb_wdata_temp;
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begin
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wait(apb_pready);
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@(negedge apb_pclk);
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apb_paddr = apb_paddr_temp;
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apb_wdata = apb_wdata_temp;
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apb_psel = 1'b1;
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apb_pwrite = 1'b1;
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apb_penable = 1'b0;
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@(posedge apb_pclk);
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#0.7
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apb_penable = 1'b1;
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wait(apb_pready);
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@(posedge apb_pclk);
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apb_psel = 1'b0;
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apb_pwrite = 1'b0;
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apb_penable = 1'b0;
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end
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endtask
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initial begin
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#50
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apb_wr(8'h00,{31'b0,1'b1});
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$finish;
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end
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endmodule
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