117 lines
1.9 KiB
Verilog
117 lines
1.9 KiB
Verilog
`timescale 1ns/1ps
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module tb_wchannel;
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reg clk;
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reg rst_n;
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reg axi_s_awvalid;
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wire axi_s_awready;
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reg [7:0] axi_s_awlen;
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reg [25:0] axi_s_awaddr;
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reg axi_s_wvalid;
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wire axi_s_wready;
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reg [63:0] axi_s_wdata;
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reg axi_s_wlast;
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wire wframe_valid;
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wire [159:0] wframe_data;
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reg wframe_ready;
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wchannel u_wchannel(
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.clk(clk),
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.rst_n(rst_n),
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.axi_s_awvalid(axi_s_awvalid),
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.axi_s_awready(axi_s_awready),
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.axi_s_awlen(axi_s_awlen),
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.axi_s_awaddr(axi_s_awaddr),
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.axi_s_wvalid(axi_s_wvalid),
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.axi_s_wready(axi_s_wready),
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.axi_s_wdata(axi_s_wdata),
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.axi_s_wlast(axi_s_wlast),
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.wframe_valid(wframe_valid),
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.wframe_data(wframe_data),
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.wframe_ready(wframe_ready)
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);
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initial begin
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clk = 0;
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forever begin
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#10 clk = ~clk;
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end
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end
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initial begin
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rst_n = 1'b0;
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axi_s_awvalid = 1'b0;
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axi_s_awlen = 8'b0;
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axi_s_wvalid = 1'b0;
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axi_s_wdata = 64'b0;
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axi_s_wlast = 1'b0;
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wframe_ready = 1'b1;
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@(posedge clk) begin
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rst_n <= 1'b1;
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end
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aw(8'd5,{16'h0,6'h3f,4'h0});
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aw(8'd3,26'h20);
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w(64'd1,0);
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w(64'd2,0);
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w(64'd3,0);
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w(64'd4,0);
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w(64'd5,0);
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w(64'd6,1);
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@(posedge clk) begin
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axi_s_wvalid <= 1'b0;
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end
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w(64'd6,0);
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w(64'd7,0);
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@(posedge clk) begin
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axi_s_wvalid <= 1'b0;
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end
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$display("end");
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#100;
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$finish;
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end
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task aw;
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input [7:0] awlen;
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input [25:0] awaddr;
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begin
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@(posedge clk) begin
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axi_s_awvalid <= 1'b1;
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axi_s_awaddr <= awaddr;
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axi_s_awlen <= awlen;
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end
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#1;
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wait(axi_s_awready);
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@(posedge clk) begin
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axi_s_awvalid <= 1'b0;
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end
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end
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endtask
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task w;
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input [63:0] wdata;
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input wlast;
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begin
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@(posedge clk) begin
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axi_s_wvalid <= 1'b1;
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axi_s_wdata <= wdata;
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axi_s_wlast <= wlast;
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$display("wdata is %0h",wdata);
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end
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#1;
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wait(axi_s_wready);
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@(posedge clk) begin
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axi_s_wvalid <= 1'b0;
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end
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end
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endtask
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initial begin
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0,tb_wchannel,"+all");
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end
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endmodule
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