IPA/sim/verdiLog/compiler.log

*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
Command arguments:
    +define+verilog
    -f rtl.f
        ../rtl/data_cache/sync_fifo.v
        ../rtl/data_cache/async_fifo.v
        ../rtl/data_cache/histogram_ctrl.v
        ../rtl/data_cache/data_assemble.v
        ../rtl/data_cache/axi_write_ctrl.v
        ../rtl/data_cache/rst_sync.v
        ../rtl/data_cache/data_cache.v
    tb.f


*Error* nonconstant index
"../rtl/data_cache/async_fifo.v", 79: 

*Error* nonconstant index
"../rtl/data_cache/async_fifo.v", 80: 

*Error* nonconstant index
"../rtl/data_cache/async_fifo.v", 82: 

*Error* nonconstant index
"../rtl/data_cache/async_fifo.v", 83: 

*Error* Syntax error at .
"tb.f", 5: 
Highest level modules:
data_cache


*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch0'
"../rtl/data_cache/data_cache.v", 198: 

*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch0'
"../rtl/data_cache/data_cache.v", 199: 

*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch1'
"../rtl/data_cache/data_cache.v", 200: 

*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch1'
"../rtl/data_cache/data_cache.v", 201: 

*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch2'
"../rtl/data_cache/data_cache.v", 202: 

*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch2'
"../rtl/data_cache/data_cache.v", 203: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awid'
"../rtl/data_cache/data_cache.v", 253: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awaddr'
"../rtl/data_cache/data_cache.v", 254: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awlen'
"../rtl/data_cache/data_cache.v", 255: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awsize'
"../rtl/data_cache/data_cache.v", 256: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awburst'
"../rtl/data_cache/data_cache.v", 257: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awlock'
"../rtl/data_cache/data_cache.v", 258: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awcache'
"../rtl/data_cache/data_cache.v", 259: 

*Warning* port sizes differ (5 vs 4) in port connection (port axi_m_awcache)
"../rtl/data_cache/data_cache.v", 259: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awprot'
"../rtl/data_cache/data_cache.v", 260: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awqos'
"../rtl/data_cache/data_cache.v", 261: 

*Warning* port sizes differ (5 vs 4) in port connection (port axi_m_awqos)
"../rtl/data_cache/data_cache.v", 261: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awvalid'
"../rtl/data_cache/data_cache.v", 262: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wid'
"../rtl/data_cache/data_cache.v", 264: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wdata'
"../rtl/data_cache/data_cache.v", 265: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wstrb'
"../rtl/data_cache/data_cache.v", 266: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wlast'
"../rtl/data_cache/data_cache.v", 267: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wvalid'
"../rtl/data_cache/data_cache.v", 268: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_bready'
"../rtl/data_cache/data_cache.v", 273: 

*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_busy'
"../rtl/data_cache/data_cache.v", 274: 
Total	28 error(s),   2 warning(s)