cache module
This commit is contained in:
Core_kingdom
85
rtl/data_cache/async_fifo.v
Normal file
85
rtl/data_cache/async_fifo.v
Normal file
@@ -0,0 +1,85 @@
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module async_fifo #(
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parameter DATA_WIDTH = 8,
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parameter FIFO_DEPTH = 16
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)(
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input wr_clk,
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input wr_rst_n,
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input wr_en,
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input [DATA_WIDTH-1:0] wr_data,
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output full,
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input rd_clk,
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input rd_rst_n,
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input rd_en,
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output [DATA_WIDTH-1:0] rd_data,
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output empty
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);
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reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0];
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reg [$clog2(FIFO_DEPTH) : 0] wr_ptr, rd_ptr;
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integer i;
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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wr_ptr <= 'd0;
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for(i=0;i<FIFO_DEPTH;i=i+1) begin
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mem[i] <= 'd0;
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end
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end else if(wr_en && !full) begin
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mem[wr_ptr[$clog2(FIFO_DEPTH)-1:0]] <= wr_data;
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wr_ptr <= wr_ptr + 1'b1;
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end else begin
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wr_ptr <= wr_ptr;
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end
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end
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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rd_ptr <= 'd0;
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end else if(rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'b1;
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end else begin
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rd_ptr <= rd_ptr;
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end
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end
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wire [$clog2(FIFO_DEPTH):0] wr_ptr_g , rd_ptr_g;
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assign wr_ptr_g = wr_ptr ^(wr_ptr >>1);
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assign rd_ptr_g = rd_ptr ^(rd_ptr >>1);
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reg [$clog2(FIFO_DEPTH):0] wr_ptr_gr , wr_ptr_grr;
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reg [$clog2(FIFO_DEPTH):0] rd_ptr_gr , rd_ptr_grr;
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always@(posedge rd_clk or negedge rd_rst_n) begin
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if(!rd_rst_n) begin
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wr_ptr_gr <= 0;
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wr_ptr_grr <=0;
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end else begin
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wr_ptr_gr <= wr_ptr_g;
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wr_ptr_grr <= wr_ptr_gr;
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end
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end
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always@(posedge wr_clk or negedge wr_rst_n) begin
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if(!wr_rst_n) begin
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rd_ptr_gr <= 0;
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rd_ptr_grr <=0;
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end else begin
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rd_ptr_gr <= rd_ptr_g;
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rd_ptr_grr <= rd_ptr_gr;
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end
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end
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assign rd_data = mem[rd_ptr[$clog2(FIFO_DEPTH)-1:0]];
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assign full = ((wr_ptr_g[$clog2(FIFO_DEPTH)] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]) && (wr_ptr_g[$clog2(FIFO_DEPTH)-1] !=
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rd_ptr_grr[$clog2(FIFO_DEPTH)]-1) && (wr_ptr_g[$clog2(FIFO_DEPTH)-2:0] ==
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rd_ptr_grr[$clog2(FIFO_DEPTH)-2 : 0])) ? 1:0;
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assign empty = (rd_ptr_g[$clog2(FIFO_DEPTH) : 0] ==
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wr_ptr_grr[$clog2(FIFO_DEPTH) :0]) ? 1:0;
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endmodule
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196
rtl/data_cache/axi_write_ctrl.v
Normal file
196
rtl/data_cache/axi_write_ctrl.v
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@@ -0,0 +1,196 @@
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module axi_write_ctrl #(
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parameter AXI_ID_W = 8, // AXI ID位宽
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parameter AXI_ADDR_W = 32, // AXI地址位宽
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parameter AXI_DATA_W = 256, // AXI数据位宽
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parameter AXI_STRB_W = AXI_DATA_W / 8 // 字节选通位宽(256bit对应32字节)
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) (
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input wire clk, // 系统时钟
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input wire rst_n, // 异步复位，低有效
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// 控制与数据输入
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input wire start_en, // 写事务启动使能
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input wire [AXI_ADDR_W-1:0] sram_base_addr, // SRAM基地址
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input wire [AXI_DATA_W-1:0] fifo_rd_data, // FIFO读数据
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input wire fifo_empty, // FIFO空标志
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output reg fifo_rd_en, // FIFO读使能
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// AXI AW通道
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output reg [AXI_ID_W-1:0] axi_m_awid, // 写地址ID
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output reg [AXI_ADDR_W-1:0] axi_m_awaddr, // 写地址
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output reg [3:0] axi_m_awlen, // 突发长度(0表示1个数据)
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output reg [2:0] axi_m_awsize, // 数据宽度(5对应32字节)
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output reg [1:0] axi_m_awburst, // 突发类型(0表示增量)
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output reg axi_m_awlock, // 锁定信号(0表示普通访问)
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output reg [4:0] axi_m_awcache, // 缓存属性(0表示非缓存)
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output reg [2:0] axi_m_awprot, // 保护属性(0表示普通)
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output reg [4:0] axi_m_awqos, // QoS优先级(0表示默认)
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output reg axi_m_awvalid, // 写地址有效
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input wire axi_m_awready, // 写地址就绪
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// AXI W通道
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output reg [AXI_ID_W-1:0] axi_m_wid, // 写数据ID
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output reg [AXI_DATA_W-1:0] axi_m_wdata, // 写数据
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output reg [AXI_STRB_W-1:0] axi_m_wstrb, // 字节选通(全1表示所有字节有效)
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output reg axi_m_wlast, // 突发结束标志
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output reg axi_m_wvalid, // 写数据有效
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input wire axi_m_wready, // 写数据就绪
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// AXI B通道
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input wire [AXI_ID_W-1:0] axi_m_bid, // 写响应ID
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input wire [1:0] axi_m_bresp, // 写响应(0表示OKAY)
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input wire axi_m_bvalid, // 写响应有效
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output reg axi_m_bready, // 写响应就绪
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// 状态输出
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output reg axi_busy, // AXI写事务忙
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output reg axi_done // AXI写事务完成
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);
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// 内部信号定义
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reg [AXI_ADDR_W-1:0] curr_addr; // 当前写地址(基于基地址递增)
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reg [1:0] axi_state; // AXI状态机状态寄存器
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// 状态定义
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localparam AXI_IDLE = 2'd0; // 空闲状态
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localparam AXI_AW = 2'd1; // 地址通道传输状态
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localparam AXI_W = 2'd2; // 数据通道传输状态
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localparam AXI_B = 2'd3; // 响应通道传输状态
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// 1. AXI状态机时序逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_state <= AXI_IDLE;
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curr_addr <= {AXI_ADDR_W{1'b0}};
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axi_busy <= 1'b0;
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axi_done <= 1'b0;
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end else begin
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axi_done <= 1'b0; // 单周期有效
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case (axi_state)
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AXI_IDLE: begin
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axi_busy <= 1'b0;
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// 启动条件: 使能信号有效且FIFO非空
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if (start_en && !fifo_empty) begin
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axi_state <= AXI_AW;
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axi_busy <= 1'b1;
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// 初始化当前地址为基地址(首次)或保持上次地址(连续传输)
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curr_addr <= (curr_addr == {AXI_ADDR_W{1'b0}}) ? sram_base_addr : curr_addr;
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end
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end
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AXI_AW: begin
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// 地址通道握手完成，进入数据通道
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if (axi_m_awvalid && axi_m_awready) begin
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axi_state <= AXI_W;
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// 预计算下一次地址(当前地址 + 数据宽度字节数)
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curr_addr <= curr_addr + (AXI_DATA_W / 8);
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end
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end
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AXI_W: begin
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// 数据通道握手完成，进入响应通道
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if (axi_m_wvalid && axi_m_wready) begin
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axi_state <= AXI_B;
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end
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end
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AXI_B: begin
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// 响应通道握手完成，事务结束
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if (axi_m_bvalid && axi_m_bready) begin
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axi_state <= AXI_IDLE;
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axi_done <= 1'b1; // 标记事务完成
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end
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end
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endcase
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end
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end
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// 2. AXI AW通道信号生成逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_awid <= {AXI_ID_W{1'b0}};
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axi_m_awaddr <= {AXI_ADDR_W{1'b0}};
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axi_m_awlen <= 4'd0;
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axi_m_awsize <= 3'd5; // 5对应32字节(2^5 = 32)
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axi_m_awburst <= 2'd0; // 0表示INCR(增量)突发
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axi_m_awlock <= 1'b0;
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axi_m_awcache <= 5'd0; // 非缓存、非缓冲
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axi_m_awprot <= 3'd0; // 普通非特权数据访问
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axi_m_awqos <= 5'd0; // 默认QoS级别
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axi_m_awvalid <= 1'b0;
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end else begin
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case (axi_state)
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AXI_AW: begin
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axi_m_awid <= 8'd0; // 固定ID为0
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axi_m_awaddr <= curr_addr; // 当前地址
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axi_m_awlen <= 4'd0; // 突发长度为1(0+1)
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axi_m_awsize <= 3'd5; // 保持32字节宽度
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axi_m_awburst <= 2'd0; // 保持增量突发
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axi_m_awvalid <= 1'b1; // 地址有效
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end
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default: begin
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axi_m_awvalid <= 1'b0; // 非地址状态时无效
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end
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endcase
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end
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end
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// 3. AXI W通道信号生成逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_wid <= {AXI_ID_W{1'b0}};
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axi_m_wdata <= {AXI_DATA_W{1'b0}};
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axi_m_wstrb <= {AXI_STRB_W{1'b1}}; // 所有字节有效
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axi_m_wlast <= 1'b1; // 单拍突发，始终为1
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axi_m_wvalid <= 1'b0;
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fifo_rd_en <= 1'b0;
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end else begin
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case (axi_state)
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AXI_AW: begin
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// 地址握手完成前预读FIFO
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if (axi_m_awready) begin
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fifo_rd_en <= 1'b1; // 读取FIFO数据
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axi_m_wid <= 8'd0; // 与AW通道ID保持一致
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axi_m_wdata <= fifo_rd_data; // 锁存FIFO数据
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axi_m_wvalid <= 1'b1; // 数据有效
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end else begin
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fifo_rd_en <= 1'b0;
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axi_m_wvalid <= 1'b0;
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end
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end
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AXI_W: begin
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fifo_rd_en <= 1'b0; // 停止读FIFO
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// 数据握手完成后失效
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if (axi_m_wready) begin
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axi_m_wvalid <= 1'b0;
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end
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end
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default: begin
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fifo_rd_en <= 1'b0;
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axi_m_wvalid <= 1'b0;
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end
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endcase
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end
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end
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// 4. AXI B通道信号生成逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_bready <= 1'b0;
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end else begin
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case (axi_state)
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AXI_B: begin
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axi_m_bready <= 1'b1; // 准备接收响应
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// 响应握手完成后失效
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if (axi_m_bvalid) begin
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axi_m_bready <= 1'b0;
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end
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end
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default: begin
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axi_m_bready <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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109
rtl/data_cache/data_assemble.v
Normal file
109
rtl/data_cache/data_assemble.v
Normal file
@@ -0,0 +1,109 @@
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module data_assemble #(
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parameter PIXEL_WIDTH = 8, // 单通道像素位宽
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parameter GRAY_PIXEL_CNT = 32, // Gray模式：32个8bit→256bit
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parameter RGB_PIXEL_CNT = 8 // RGB模式：8个32bit（24bit数据+8bit补零）→256bit
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) (
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input wire clk,
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input wire rst_n,
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input wire en, // 拼接使能
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input wire input_pixel_type, // 0=Gray，1=RGB
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input wire [PIXEL_WIDTH-1:0] ir_ch0, // CH0数据
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input wire [PIXEL_WIDTH-1:0] ir_ch1, // CH1数据
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input wire [PIXEL_WIDTH-1:0] ir_ch2, // CH2数据
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input wire pixel_valid, // 像素有效
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output reg done, // 拼接完成（256bit就绪）
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output reg [255:0] assembled_data // 拼接后256bit数据
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);
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// 内部信号
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reg [4:0] gray_cnt; // Gray模式计数器（0~31）
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reg [2:0] rgb_cnt; // RGB模式计数器（0~7）
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reg [255:0] data_reg; // 拼接数据寄存器
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reg sync_out,sync_out_r;
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// 拼接计数器复位逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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gray_cnt <= 5'd0;
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rgb_cnt <= 3'd0;
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end else if (!en) begin
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gray_cnt <= 5'd0;
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rgb_cnt <= 3'd0;
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end else if (pixel_valid) begin
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case (input_pixel_type)
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1'b0: begin // Gray模式
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gray_cnt <= (gray_cnt == GRAY_PIXEL_CNT ) ? 5'd0 : gray_cnt + 5'd1;
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end
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1'b1: begin // RGB模式
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rgb_cnt <= (rgb_cnt == RGB_PIXEL_CNT ) ? 3'd0 : rgb_cnt + 3'd1;
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end
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endcase
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end
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end
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// 数据拼接逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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data_reg <= 256'd0;
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assembled_data <= 256'd0;
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sync_out <= 'd0;
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sync_out_r <= 'd0;
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end else if (!en) begin
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sync_out <= 'd0;
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data_reg <= 256'd0;
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assembled_data <= 256'd0;
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done <= 'd0;
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end else if (pixel_valid) begin
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case (input_pixel_type)
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1'b0: begin // Gray模式：32x8bit→256bit（高位到低位拼接）
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data_reg[(GRAY_PIXEL_CNT -1- gray_cnt) * PIXEL_WIDTH +: PIXEL_WIDTH] <= ir_ch0;
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// 计数器满：拼接完成，锁存数据
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if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin
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sync_out = 1'd1;
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//data_reg <= 256'd0; // 复位寄存器，准备下一轮
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end
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end
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1'b1: begin // RGB模式：8x32bit→256bit（32bit=8bit补零+CH2+CH1+CH0）
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reg [31:0] rgb_pixel;
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rgb_pixel = {8'd0, ir_ch2, ir_ch1, ir_ch0}; // 补零+三通道数据
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data_reg[(RGB_PIXEL_CNT - 1 - rgb_cnt) * 32 +: 32] <= rgb_pixel;
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// 计数器满：拼接完成，锁存数据
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if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin
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sync_out = 1'd1;
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//data_reg <= 256'd0; // 复位寄存器，准备下一轮
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end
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end
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endcase
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sync_out_r <= 'd0;
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end else begin
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sync_out_r <= sync_out;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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assembled_data <= 'd0;
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done <= 'd0;
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end else if (sync_out_r) begin
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assembled_data <= data_reg;
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done <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (done == 1'b1) begin
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done <= 'd0;
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end
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end
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endmodule
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470
rtl/data_cache/data_cache.v
Normal file
470
rtl/data_cache/data_cache.v
Normal file
@@ -0,0 +1,470 @@
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module data_cache #(
|
||||
// 异步FIFO参数（IR→系统时钟域）
|
||||
parameter ASYNC_FIFO_DEPTH = 1024, // 异步FIFO深度
|
||||
parameter ASYNC_FIFO_DATA_W = 27, // 27bit=1(ir_valid)+1(ir_vs)+1(ir_hs)+8(ch0)+8(ch1)+8(ch2)
|
||||
// 同步FIFO参数（系统时钟域，256bit数据缓存）
|
||||
parameter SYNC_FIFO_DEPTH = 2048, // 同步FIFO深度（适配256x256图像）
|
||||
parameter SYNC_FIFO_DATA_W = 256, // 同步FIFO数据位宽（AXI写数据位宽）
|
||||
// 直方图RAM参数（1x256，每个通道1个）
|
||||
parameter HIST_RAM_DEPTH = 256, // 直方图RAM深度（0~255，对应8bit像素值）
|
||||
parameter HIST_RAM_DATA_W = 1, // 直方图RAM数据位宽（1bit：存在标记）
|
||||
// AXI参数
|
||||
parameter AXI_ID_W = 8, // AXI AW/W ID位宽
|
||||
parameter AXI_ADDR_W = 32, // AXI地址位宽
|
||||
parameter AXI_DATA_W = 256, // AXI数据位宽（与SYNC_FIFO_DATA_W一致）
|
||||
parameter AXI_STRB_W = AXI_DATA_W / 8 // AXI WSTRB位宽（32bit）
|
||||
) (
|
||||
// -------------------------- Common 端口 --------------------------
|
||||
input wire clk, // 系统时钟（AXI/控制逻辑时钟）
|
||||
input wire rst_n, // 系统复位（低有效，同步clk）
|
||||
// -------------------------- 配置信号端口 --------------------------
|
||||
input wire ipa_en, // IPA总使能
|
||||
input wire update_src_trig, // 更新原始图像触发（高有效）
|
||||
input wire input_pixel_type, // 输入像素类型：0=Gray，1=RGB
|
||||
input wire [15:0] src_pixel_height, // 原始图像高度
|
||||
input wire [15:0] src_pixel_width, // 原始图像宽度
|
||||
input wire [15:0] histogram_low_num, // 直方图低位数（计算min用）
|
||||
input wire [15:0] histogram_high_num, // 直方图高位数（计算max用）
|
||||
output reg src_image_cache_done, // 原始图像缓存完成（高有效）
|
||||
// -------------------------- 连接Windowed模块端口 --------------------------
|
||||
output reg [7:0] dwidth_conv_min_ch0, // CH0归一化min值
|
||||
output reg [7:0] dwidth_conv_max_ch0, // CH0归一化max值
|
||||
output reg [7:0] dwidth_conv_min_ch1, // CH1归一化min值
|
||||
output reg [7:0] dwidth_conv_max_ch1, // CH1归一化max值
|
||||
output reg [7:0] dwidth_conv_min_ch2, // CH2归一化min值
|
||||
output reg [7:0] dwidth_conv_max_ch2, // CH2归一化max值
|
||||
// -------------------------- IR图像输入端口（IR时钟域） --------------------------
|
||||
input wire ir_clk, // IR像素同步时钟
|
||||
input wire ir_valid, // IR像素有效信号
|
||||
input wire ir_vs, // IR垂直同步（帧起始）
|
||||
input wire ir_hs, // IR水平同步（行起始）
|
||||
input wire [7:0] ir_ch0, // IR CH0数据（Gray时有效）
|
||||
input wire [7:0] ir_ch1, // IR CH1数据（RGB时有效）
|
||||
input wire [7:0] ir_ch2, // IR CH2数据（RGB时有效）
|
||||
// -------------------------- AXI写总线端口（系统时钟域） --------------------------
|
||||
output reg [AXI_ID_W-1:0] axi_m_awid, // AXI AW通道ID
|
||||
output reg [AXI_ADDR_W-1:0] axi_m_awaddr, // AXI AW通道地址（SRAM起始地址）
|
||||
output reg [3:0] axi_m_awlen, // AXI AW通道突发长度（0=1拍）
|
||||
output reg [2:0] axi_m_awsize, // AXI AW通道数据宽度（5=32字节=256bit）
|
||||
output reg [1:0] axi_m_awburst, // AXI AW通道突发类型（0=INCR）
|
||||
output reg axi_m_awlock, // AXI AW通道锁定（0=普通）
|
||||
output reg [3:0] axi_m_awcache, // AXI AW通道缓存属性（0=非缓存）
|
||||
output reg [2:0] axi_m_awprot, // AXI AW通道保护属性（0=普通）
|
||||
output reg [3:0] axi_m_awqos, // AXI AW通道QoS（0=默认）
|
||||
output reg axi_m_awvalid, // AXI AW通道有效
|
||||
input wire axi_m_awready, // AXI AW通道就绪
|
||||
output reg [AXI_ID_W-1:0] axi_m_wid, // AXI W通道ID（与AW一致）
|
||||
output reg [AXI_DATA_W-1:0] axi_m_wdata, // AXI W通道数据（256bit）
|
||||
output reg [AXI_STRB_W-1:0] axi_m_wstrb, // AXI W通道字节使能（全1=有效）
|
||||
output reg axi_m_wlast, // AXI W通道突发结束标记
|
||||
output reg axi_m_wvalid, // AXI W通道有效
|
||||
input wire axi_m_wready, // AXI W通道就绪
|
||||
input wire [AXI_ID_W-1:0] axi_m_bid, // AXI B通道ID
|
||||
input wire [1:0] axi_m_bresp, // AXI B通道响应（0=OKAY）
|
||||
input wire axi_m_bvalid, // AXI B通道有效
|
||||
output reg axi_m_bready // AXI B通道就绪
|
||||
);
|
||||
|
||||
// -------------------------- 内部信号定义 --------------------------
|
||||
// 1. 复位同步（跨时钟域复位处理）
|
||||
wire rst_n_ir; // IR时钟域同步后的复位
|
||||
wire rst_n_sys; // 系统时钟域同步后的复位
|
||||
|
||||
// 2. 异步FIFO信号（IR→系统时钟域）
|
||||
wire async_fifo_wr_en; // 异步FIFO写使能（IR时钟域）
|
||||
wire [ASYNC_FIFO_DATA_W-1:0] async_fifo_wr_data; // 异步FIFO写数据（IR时钟域）
|
||||
wire async_fifo_full; // 异步FIFO满（IR时钟域）
|
||||
wire async_fifo_rd_en; // 异步FIFO读使能（系统时钟域）
|
||||
wire [ASYNC_FIFO_DATA_W-1:0] async_fifo_rd_data; // 异步FIFO读数据（系统时钟域）
|
||||
wire async_fifo_empty; // 异步FIFO空（系统时钟域）
|
||||
|
||||
// 3. 跨域后像素信号（系统时钟域）
|
||||
wire ir_valid_sys; // 跨域后像素有效
|
||||
wire ir_vs_sys; // 跨域后帧起始
|
||||
wire ir_hs_sys; // 跨域后行起始
|
||||
wire [7:0] ir_ch0_sys; // 跨域后CH0数据
|
||||
wire [7:0] ir_ch1_sys; // 跨域后CH1数据
|
||||
wire [7:0] ir_ch2_sys; // 跨域后CH2数据
|
||||
reg flag;
|
||||
|
||||
// 4. 直方图控制信号
|
||||
wire hist_rst; // 直方图RAM复位（帧起始/更新触发）
|
||||
wire hist_wr_en_ch0; // CH0直方图写使能
|
||||
wire [7:0] hist_wr_addr_ch0; // CH0直方图写地址（像素值）
|
||||
wire hist_wr_en_ch1; // CH1直方图写使能
|
||||
wire [7:0] hist_wr_addr_ch1; // CH1直方图写地址（像素值）
|
||||
wire hist_wr_en_ch2; // CH2直方图写使能
|
||||
wire [7:0] hist_wr_addr_ch2; // CH2直方图写地址（像素值）
|
||||
reg hist_calc_en; // 直方图min/max计算使能（帧结束后）
|
||||
wire hist_calc_done; // 直方图min/max计算完成
|
||||
|
||||
// 5. 数据拼接信号
|
||||
wire assemble_en; // 数据拼接使能
|
||||
wire assemble_done; // 数据拼接完成（256bit就绪）
|
||||
wire [255:0] assemble_data; // 拼接后256bit数据
|
||||
|
||||
// 6. 同步FIFO信号（系统时钟域）
|
||||
wire sync_fifo_wr_en; // 同步FIFO写使能
|
||||
wire [255:0] sync_fifo_wr_data;// 同步FIFO写数据（拼接后256bit）
|
||||
wire sync_fifo_full; // 同步FIFO满
|
||||
wire sync_fifo_rd_en; // 同步FIFO读使能
|
||||
wire [255:0] sync_fifo_rd_data;// 同步FIFO读数据
|
||||
wire sync_fifo_empty; // 同步FIFO空
|
||||
|
||||
// 7. 帧计数与状态信号
|
||||
reg [15:0] col_cnt; // 列计数器（像素宽度计数）
|
||||
reg [15:0] row_cnt; // 行计数器（像素高度计数）
|
||||
reg frame_active; // 帧活跃标记（IR_VS后到帧结束）
|
||||
reg axi_write_busy; // AXI写事务忙标记
|
||||
wire axi_write_done; // 来自 axi_write_ctrl 的写完成标志
|
||||
|
||||
// 8. 状态机定义
|
||||
// typedef enum logic [2:0] {
|
||||
// S_IDLE, // 空闲（等待IPA使能）
|
||||
// S_WAIT_VS, // 等待帧起始（IR_VS）
|
||||
// S_RECEIVE_DATA, // 接收像素数据（写直方图+拼接）
|
||||
// S_WRITE_FIFO, // 拼接完成写同步FIFO
|
||||
// S_WAIT_AXI, // 等待AXI写完成
|
||||
// S_FRAME_DONE // 帧缓存完成（置位src_image_cache_done）
|
||||
// } data_cache_state_t;
|
||||
|
||||
localparam [3:0] S_IDLE = 3'b000;
|
||||
localparam [3:0] S_WAIT_VS = 3'b001;
|
||||
localparam [3:0] S_RECEIVE_DATA = 3'b010;
|
||||
localparam [3:0] S_WRITE_FIFO = 3'b011;
|
||||
localparam [3:0] S_WAIT_AXI = 3'b100;
|
||||
localparam [3:0] S_FRAME_DONE = 3'b101;
|
||||
|
||||
reg [2:0] curr_state;
|
||||
reg [2:0] next_state;
|
||||
|
||||
|
||||
// -------------------------- 子模块实例化 --------------------------
|
||||
// 1. 复位同步（确保跨时钟域复位稳定）
|
||||
rst_sync #(
|
||||
.SYNC_STAGE(2) // 2级同步
|
||||
) u_rst_sync_ir (
|
||||
.clk(ir_clk),
|
||||
.rst_n_in(rst_n),
|
||||
.rst_n_out(rst_n_ir)
|
||||
);
|
||||
|
||||
rst_sync #(
|
||||
.SYNC_STAGE(2)
|
||||
) u_rst_sync_sys (
|
||||
.clk(clk),
|
||||
.rst_n_in(rst_n),
|
||||
.rst_n_out(rst_n_sys)
|
||||
);
|
||||
|
||||
// 2. 异步FIFO（IR时钟域→系统时钟域，传输像素数据+控制信号）
|
||||
async_fifo #(
|
||||
.FIFO_DEPTH(ASYNC_FIFO_DEPTH),
|
||||
.DATA_WIDTH(ASYNC_FIFO_DATA_W)
|
||||
) u_async_fifo (
|
||||
// 写端口（IR时钟域）
|
||||
.wr_clk(ir_clk),
|
||||
.wr_rst_n(rst_n_ir),
|
||||
.wr_en(async_fifo_wr_en),
|
||||
.wr_data(async_fifo_wr_data),
|
||||
.full(async_fifo_full),
|
||||
// 读端口（系统时钟域）
|
||||
.rd_clk(clk),
|
||||
.rd_rst_n(rst_n_sys),
|
||||
.rd_en(async_fifo_rd_en),
|
||||
.rd_data(async_fifo_rd_data),
|
||||
.empty(async_fifo_empty)
|
||||
);
|
||||
|
||||
// 3. 直方图控制模块（统计CH0/CH1/CH2直方图，计算min/max）
|
||||
histogram_ctrl #(
|
||||
.HIST_RAM_DEPTH(HIST_RAM_DEPTH),
|
||||
.HIST_RAM_DATA_W(HIST_RAM_DATA_W)
|
||||
) u_histogram_ctrl (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n_sys),
|
||||
.hist_rst(hist_rst),
|
||||
.input_pixel_type(input_pixel_type),
|
||||
.hist_wr_en_ch0(hist_wr_en_ch0),
|
||||
.hist_wr_addr_ch0(hist_wr_addr_ch0),
|
||||
.hist_wr_en_ch1(hist_wr_en_ch1),
|
||||
.hist_wr_addr_ch1(hist_wr_addr_ch1),
|
||||
.hist_wr_en_ch2(hist_wr_en_ch2),
|
||||
.hist_wr_addr_ch2(hist_wr_addr_ch2),
|
||||
.histogram_low_num(histogram_low_num),
|
||||
.histogram_high_num(histogram_high_num),
|
||||
.calc_en(hist_calc_en),
|
||||
.calc_done(hist_calc_done),
|
||||
.dwidth_conv_min_ch0(dwidth_conv_min_ch0),
|
||||
.dwidth_conv_max_ch0(dwidth_conv_max_ch0),
|
||||
.dwidth_conv_min_ch1(dwidth_conv_min_ch1),
|
||||
.dwidth_conv_max_ch1(dwidth_conv_max_ch1),
|
||||
.dwidth_conv_min_ch2(dwidth_conv_min_ch2),
|
||||
.dwidth_conv_max_ch2(dwidth_conv_max_ch2)
|
||||
);
|
||||
|
||||
// 4. 数据拼接模块（Gray:32x8bit→256bit；RGB:8x32bit→256bit）
|
||||
data_assemble #(
|
||||
.PIXEL_WIDTH(8), // 单通道像素位宽
|
||||
.GRAY_PIXEL_CNT(32), // Gray模式拼接像素数（32x8bit=256bit）
|
||||
.RGB_PIXEL_CNT(8) // RGB模式拼接像素数（8x32bit=256bit）
|
||||
) u_data_assemble (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n_sys),
|
||||
.en(assemble_en),
|
||||
.input_pixel_type(input_pixel_type),
|
||||
.ir_ch0(ir_ch0_sys),
|
||||
.ir_ch1(ir_ch1_sys),
|
||||
.ir_ch2(ir_ch2_sys),
|
||||
.pixel_valid(async_fifo_rd_data[26]),
|
||||
.done(assemble_done),
|
||||
.assembled_data(assemble_data)
|
||||
);
|
||||
|
||||
// 5. 同步FIFO（缓存拼接后的256bit数据，适配AXI写速度）
|
||||
sync_fifo #(
|
||||
.FIFO_DEPTH(SYNC_FIFO_DEPTH),
|
||||
.DATA_WIDTH(SYNC_FIFO_DATA_W)
|
||||
) u_sync_fifo (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n_sys),
|
||||
.wr_en(sync_fifo_wr_en),
|
||||
.wr_data(sync_fifo_wr_data),
|
||||
.full(sync_fifo_full),
|
||||
.rd_en(sync_fifo_rd_en),
|
||||
.rd_data(sync_fifo_rd_data),
|
||||
.empty(sync_fifo_empty)
|
||||
);
|
||||
|
||||
// 6. AXI写控制模块（从同步FIFO读数据，发起AXI写事务）
|
||||
axi_write_ctrl #(
|
||||
.AXI_ID_W(AXI_ID_W),
|
||||
.AXI_ADDR_W(AXI_ADDR_W),
|
||||
.AXI_DATA_W(AXI_DATA_W),
|
||||
.AXI_STRB_W(AXI_STRB_W)
|
||||
) u_axi_write_ctrl (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n_sys),
|
||||
.start_en(!sync_fifo_empty && !axi_write_busy), // FIFO非空且AXI空闲时启动
|
||||
.sram_base_addr(32'h0000_0000), // SRAM基地址（可配置）
|
||||
.fifo_rd_data(sync_fifo_rd_data),
|
||||
.fifo_empty(sync_fifo_empty),
|
||||
.fifo_rd_en(sync_fifo_rd_en),
|
||||
.axi_m_awid(axi_m_awid),
|
||||
.axi_m_awaddr(axi_m_awaddr),
|
||||
.axi_m_awlen(axi_m_awlen),
|
||||
.axi_m_awsize(axi_m_awsize),
|
||||
.axi_m_awburst(axi_m_awburst),
|
||||
.axi_m_awlock(axi_m_awlock),
|
||||
.axi_m_awcache(axi_m_awcache),
|
||||
.axi_m_awprot(axi_m_awprot),
|
||||
.axi_m_awqos(axi_m_awqos),
|
||||
.axi_m_awvalid(axi_m_awvalid),
|
||||
.axi_m_awready(axi_m_awready),
|
||||
.axi_m_wid(axi_m_wid),
|
||||
.axi_m_wdata(axi_m_wdata),
|
||||
.axi_m_wstrb(axi_m_wstrb),
|
||||
.axi_m_wlast(axi_m_wlast),
|
||||
.axi_m_wvalid(axi_m_wvalid),
|
||||
.axi_m_wready(axi_m_wready),
|
||||
.axi_m_bid(axi_m_bid),
|
||||
.axi_m_bresp(axi_m_bresp),
|
||||
.axi_m_bvalid(axi_m_bvalid),
|
||||
.axi_m_bready(axi_m_bready),
|
||||
.axi_busy(axi_write_busy),
|
||||
.axi_done(axi_write_done)
|
||||
);
|
||||
|
||||
|
||||
// -------------------------- 核心逻辑实现 --------------------------
|
||||
// assign flag = (col_cnt == src_pixel_width-1'd1);
|
||||
assign axi_write_done = (axi_m_bvalid && axi_m_bready);
|
||||
// 1. 异步FIFO写控制（IR时钟域）
|
||||
assign async_fifo_wr_data = {ir_valid, ir_vs, ir_hs, ir_ch2, ir_ch1, ir_ch0};
|
||||
assign async_fifo_wr_en = ir_valid && !async_fifo_full && ipa_en; // 像素有效且FIFO未满
|
||||
|
||||
// 2. 异步FIFO读控制（系统时钟域）
|
||||
assign async_fifo_rd_en = !async_fifo_empty &&
|
||||
(curr_state == S_WAIT_VS || frame_active) && !flag; // 帧活跃且FIFO非空
|
||||
|
||||
// 3. 跨域后信号解析（系统时钟域）
|
||||
assign ir_valid_sys = async_fifo_rd_data[26] && !flag; // [26] = ir_valid
|
||||
assign ir_vs_sys = async_fifo_rd_data[25]; // [25] = ir_vs
|
||||
assign ir_hs_sys = async_fifo_rd_data[24]; // [24] = ir_hs
|
||||
assign ir_ch2_sys = async_fifo_rd_data[23:16];// [23:16] = ir_ch2
|
||||
assign ir_ch1_sys = async_fifo_rd_data[15:8]; // [15:8] = ir_ch1
|
||||
assign ir_ch0_sys = async_fifo_rd_data[7:0]; // [7:0] = ir_ch0
|
||||
|
||||
// 4. 直方图写控制（系统时钟域）
|
||||
assign hist_rst = update_src_trig || ir_vs_sys; // 更新触发或帧起始时复位直方图
|
||||
assign hist_wr_en_ch0 = ir_valid_sys && frame_active; // CH0始终写（Gray/RGB均有效）
|
||||
assign hist_wr_addr_ch0 = ir_ch0_sys;
|
||||
assign hist_wr_en_ch1 = ir_valid_sys && frame_active && (input_pixel_type == 1'b1); // RGB时写CH1
|
||||
assign hist_wr_addr_ch1 = ir_ch1_sys;
|
||||
assign hist_wr_en_ch2 = ir_valid_sys && frame_active && (input_pixel_type == 1'b1); // RGB时写CH2
|
||||
assign hist_wr_addr_ch2 = ir_ch2_sys;
|
||||
//assign hist_calc_en = (row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1); // 帧结束后计算min/max
|
||||
|
||||
// 5. 数据拼接使能控制
|
||||
assign assemble_en = frame_active && ir_valid_sys && !ir_vs_sys;
|
||||
|
||||
// 6. 同步FIFO写控制
|
||||
assign sync_fifo_wr_en = assemble_done && !sync_fifo_full;
|
||||
assign sync_fifo_wr_data = assemble_data;
|
||||
|
||||
// 7. 帧计数逻辑 - 修复frame_active激活（关键：不依赖frame_active读FIFO）
|
||||
always @(posedge clk or negedge rst_n_sys) begin
|
||||
if (!rst_n_sys) begin
|
||||
col_cnt <= 16'd0;
|
||||
row_cnt <= 16'd0;
|
||||
frame_active <= 1'b0;
|
||||
end else if (update_src_trig) begin
|
||||
col_cnt <= 16'd0;
|
||||
row_cnt <= 16'd0;
|
||||
frame_active <= 1'b0;
|
||||
end else if (ir_vs_sys && curr_state == S_WAIT_VS) begin
|
||||
// WAIT_VS状态下，ir_vs_sys=1 → 激活frame_active
|
||||
col_cnt <= 16'd0;
|
||||
row_cnt <= 16'd0;
|
||||
frame_active <= 1'b1;
|
||||
end else if (curr_state == S_RECEIVE_DATA) begin
|
||||
// RECEIVE_DATA状态下保持frame_active=1，直到帧结束
|
||||
frame_active <= 1'b1;
|
||||
if (ir_valid_sys && !ir_vs_sys) begin
|
||||
col_cnt <= col_cnt + 16'd1;
|
||||
if (col_cnt == src_pixel_width - 16'd1) begin
|
||||
col_cnt <= 16'd0;
|
||||
row_cnt <= row_cnt + 16'd1;
|
||||
if (row_cnt == src_pixel_height - 16'd1) begin
|
||||
frame_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
frame_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// 8. 状态机时序逻辑
|
||||
always @(posedge clk or negedge rst_n_sys) begin
|
||||
if (!rst_n_sys) begin
|
||||
curr_state <= S_IDLE;
|
||||
end else begin
|
||||
curr_state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
// 9. 状态机组合逻辑（状态转移）
|
||||
always @(*) begin
|
||||
next_state = curr_state;
|
||||
case (curr_state)
|
||||
S_IDLE: begin
|
||||
// 等待IPA使能
|
||||
if (ipa_en && !update_src_trig) begin
|
||||
next_state = S_WAIT_VS;
|
||||
end
|
||||
end
|
||||
S_WAIT_VS: begin
|
||||
// 等待帧起始（IR_VS）
|
||||
if (ir_vs_sys) begin
|
||||
next_state = S_RECEIVE_DATA;
|
||||
end else if (update_src_trig) begin
|
||||
next_state = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_RECEIVE_DATA: begin
|
||||
// 接收数据：直到帧结束（行/列计数满）
|
||||
if ((row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1)) begin
|
||||
next_state = S_WRITE_FIFO;
|
||||
end else if (update_src_trig) begin
|
||||
next_state = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_WRITE_FIFO: begin
|
||||
// 条件1：同步FIFO已空（数据已全部读出到AXI控制器），但AXI仍在忙碌 → 等待AXI完成
|
||||
if (sync_fifo_empty && axi_write_busy) begin
|
||||
next_state = S_WAIT_AXI;
|
||||
end
|
||||
// 条件2：同步FIFO已空，且AXI已完成所有写操作 → 直接进入帧完成
|
||||
else if (sync_fifo_empty && !axi_write_busy) begin
|
||||
next_state = S_FRAME_DONE;
|
||||
end
|
||||
// 条件3：收到更新触发 → 强制回到IDLE
|
||||
else if (update_src_trig) begin
|
||||
next_state = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_WAIT_AXI: begin
|
||||
// AXI写完成后进入帧完成状态
|
||||
if (axi_write_done) begin
|
||||
next_state = S_FRAME_DONE;
|
||||
end
|
||||
// 收到更新触发 → 强制回到IDLE
|
||||
else if (update_src_trig) begin
|
||||
next_state = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_FRAME_DONE: begin
|
||||
// 帧完成：保持1拍后回到等待VS（支持连续帧）
|
||||
if (src_image_cache_done) begin
|
||||
next_state = S_WAIT_VS;
|
||||
end else begin
|
||||
next_state = S_FRAME_DONE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// 10. 状态机输出逻辑（控制各模块行为）
|
||||
always @(posedge clk or negedge rst_n_sys) begin
|
||||
if (!rst_n_sys) begin
|
||||
src_image_cache_done <= 1'b0;
|
||||
end else begin
|
||||
src_image_cache_done <= 1'b0;
|
||||
case (curr_state)
|
||||
S_FRAME_DONE: begin
|
||||
// 帧完成：置位缓存完成信号，并等待直方图计算完成
|
||||
src_image_cache_done <= hist_calc_done;
|
||||
end
|
||||
default: begin
|
||||
src_image_cache_done <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rst_n_sys) begin
|
||||
if (!rst_n_sys) begin
|
||||
hist_calc_en <= 'd0;
|
||||
end else begin
|
||||
hist_calc_en <= (row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// always @(posedge clk or negedge rst_n_sys) begin
|
||||
// if (!rst_n_sys) begin
|
||||
// assemble_en <= 'd0;
|
||||
// end else begin
|
||||
// assemble_en <= frame_active && ir_valid_sys && !ir_vs_sys;
|
||||
// end
|
||||
|
||||
// end
|
||||
reg [1:0] flag_cnt;
|
||||
always @(posedge clk or negedge rst_n_sys) begin
|
||||
if (!rst_n_sys) begin
|
||||
flag <= 'd0;
|
||||
flag_cnt <='d0;
|
||||
end else if (flag == 1'b1)begin
|
||||
flag_cnt <= flag_cnt + 1'b1;
|
||||
if (flag_cnt == 2'd2) begin
|
||||
flag <= 'd0;
|
||||
flag_cnt <='d0;
|
||||
end
|
||||
end else if (col_cnt == src_pixel_width-1'd1) begin
|
||||
flag <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
231
rtl/data_cache/histogram_ctrl.v
Normal file
231
rtl/data_cache/histogram_ctrl.v
Normal file
@@ -0,0 +1,231 @@
|
||||
module histogram_ctrl #(
|
||||
parameter HIST_RAM_DEPTH = 256,
|
||||
parameter HIST_RAM_DATA_W = 1
|
||||
) (
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
input wire hist_rst, // 直方图复位
|
||||
input wire input_pixel_type, // 0=Gray，1=RGB
|
||||
input wire hist_wr_en_ch0, // CH0写使能
|
||||
input wire [7:0] hist_wr_addr_ch0, // CH0写地址（像素值0~255）
|
||||
input wire hist_wr_en_ch1, // CH1写使能
|
||||
input wire [7:0] hist_wr_addr_ch1, // CH1写地址
|
||||
input wire hist_wr_en_ch2, // CH2写使能
|
||||
input wire [7:0] hist_wr_addr_ch2, // CH2写地址
|
||||
input wire [15:0] histogram_low_num, // 低位数（计算min）
|
||||
input wire [15:0] histogram_high_num,// 高位数（计算max）
|
||||
input wire calc_en, // 计算使能
|
||||
output reg calc_done, // 计算完成
|
||||
output reg [7:0] dwidth_conv_min_ch0,
|
||||
output reg [7:0] dwidth_conv_max_ch0,
|
||||
output reg [7:0] dwidth_conv_min_ch1,
|
||||
output reg [7:0] dwidth_conv_max_ch1,
|
||||
output reg [7:0] dwidth_conv_min_ch2,
|
||||
output reg [7:0] dwidth_conv_max_ch2
|
||||
);
|
||||
|
||||
// 内部信号
|
||||
reg [HIST_RAM_DATA_W-1:0] hist_ram_ch0 [HIST_RAM_DEPTH-1:0]; // CH0直方图RAM
|
||||
reg [HIST_RAM_DATA_W-1:0] hist_ram_ch1 [HIST_RAM_DEPTH-1:0]; // CH1直方图RAM
|
||||
reg [HIST_RAM_DATA_W-1:0] hist_ram_ch2 [HIST_RAM_DEPTH-1:0]; // CH2直方图RAM
|
||||
reg [7:0] calc_addr; // 遍历地址（0~255）
|
||||
reg [15:0] low_cnt_ch0; // CH0低位数计数器
|
||||
reg [15:0] high_cnt_ch0; // CH0高位数计数器
|
||||
reg [15:0] low_cnt_ch1; // CH1低位数计数器
|
||||
reg [15:0] high_cnt_ch1; // CH1高位数计数器
|
||||
reg [15:0] low_cnt_ch2; // CH2低位数计数器
|
||||
reg [15:0] high_cnt_ch2; // CH2高位数计数器
|
||||
reg calc_active; // 计算活跃标记
|
||||
|
||||
// 状态定义
|
||||
|
||||
localparam [1:0] S_HIST_IDLE = 2'b00;
|
||||
localparam [1:0] S_HIST_CLEAR = 2'b01;
|
||||
localparam [1:0] S_HIST_WRITE = 2'b10;
|
||||
localparam [1:0] S_HIST_CALC = 2'b11;
|
||||
|
||||
reg [1:0] curr_hist_state;
|
||||
reg [1:0] next_hist_state;
|
||||
|
||||
// 1. 状态机时序逻辑
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
curr_hist_state <= S_HIST_IDLE;
|
||||
end else begin
|
||||
curr_hist_state <= next_hist_state;
|
||||
end
|
||||
end
|
||||
|
||||
// 2. 状态机组合逻辑
|
||||
always @(*) begin
|
||||
next_hist_state = curr_hist_state;
|
||||
case (curr_hist_state)
|
||||
S_HIST_IDLE: begin
|
||||
if (hist_rst) begin
|
||||
next_hist_state = S_HIST_CLEAR;
|
||||
end else if (hist_wr_en_ch0 || hist_wr_en_ch1 || hist_wr_en_ch2) begin
|
||||
next_hist_state = S_HIST_WRITE;
|
||||
end else if (calc_en) begin
|
||||
next_hist_state = S_HIST_CALC;
|
||||
end
|
||||
end
|
||||
S_HIST_CLEAR: begin
|
||||
if (calc_addr == HIST_RAM_DEPTH - 1) begin
|
||||
next_hist_state = S_HIST_IDLE;
|
||||
end
|
||||
end
|
||||
S_HIST_WRITE: begin
|
||||
if (hist_rst) begin
|
||||
next_hist_state = S_HIST_CLEAR;
|
||||
end else if (calc_en) begin
|
||||
next_hist_state = S_HIST_CALC;
|
||||
end
|
||||
end
|
||||
S_HIST_CALC: begin
|
||||
if (calc_addr == HIST_RAM_DEPTH - 1) begin
|
||||
next_hist_state = S_HIST_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// 3. 直方图RAM复位/写逻辑
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
// 复位所有RAM
|
||||
integer i;
|
||||
for (i = 0; i < HIST_RAM_DEPTH; i = i+1) begin
|
||||
hist_ram_ch0[i] <= 1'b0;
|
||||
hist_ram_ch1[i] <= 1'b0;
|
||||
hist_ram_ch2[i] <= 1'b0;
|
||||
end
|
||||
calc_addr <= 8'd0;
|
||||
end else begin
|
||||
case (curr_hist_state)
|
||||
S_HIST_CLEAR: begin
|
||||
// 清空RAM（地址递增）
|
||||
hist_ram_ch0[calc_addr] <= 1'b0;
|
||||
hist_ram_ch1[calc_addr] <= 1'b0;
|
||||
hist_ram_ch2[calc_addr] <= 1'b0;
|
||||
calc_addr <= calc_addr + 8'd1;
|
||||
end
|
||||
S_HIST_WRITE: begin
|
||||
// CH0写（始终有效）
|
||||
if (hist_wr_en_ch0) begin
|
||||
hist_ram_ch0[hist_wr_addr_ch0] <= 1'b1; // 标记像素值存在
|
||||
end
|
||||
// CH1/CH2写（仅RGB模式有效）
|
||||
if (hist_wr_en_ch1 && (input_pixel_type == 1'b1)) begin
|
||||
hist_ram_ch1[hist_wr_addr_ch1] <= 1'b1;
|
||||
end
|
||||
if (hist_wr_en_ch2 && (input_pixel_type == 1'b1)) begin
|
||||
hist_ram_ch2[hist_wr_addr_ch2] <= 1'b1;
|
||||
end
|
||||
calc_addr <= 8'd0;
|
||||
end
|
||||
S_HIST_CALC: begin
|
||||
// 遍历地址递增
|
||||
calc_addr <= calc_addr + 8'd1;
|
||||
end
|
||||
default: begin
|
||||
calc_addr <= 8'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// 4. 修复后的直方图min/max计算逻辑（关键修复点）
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
low_cnt_ch0 <= 16'd0;
|
||||
high_cnt_ch0 <= 16'd0;
|
||||
low_cnt_ch1 <= 16'd0;
|
||||
high_cnt_ch1 <= 16'd0;
|
||||
low_cnt_ch2 <= 16'd0;
|
||||
high_cnt_ch2 <= 16'd0;
|
||||
dwidth_conv_min_ch0 <= 8'd0;
|
||||
dwidth_conv_max_ch0 <= 8'd255;
|
||||
dwidth_conv_min_ch1 <= 8'd0;
|
||||
dwidth_conv_max_ch1 <= 8'd255;
|
||||
dwidth_conv_min_ch2 <= 8'd0;
|
||||
dwidth_conv_max_ch2 <= 8'd255;
|
||||
calc_done <= 1'b0;
|
||||
calc_active <= 1'b0;
|
||||
end else begin
|
||||
calc_done <= 1'b0;
|
||||
case (curr_hist_state)
|
||||
S_HIST_CALC: begin
|
||||
calc_active <= 1'b1;
|
||||
// -------------------------- 关键修复1：计算开始时强制清零计数器 --------------------------
|
||||
if (calc_addr == 8'd0) begin // 遍历地址为0时（计算起始），清零所有计数器
|
||||
low_cnt_ch0 <= 16'd0;
|
||||
high_cnt_ch0 <= 16'd0;
|
||||
low_cnt_ch1 <= 16'd0;
|
||||
high_cnt_ch1 <= 16'd0;
|
||||
low_cnt_ch2 <= 16'd0;
|
||||
high_cnt_ch2 <= 16'd0;
|
||||
end
|
||||
|
||||
// -------------------------- CH0计算 --------------------------
|
||||
// min：0→255遍历，找第histogram_low_num个1
|
||||
if (low_cnt_ch0 < histogram_low_num && hist_ram_ch0[calc_addr] == 1'b1) begin
|
||||
low_cnt_ch0 <= low_cnt_ch0 + 16'd1;
|
||||
if (low_cnt_ch0 == histogram_low_num - 16'd1) begin
|
||||
dwidth_conv_min_ch0 <= calc_addr;
|
||||
end
|
||||
end
|
||||
// max：255→0遍历，找第histogram_high_num个1
|
||||
if (high_cnt_ch0 < histogram_high_num && hist_ram_ch0[255 - calc_addr] == 1'b1) begin
|
||||
high_cnt_ch0 <= high_cnt_ch0 + 16'd1;
|
||||
if (high_cnt_ch0 == histogram_high_num - 16'd1) begin
|
||||
dwidth_conv_max_ch0 <= 255 - calc_addr;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------- CH1计算（仅RGB模式） --------------------------
|
||||
if (input_pixel_type == 1'b1) begin
|
||||
if (low_cnt_ch1 < histogram_low_num && hist_ram_ch1[calc_addr] == 1'b1) begin
|
||||
low_cnt_ch1 <= low_cnt_ch1 + 16'd1;
|
||||
if (low_cnt_ch1 == histogram_low_num - 16'd1) begin
|
||||
dwidth_conv_min_ch1 <= calc_addr;
|
||||
end
|
||||
end
|
||||
if (high_cnt_ch1 < histogram_high_num && hist_ram_ch1[255 - calc_addr] == 1'b1) begin
|
||||
high_cnt_ch1 <= high_cnt_ch1 + 16'd1;
|
||||
if (high_cnt_ch1 == histogram_high_num - 16'd1) begin
|
||||
dwidth_conv_max_ch1 <= 255 - calc_addr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------- CH2计算（仅RGB模式） --------------------------
|
||||
if (input_pixel_type == 1'b1) begin
|
||||
if (low_cnt_ch2 < histogram_low_num && hist_ram_ch2[calc_addr] == 1'b1) begin
|
||||
low_cnt_ch2 <= low_cnt_ch2 + 16'd1;
|
||||
if (low_cnt_ch2 == histogram_low_num - 16'd1) begin
|
||||
dwidth_conv_min_ch2 <= calc_addr;
|
||||
end
|
||||
end
|
||||
if (high_cnt_ch2 < histogram_high_num && hist_ram_ch2[255 - calc_addr] == 1'b1) begin
|
||||
high_cnt_ch2 <= high_cnt_ch2 + 16'd1;
|
||||
if (high_cnt_ch2 == histogram_high_num - 16'd1) begin
|
||||
dwidth_conv_max_ch2 <= 255 - calc_addr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------- 遍历结束：置位完成信号 --------------------------
|
||||
if (calc_addr == HIST_RAM_DEPTH - 1) begin
|
||||
calc_done <= 1'b1;
|
||||
calc_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
calc_active <= 1'b0;
|
||||
calc_done <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
27
rtl/data_cache/rst_sync.v
Normal file
27
rtl/data_cache/rst_sync.v
Normal file
@@ -0,0 +1,27 @@
|
||||
module rst_sync #(
|
||||
parameter SYNC_STAGE = 2 // 同步级数（推荐2级）
|
||||
) (
|
||||
input wire clk,
|
||||
input wire rst_n_in,
|
||||
output reg rst_n_out
|
||||
);
|
||||
|
||||
reg [SYNC_STAGE-1:0] rst_sync_reg;
|
||||
|
||||
always @(posedge clk or negedge rst_n_in) begin
|
||||
if (!rst_n_in) begin
|
||||
rst_sync_reg <= {SYNC_STAGE{1'b0}};
|
||||
end else begin
|
||||
rst_sync_reg <= {rst_sync_reg[SYNC_STAGE-2:0], 1'b1};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rst_n_in) begin
|
||||
if (!rst_n_in) begin
|
||||
rst_n_out <= 1'b0;
|
||||
end else begin
|
||||
rst_n_out <= rst_sync_reg[SYNC_STAGE-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
73
rtl/data_cache/sync_fifo.v
Normal file
73
rtl/data_cache/sync_fifo.v
Normal file
@@ -0,0 +1,73 @@
|
||||
module sync_fifo #(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter FIFO_DEPTH = 16
|
||||
)(
|
||||
input clk,
|
||||
input rst_n,
|
||||
input wr_en,
|
||||
input [DATA_WIDTH-1:0] wr_data,
|
||||
output full,
|
||||
input rd_en,
|
||||
output [DATA_WIDTH-1:0] rd_data,
|
||||
output empty
|
||||
);
|
||||
localparam ADDR_WIDTH = $clog2(FIFO_DEPTH);
|
||||
reg [DATA_WIDTH-1:0] mem [0 : FIFO_DEPTH -1];
|
||||
reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr;
|
||||
wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr;
|
||||
|
||||
assign wr_addr = wr_ptr[ADDR_WIDTH -1:0];
|
||||
assign rd_addr = rd_ptr[ADDR_WIDTH -1:0];
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
wr_ptr <= 'd0;
|
||||
end else if(wr_en && !full) begin
|
||||
wr_ptr <= wr_ptr + 1'b1;
|
||||
end else begin
|
||||
wr_ptr <= wr_ptr;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
rd_ptr <= 'd0;
|
||||
end else if(rd_en && !empty) begin
|
||||
rd_ptr <= rd_ptr + 1'b1;
|
||||
end else begin
|
||||
rd_ptr <= rd_ptr;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
integer i;
|
||||
always@(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
for(i=0;i<FIFO_DEPTH;i=i+1) begin
|
||||
mem[i] <= 'd0;
|
||||
end
|
||||
end else if(wr_en && !full) begin
|
||||
mem[wr_addr] <= wr_data;
|
||||
end else begin
|
||||
mem[wr_addr] <= mem[wr_addr];
|
||||
end
|
||||
end
|
||||
|
||||
// always@(posedge clk or negedge rst_n) begin
|
||||
// if(!rst_n) begin
|
||||
// rd_data <= 'd0;
|
||||
// end else if(rd_en && !empty) begin
|
||||
// rd_data <= mem[rd_addr];
|
||||
// end else begin
|
||||
// rd_data <= rd_data;
|
||||
// end
|
||||
// end
|
||||
|
||||
assign rd_data = mem[rd_addr];
|
||||
|
||||
|
||||
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
|
||||
(wr_ptr[ADDR_WIDTH -1:0] == rd_ptr[ADDR_WIDTH -1:0])) ? 1:0;
|
||||
assign empty = (wr_ptr == rd_ptr) ? 1:0;
|
||||
|
||||
endmodule
|
||||
20
sim/Makefile
Executable file
20
sim/Makefile
Executable file
@@ -0,0 +1,20 @@
|
||||
find :
|
||||
find ../rtl -name "*.v" >>rtl.f
|
||||
find ../tb -name "*.v" >>tb.f
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
comp : clean vcs
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
vcs :
|
||||
vcs \
|
||||
-f rtl.f \
|
||||
-f tb.f \
|
||||
-timescale=1ns/1ps \
|
||||
-full64 -R +vc +v2k -sverilog -debug_access+all\
|
||||
| tee vcs.log
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
verdi :
|
||||
verdi -f rtl.f tb.f -ssf tb.fsdb &
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
clean :
|
||||
rm -rf *~ *.f core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd
|
||||
#-------------------------------------------------------------------------------------------------------
|
||||
116
sim/csrc/Makefile
Normal file
116
sim/csrc/Makefile
Normal file
@@ -0,0 +1,116 @@
|
||||
# Makefile generated by VCS to build your model
|
||||
# This file may be modified; VCS will not overwrite it unless -Mupdate is used
|
||||
|
||||
# define default verilog source directory
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Choose name of executable
|
||||
PRODUCTBASE=$(VSRC)/simv
|
||||
|
||||
PRODUCT=$(PRODUCTBASE)
|
||||
|
||||
# Product timestamp file. If product is newer than this one,
|
||||
# we will also re-link the product.
|
||||
PRODUCT_TIMESTAMP=product_timestamp
|
||||
|
||||
# Path to runtime library
|
||||
DEPLIBS=
|
||||
VCSUCLI=-lvcsucli
|
||||
RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o $(DEPLIBS)
|
||||
|
||||
VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
|
||||
# Strip Flags for target product
|
||||
STRIPFLAGS=
|
||||
|
||||
PRE_LDFLAGS= # Loader Flags
|
||||
LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib
|
||||
# Picarchive Flags
|
||||
PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir
|
||||
|
||||
# C run time startup
|
||||
CRT0=
|
||||
# C run time startup
|
||||
CRTN=
|
||||
# Machine specific libraries
|
||||
SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
|
||||
CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O0 -fno-strict-aliasing
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing
|
||||
|
||||
LD_PARTIAL_LOADER=ld
|
||||
# Partial linking
|
||||
LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
|
||||
ASFLAGS=
|
||||
LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs
|
||||
# Note: if make gives you errors about include, either get gmake, or
|
||||
# replace the following line with the contents of the file filelist,
|
||||
# EACH TIME IT CHANGES
|
||||
# included file defines OBJS, and is automatically generated by vcs
|
||||
include filelist
|
||||
|
||||
OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS)
|
||||
|
||||
product : $(PRODUCT_TIMESTAMP)
|
||||
@echo $(PRODUCT) up to date
|
||||
|
||||
objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)
|
||||
|
||||
clean :
|
||||
rm -f $(VCS_OBJS) $(CU_OBJS)
|
||||
|
||||
clobber : clean
|
||||
rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP)
|
||||
|
||||
picclean :
|
||||
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
||||
@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
|
||||
|
||||
product_clean_order :
|
||||
@$(MAKE) -f Makefile --no-print-directory picclean
|
||||
@$(MAKE) -f Makefile --no-print-directory product_order
|
||||
|
||||
product_order : $(PRODUCT)
|
||||
|
||||
$(PRODUCT_TIMESTAMP) : product_clean_order
|
||||
-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
|
||||
$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
|
||||
@rm -f csrc[0-9]*.o
|
||||
@touch $(PRODUCT_TIMESTAMP)
|
||||
@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
|
||||
|
||||
$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsnew.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsimprofile.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libuclinative.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ)
|
||||
@touch $(PRODUCT)
|
||||
|
||||
47
sim/csrc/Makefile.hsopt
Normal file
47
sim/csrc/Makefile.hsopt
Normal file
@@ -0,0 +1,47 @@
|
||||
# Makefile generated by VCS to build rmapats.so for your model
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
# Loader Flags
|
||||
LDFLAGS=
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing
|
||||
|
||||
ASFLAGS=
|
||||
LIBS=
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
|
||||
rmapats.so: $(HSOPT_OBJS)
|
||||
@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)
|
||||
BIN
sim/csrc/SIM_l.o
Normal file
BIN
sim/csrc/SIM_l.o
Normal file
Binary file not shown.
1
sim/csrc/_16331_archive_1.so
Symbolic link
1
sim/csrc/_16331_archive_1.so
Symbolic link
@@ -0,0 +1 @@
|
||||
.//../simv.daidir//_16331_archive_1.so
|
||||
964
sim/csrc/_vcs_pli_stub_.c
Normal file
964
sim/csrc/_vcs_pli_stub_.c
Normal file
@@ -0,0 +1,964 @@
|
||||
#ifndef _GNU_SOURCE
|
||||
#define _GNU_SOURCE
|
||||
#endif
|
||||
#include <stdio.h>
|
||||
#include <dlfcn.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern void* VCS_dlsymLookup(const char *);
|
||||
extern void vcsMsgReportNoSource1(const char *, const char*);
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
extern void novas_call_fsdbDumpvars(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvars
|
||||
void novas_call_fsdbDumpvars(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:misc */
|
||||
#ifndef __VCS_PLI_STUB_novas_misc
|
||||
#define __VCS_PLI_STUB_novas_misc
|
||||
extern void novas_misc(int data, int reason, int iparam );
|
||||
#pragma weak novas_misc
|
||||
void novas_misc(int data, int reason, int iparam )
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason, iparam );
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
|
||||
#endif /* __VCS_PLI_STUB_novas_misc */
|
||||
|
||||
/* PLI routine: $fsdbDumpvarsByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvarsByFile
|
||||
void novas_call_fsdbDumpvarsByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
|
||||
|
||||
/* PLI routine: $fsdbAddRuntimeSignal:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
|
||||
#pragma weak novas_call_fsdbAddRuntimeSignal
|
||||
void novas_call_fsdbAddRuntimeSignal(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
|
||||
|
||||
/* PLI routine: $sps_create_transaction_stream:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
extern void novas_call_sps_create_transaction_stream(int data, int reason);
|
||||
#pragma weak novas_call_sps_create_transaction_stream
|
||||
void novas_call_sps_create_transaction_stream(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
|
||||
|
||||
/* PLI routine: $sps_begin_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
extern void novas_call_sps_begin_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_begin_transaction
|
||||
void novas_call_sps_begin_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
|
||||
|
||||
/* PLI routine: $sps_end_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
extern void novas_call_sps_end_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_end_transaction
|
||||
void novas_call_sps_end_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
|
||||
|
||||
/* PLI routine: $sps_free_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
extern void novas_call_sps_free_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_free_transaction
|
||||
void novas_call_sps_free_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
|
||||
|
||||
/* PLI routine: $sps_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
extern void novas_call_sps_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_attribute
|
||||
void novas_call_sps_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
|
||||
|
||||
/* PLI routine: $sps_update_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
#define __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
extern void novas_call_sps_update_label(int data, int reason);
|
||||
#pragma weak novas_call_sps_update_label
|
||||
void novas_call_sps_update_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
|
||||
|
||||
/* PLI routine: $sps_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
extern void novas_call_sps_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_relation
|
||||
void novas_call_sps_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbWhatif:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
extern void novas_call_fsdbWhatif(int data, int reason);
|
||||
#pragma weak novas_call_fsdbWhatif
|
||||
void novas_call_fsdbWhatif(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
|
||||
|
||||
/* PLI routine: $paa_init:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_init
|
||||
#define __VCS_PLI_STUB_novas_call_paa_init
|
||||
extern void novas_call_paa_init(int data, int reason);
|
||||
#pragma weak novas_call_paa_init
|
||||
void novas_call_paa_init(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_init */
|
||||
|
||||
/* PLI routine: $paa_sync:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_sync
|
||||
#define __VCS_PLI_STUB_novas_call_paa_sync
|
||||
extern void novas_call_paa_sync(int data, int reason);
|
||||
#pragma weak novas_call_paa_sync
|
||||
void novas_call_paa_sync(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
extern void novas_call_fsdbDumpClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassMethod
|
||||
void novas_call_fsdbDumpClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassMethod
|
||||
void novas_call_fsdbSuppressClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassProp:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
extern void novas_call_fsdbSuppressClassProp(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassProp
|
||||
void novas_call_fsdbSuppressClassProp(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
|
||||
|
||||
/* PLI routine: $fsdbDumpMDAByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpMDAByFile
|
||||
void novas_call_fsdbDumpMDAByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_begin
|
||||
void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_define_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_stream_attribute
|
||||
void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_end
|
||||
void novas_call_fsdbEvent_create_stream_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
extern void novas_call_fsdbEvent_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_begin
|
||||
void novas_call_fsdbEvent_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_set_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
extern void novas_call_fsdbEvent_set_label(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_set_label
|
||||
void novas_call_fsdbEvent_set_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_attribute
|
||||
void novas_call_fsdbEvent_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_tag:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
extern void novas_call_fsdbEvent_add_tag(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_tag
|
||||
void novas_call_fsdbEvent_add_tag(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
|
||||
|
||||
/* PLI routine: $fsdbTrans_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
extern void novas_call_fsdbEvent_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_end
|
||||
void novas_call_fsdbEvent_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
extern void novas_call_fsdbEvent_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_relation
|
||||
void novas_call_fsdbEvent_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbTrans_get_error_code:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_get_error_code
|
||||
void novas_call_fsdbEvent_get_error_code(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_stream_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_stream_attribute
|
||||
void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_scope_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_scope_attribute
|
||||
void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
|
||||
|
||||
/* PLI routine: $sps_interactive:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
#define __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
extern void novas_call_sps_interactive(int data, int reason);
|
||||
#pragma weak novas_call_sps_interactive
|
||||
void novas_call_sps_interactive(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
|
||||
|
||||
/* PLI routine: $sps_test:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_test
|
||||
#define __VCS_PLI_STUB_novas_call_sps_test
|
||||
extern void novas_call_sps_test(int data, int reason);
|
||||
#pragma weak novas_call_sps_test
|
||||
void novas_call_sps_test(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_test */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObject:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
extern void novas_call_fsdbDumpClassObject(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObject
|
||||
void novas_call_fsdbDumpClassObject(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObjectByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObjectByFile
|
||||
void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
|
||||
|
||||
/* PLI routine: $ridbDump:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_ridbDump
|
||||
#define __VCS_PLI_STUB_novas_call_ridbDump
|
||||
extern void novas_call_ridbDump(int data, int reason);
|
||||
#pragma weak novas_call_ridbDump
|
||||
void novas_call_ridbDump(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
|
||||
|
||||
/* PLI routine: $sps_flush_file:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
#define __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
extern void novas_call_sps_flush_file(int data, int reason);
|
||||
#pragma weak novas_call_sps_flush_file
|
||||
void novas_call_sps_flush_file(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
|
||||
|
||||
/* PLI routine: $fsdbDumpSingle:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
extern void novas_call_fsdbDumpSingle(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpSingle
|
||||
void novas_call_fsdbDumpSingle(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
|
||||
|
||||
/* PLI routine: $fsdbDumpIO:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
extern void novas_call_fsdbDumpIO(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpIO
|
||||
void novas_call_fsdbDumpIO(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
BIN
sim/csrc/_vcs_pli_stub_.o
Normal file
BIN
sim/csrc/_vcs_pli_stub_.o
Normal file
Binary file not shown.
BIN
sim/csrc/archive.0/_16331_archive_1.a
Normal file
BIN
sim/csrc/archive.0/_16331_archive_1.a
Normal file
Binary file not shown.
3
sim/csrc/archive.0/_16331_archive_1.a.info
Normal file
3
sim/csrc/archive.0/_16331_archive_1.a.info
Normal file
@@ -0,0 +1,3 @@
|
||||
reYIK_d.o
|
||||
EULYA_d.o
|
||||
amcQwB.o
|
||||
BIN
sim/csrc/cgincr.sdb
Normal file
BIN
sim/csrc/cgincr.sdb
Normal file
Binary file not shown.
350
sim/csrc/cginfo.json
Normal file
350
sim/csrc/cginfo.json
Normal file
@@ -0,0 +1,350 @@
|
||||
{
|
||||
"cpu_cycles_pass2_start": 45448695155550,
|
||||
"PEModules": [],
|
||||
"rlimit": {
|
||||
"data": -1,
|
||||
"stack": -1
|
||||
},
|
||||
"cycles_program_begin": 45448290911142,
|
||||
"PrevCompiledModules": {},
|
||||
"CurCompileUdps": {},
|
||||
"perf": [
|
||||
{
|
||||
"stat": [
|
||||
"main",
|
||||
"entry",
|
||||
0.021094083786010742,
|
||||
0.046309999999999997,
|
||||
0.016108000000000001,
|
||||
211380,
|
||||
211380,
|
||||
0.0,
|
||||
0.0,
|
||||
1756197955.728925,
|
||||
45448291181971
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"entry",
|
||||
0.041102170944213867,
|
||||
0.051603000000000003,
|
||||
0.024726000000000001,
|
||||
267272,
|
||||
268072,
|
||||
0.0,
|
||||
0.0,
|
||||
1756197955.7489331,
|
||||
45448327167267
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doParsingAndDesignResolution",
|
||||
"exit",
|
||||
0.060034036636352539,
|
||||
0.068806999999999993,
|
||||
0.026464000000000001,
|
||||
268496,
|
||||
269144,
|
||||
0.0,
|
||||
0.0,
|
||||
1756197955.7678649,
|
||||
45448361287035
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"entry",
|
||||
0.061084985733032227,
|
||||
0.069100999999999996,
|
||||
0.027220999999999999,
|
||||
268496,
|
||||
269144,
|
||||
0.0,
|
||||
0.0,
|
||||
1756197955.7689159,
|
||||
45448363148795
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"entry",
|
||||
0.074229001998901367,
|
||||
0.079996999999999999,
|
||||
0.029472000000000002,
|
||||
269608,
|
||||
269612,
|
||||
0.0,
|
||||
0.0,
|
||||
1756197955.7820599,
|
||||
45448386873357
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doUptoVir2VcsNoSepCleanup",
|
||||
"exit",
|
||||
0.19600415229797363,
|
||||
0.13907700000000001,
|
||||
0.051239,
|
||||
271472,
|
||||
283820,
|
||||
0.0059670000000000001,
|
||||
0.034832000000000002,
|
||||
1756197955.9038351,
|
||||
45448606168370
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"entry",
|
||||
0.19611406326293945,
|
||||
0.139158,
|
||||
0.051269000000000002,
|
||||
271472,
|
||||
283820,
|
||||
0.0059670000000000001,
|
||||
0.034832000000000002,
|
||||
1756197955.903945,
|
||||
45448606320154
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doRadify_vir2vcsAll",
|
||||
"exit",
|
||||
0.20636320114135742,
|
||||
0.147649,
|
||||
0.053029,
|
||||
272676,
|
||||
283820,
|
||||
0.0059670000000000001,
|
||||
0.034832000000000002,
|
||||
1756197955.9141941,
|
||||
45448624886998
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doPostDesignResolutionToVir2Vcs",
|
||||
"exit",
|
||||
0.20646810531616211,
|
||||
0.147729,
|
||||
0.053057,
|
||||
272676,
|
||||
283820,
|
||||
0.0059670000000000001,
|
||||
0.034832000000000002,
|
||||
1756197955.914299,
|
||||
45448624978062
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"entry",
|
||||
0.20652103424072266,
|
||||
0.14776800000000001,
|
||||
0.053071,
|
||||
272676,
|
||||
283820,
|
||||
0.0059670000000000001,
|
||||
0.034832000000000002,
|
||||
1756197955.9143519,
|
||||
45448625073063
|
||||
],
|
||||
"sub": [
|
||||
{
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"entry",
|
||||
0.24538707733154297,
|
||||
0.14907799999999999,
|
||||
0.056294999999999998,
|
||||
271120,
|
||||
283820,
|
||||
0.0189,
|
||||
0.057668999999999998,
|
||||
1756197955.953218,
|
||||
45448695143967
|
||||
],
|
||||
"sub": []
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"DoPass2",
|
||||
"exit",
|
||||
0.42847418785095215,
|
||||
0.31499300000000002,
|
||||
0.073566999999999994,
|
||||
285232,
|
||||
285260,
|
||||
0.0189,
|
||||
0.057668999999999998,
|
||||
1756197956.1363051,
|
||||
45449024799828
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"doGAToPass2",
|
||||
"exit",
|
||||
0.43257713317871094,
|
||||
0.31767400000000001,
|
||||
0.074746000000000007,
|
||||
285232,
|
||||
285260,
|
||||
0.0189,
|
||||
0.057668999999999998,
|
||||
1756197956.140408,
|
||||
45449032197193
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"stat": [
|
||||
"main",
|
||||
"exit",
|
||||
0.43307614326477051,
|
||||
0.31807800000000003,
|
||||
0.074842000000000006,
|
||||
285224,
|
||||
285260,
|
||||
0.0189,
|
||||
0.057668999999999998,
|
||||
1756197956.140907,
|
||||
45449033076874
|
||||
],
|
||||
"sub": []
|
||||
}
|
||||
],
|
||||
"MlibObjs": {},
|
||||
"NameTable": {
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
3
|
||||
],
|
||||
"tb_data_cache": [
|
||||
"tb_data_cache",
|
||||
"EULYA",
|
||||
"module",
|
||||
2
|
||||
]
|
||||
},
|
||||
"CompileStrategy": "fullobj",
|
||||
"stat": {
|
||||
"Frontend(%)": 49.865292291989341,
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.0189,
|
||||
"ru_nvcsw": 26,
|
||||
"ru_minflt": 10715,
|
||||
"ru_stime_sec": 0.057668999999999998,
|
||||
"ru_maxrss_kb": 25896,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"ru_self_cgstart": {
|
||||
"ru_utime_sec": 0.14915900000000001,
|
||||
"ru_nvcsw": 30,
|
||||
"ru_minflt": 26649,
|
||||
"ru_stime_sec": 0.056326000000000001,
|
||||
"ru_maxrss_kb": 78204,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"totalObjSize": 405560,
|
||||
"peak_mem_kb": 285260,
|
||||
"cpu_cycles_cgstart": 45448695212266,
|
||||
"realTime": 0.43317604064941406,
|
||||
"outputSizePerQuad": 60.486204325130501,
|
||||
"ru_childs_cgstart": {
|
||||
"ru_utime_sec": 0.0189,
|
||||
"ru_nvcsw": 26,
|
||||
"ru_minflt": 10715,
|
||||
"ru_stime_sec": 0.057668999999999998,
|
||||
"ru_maxrss_kb": 25896,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"mop/quad": 2.4156599552572708,
|
||||
"nMops": 16197,
|
||||
"nQuads": 6705,
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.31812600000000002,
|
||||
"ru_nvcsw": 32,
|
||||
"ru_minflt": 31228,
|
||||
"ru_stime_sec": 0.074853000000000003,
|
||||
"ru_maxrss_kb": 92172,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"cpu_cycles_total": 742224958,
|
||||
"CodeGen(%)": 50.134707708010659,
|
||||
"cpu_cycles_end": 45449033136100,
|
||||
"mopSpeed": 95858.954707132143,
|
||||
"quadSpeed": 39682.304828753535
|
||||
},
|
||||
"CompileStatus": "Successful",
|
||||
"SIMBData": {
|
||||
"out": "amcQwB.o",
|
||||
"bytes": 121792,
|
||||
"text": 0,
|
||||
"archive": "archive.0/_16331_archive_1.a"
|
||||
},
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
],
|
||||
"CompileProcesses": [
|
||||
"cgproc.16331.json"
|
||||
],
|
||||
"incremental": "on",
|
||||
"CurCompileModules": [
|
||||
"...MASTER...",
|
||||
"...MASTER...",
|
||||
"std",
|
||||
"std",
|
||||
"tb_data_cache",
|
||||
"tb_data_cache"
|
||||
],
|
||||
"Misc": {
|
||||
"vcs_version": "O-2018.09-1_Full64",
|
||||
"vcs_build_date": "Build Date = Oct 12 2018 20:38:10",
|
||||
"master_pid": 16331,
|
||||
"VCS_HOME": "/home/synopsys/vcs-mx/O-2018.09-1",
|
||||
"cwd": "/home/ICer/ic_prjs/IPA/sim",
|
||||
"csrc": "csrc",
|
||||
"default_output_dir": "csrc",
|
||||
"hostname": "IC_EDA",
|
||||
"csrc_abs": "/home/ICer/ic_prjs/IPA/sim/csrc",
|
||||
"archive_dir": "archive.0",
|
||||
"daidir": "simv.daidir",
|
||||
"daidir_abs": "/home/ICer/ic_prjs/IPA/sim/simv.daidir"
|
||||
}
|
||||
}
|
||||
284
sim/csrc/cgproc.16331.json
Normal file
284
sim/csrc/cgproc.16331.json
Normal file
@@ -0,0 +1,284 @@
|
||||
{
|
||||
"stat": {
|
||||
"ru_self_end": {
|
||||
"ru_utime_sec": 0.31775999999999999,
|
||||
"ru_nvcsw": 32,
|
||||
"ru_minflt": 31224,
|
||||
"ru_stime_sec": 0.074767,
|
||||
"ru_maxrss_kb": 92172,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 4
|
||||
},
|
||||
"ru_childs_end": {
|
||||
"ru_utime_sec": 0.0189,
|
||||
"ru_nvcsw": 26,
|
||||
"ru_minflt": 10715,
|
||||
"ru_stime_sec": 0.057668999999999998,
|
||||
"ru_maxrss_kb": 25896,
|
||||
"ru_majflt": 0,
|
||||
"ru_nivcsw": 24
|
||||
},
|
||||
"cpu_cycles_end": 45449032347572,
|
||||
"peak_mem_kb": 285260
|
||||
},
|
||||
"Modules": {
|
||||
"tb_data_cache": {
|
||||
"Compiled": "Yes",
|
||||
"nQuads": 6487,
|
||||
"start_perf": [
|
||||
0.26711106300354004,
|
||||
0.162518,
|
||||
0.064589999999999995,
|
||||
277368,
|
||||
283820,
|
||||
1756197955.974942,
|
||||
45448734171870
|
||||
],
|
||||
"nRouts": 715,
|
||||
"child_modules": {},
|
||||
"Compiled Times": 1,
|
||||
"significant_routs": [
|
||||
[
|
||||
29,
|
||||
"R_VCSgd_EULYA_1d",
|
||||
2188698,
|
||||
95,
|
||||
7
|
||||
],
|
||||
[
|
||||
31,
|
||||
"R_VCSgd_EULYA_1f",
|
||||
3076549,
|
||||
2178,
|
||||
269
|
||||
],
|
||||
[
|
||||
264,
|
||||
"U_VCSgd_EULYA_264",
|
||||
4042811,
|
||||
3819,
|
||||
355
|
||||
],
|
||||
[
|
||||
274,
|
||||
"U_VCSgd_EULYA_274",
|
||||
5590207,
|
||||
4729,
|
||||
511
|
||||
],
|
||||
[
|
||||
328,
|
||||
"R_VCSgd_EULYA_148",
|
||||
2365361,
|
||||
2104,
|
||||
268
|
||||
],
|
||||
[
|
||||
346,
|
||||
"R_VCSgd_EULYA_15a",
|
||||
2456044,
|
||||
2612,
|
||||
300
|
||||
],
|
||||
[
|
||||
348,
|
||||
"R_VCSgd_EULYA_15c",
|
||||
3181664,
|
||||
2723,
|
||||
290
|
||||
],
|
||||
[
|
||||
374,
|
||||
"R_VCSgd_EULYA_176",
|
||||
3210868,
|
||||
3639,
|
||||
419
|
||||
],
|
||||
[
|
||||
376,
|
||||
"R_VCSgd_EULYA_178",
|
||||
9568540,
|
||||
8866,
|
||||
1042
|
||||
],
|
||||
[
|
||||
389,
|
||||
"R_VCSgd_EULYA_185",
|
||||
2166116,
|
||||
1120,
|
||||
148
|
||||
]
|
||||
],
|
||||
"end_perf": [
|
||||
0.42611598968505859,
|
||||
0.31456600000000001,
|
||||
0.071634000000000003,
|
||||
283572,
|
||||
283820,
|
||||
45449020587427,
|
||||
42949672961,
|
||||
0
|
||||
],
|
||||
"nMops": 15669
|
||||
},
|
||||
"...MASTER...": {
|
||||
"nQuads": 0,
|
||||
"start_perf": [
|
||||
0.24554800987243652,
|
||||
0.14919499999999999,
|
||||
0.056339,
|
||||
271120,
|
||||
283820,
|
||||
1756197955.9533789,
|
||||
45448695337291
|
||||
],
|
||||
"nRouts": 5,
|
||||
"child_modules": {
|
||||
"std": 1,
|
||||
"tb_data_cache": 1
|
||||
},
|
||||
"end_perf": [
|
||||
0.25063300132751465,
|
||||
0.15148200000000001,
|
||||
0.059139999999999998,
|
||||
273552,
|
||||
283820,
|
||||
45448704529239,
|
||||
0,
|
||||
0
|
||||
],
|
||||
"nMops": 0
|
||||
},
|
||||
"std": {
|
||||
"Compiled": "Yes",
|
||||
"nQuads": 218,
|
||||
"start_perf": [
|
||||
0.25073599815368652,
|
||||
0.151556,
|
||||
0.059168999999999999,
|
||||
273552,
|
||||
283820,
|
||||
1756197955.9585669,
|
||||
45448704686469
|
||||
],
|
||||
"nRouts": 33,
|
||||
"child_modules": {},
|
||||
"Compiled Times": 1,
|
||||
"significant_routs": [
|
||||
[
|
||||
1,
|
||||
"T_VCSgd_reYIK_1_0",
|
||||
2539467,
|
||||
138,
|
||||
13
|
||||
],
|
||||
[
|
||||
24,
|
||||
"F_VCSgd_reYIK_24_0",
|
||||
2405512,
|
||||
984,
|
||||
90
|
||||
]
|
||||
],
|
||||
"end_perf": [
|
||||
0.26701617240905762,
|
||||
0.16245000000000001,
|
||||
0.064562999999999995,
|
||||
277368,
|
||||
283820,
|
||||
45448734074536,
|
||||
8589934594,
|
||||
0
|
||||
],
|
||||
"svclass": [
|
||||
"$vcs_nba_dyn_obj",
|
||||
576,
|
||||
35,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"sigprop$$",
|
||||
576,
|
||||
35,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"process",
|
||||
2380,
|
||||
200,
|
||||
8,
|
||||
8,
|
||||
0,
|
||||
"event",
|
||||
597,
|
||||
34,
|
||||
2,
|
||||
2,
|
||||
0,
|
||||
"mailbox",
|
||||
1769,
|
||||
140,
|
||||
9,
|
||||
9,
|
||||
0,
|
||||
"semaphore",
|
||||
1119,
|
||||
84,
|
||||
5,
|
||||
5,
|
||||
0
|
||||
],
|
||||
"nMops": 528
|
||||
}
|
||||
},
|
||||
"ObjArchives": [
|
||||
{
|
||||
"archive": "archive.0/_16331_archive_1.a",
|
||||
"objects": [
|
||||
[
|
||||
"reYIK_d.o",
|
||||
43078
|
||||
],
|
||||
[
|
||||
"EULYA_d.o",
|
||||
232786
|
||||
],
|
||||
[
|
||||
"amcQwB.o",
|
||||
121792
|
||||
]
|
||||
],
|
||||
"size": 397656
|
||||
}
|
||||
],
|
||||
"CompUnits": {
|
||||
"EULYA_d": {
|
||||
"mod": "tb_data_cache",
|
||||
"out": "EULYA_d.o",
|
||||
"bytes": 232786,
|
||||
"text": 141941,
|
||||
"checksum": 0,
|
||||
"mode": 4,
|
||||
"archive": "archive.0/_16331_archive_1.a"
|
||||
},
|
||||
"reYIK_d": {
|
||||
"mod": "std",
|
||||
"out": "reYIK_d.o",
|
||||
"bytes": 43078,
|
||||
"text": 7325,
|
||||
"cls": 7017,
|
||||
"checksum": 0,
|
||||
"mode": 4,
|
||||
"archive": "archive.0/_16331_archive_1.a"
|
||||
},
|
||||
"amcQw_d": {
|
||||
"mod": "...MASTER...",
|
||||
"out": "objs/amcQw_d.o",
|
||||
"bytes": 7904,
|
||||
"text": 434,
|
||||
"checksum": 0,
|
||||
"mode": 4
|
||||
}
|
||||
},
|
||||
"reusePaths": {}
|
||||
}
|
||||
31
sim/csrc/filelist
Normal file
31
sim/csrc/filelist
Normal file
@@ -0,0 +1,31 @@
|
||||
|
||||
|
||||
AR=ar
|
||||
DOTLIBS=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
|
||||
# This file is automatically generated by VCS. Any changes you make to it
|
||||
# will be overwritten the next time VCS is run
|
||||
VCS_LIBEXT=
|
||||
XTRN_OBJS=
|
||||
|
||||
DPI_WRAPPER_OBJS =
|
||||
DPI_STUB_OBJS =
|
||||
# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
|
||||
include filelist.dpi
|
||||
PLI_STUB_OBJS =
|
||||
include filelist.pli
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
include filelist.cu
|
||||
|
||||
VCS_INCR_OBJS=
|
||||
|
||||
|
||||
AUGDIR=
|
||||
AUG_LDFLAGS=
|
||||
SHARED_OBJ_SO=
|
||||
|
||||
|
||||
|
||||
VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)
|
||||
33
sim/csrc/filelist.cu
Normal file
33
sim/csrc/filelist.cu
Normal file
@@ -0,0 +1,33 @@
|
||||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _16331_archive_1.so
|
||||
_16331_archive_1.so : archive.0/_16331_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_16331_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_16331_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
O0_OBJS =
|
||||
|
||||
$(O0_OBJS) : %.o: %.c
|
||||
$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
|
||||
|
||||
|
||||
%.o: %.c
|
||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
||||
CU_UDP_OBJS = \
|
||||
|
||||
|
||||
CU_LVL_OBJS = \
|
||||
SIM_l.o
|
||||
|
||||
MAIN_OBJS = \
|
||||
objs/amcQw_d.o
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
0
sim/csrc/filelist.dpi
Normal file
0
sim/csrc/filelist.dpi
Normal file
13
sim/csrc/filelist.hsopt
Normal file
13
sim/csrc/filelist.hsopt
Normal file
@@ -0,0 +1,13 @@
|
||||
rmapats_mop.o: rmapats.m
|
||||
@/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
|
||||
|
||||
rmapats.o: rmapats.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
|
||||
rmapats%.o: rmapats%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
rmar.o: rmar.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
|
||||
rmar%.o: rmar%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
|
||||
include filelist.hsopt.objs
|
||||
1
sim/csrc/filelist.hsopt.llvm2_0.objs
Normal file
1
sim/csrc/filelist.hsopt.llvm2_0.objs
Normal file
@@ -0,0 +1 @@
|
||||
LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o
|
||||
7
sim/csrc/filelist.hsopt.objs
Normal file
7
sim/csrc/filelist.hsopt.objs
Normal file
@@ -0,0 +1,7 @@
|
||||
HSOPT_OBJS +=rmapats_mop.o \
|
||||
rmapats.o \
|
||||
rmar.o rmar_nd.o
|
||||
|
||||
include filelist.hsopt.llvm2_0.objs
|
||||
HSOPT_OBJS += $(LLVM_OBJS)
|
||||
|
||||
4
sim/csrc/filelist.pli
Normal file
4
sim/csrc/filelist.pli
Normal file
@@ -0,0 +1,4 @@
|
||||
PLI_STUB_OBJS += _vcs_pli_stub_.o
|
||||
_vcs_pli_stub_.o: _vcs_pli_stub_.c
|
||||
@$(CC) -I/home/synopsys/vcs-mx/O-2018.09-1/include -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
|
||||
@strip -g _vcs_pli_stub_.o
|
||||
BIN
sim/csrc/hsim/hsim.sdb
Normal file
BIN
sim/csrc/hsim/hsim.sdb
Normal file
Binary file not shown.
0
sim/csrc/import_dpic.h
Normal file
0
sim/csrc/import_dpic.h
Normal file
BIN
sim/csrc/objs/amcQw_d.o
Normal file
BIN
sim/csrc/objs/amcQw_d.o
Normal file
Binary file not shown.
0
sim/csrc/product_timestamp
Normal file
0
sim/csrc/product_timestamp
Normal file
43
sim/csrc/rmapats.c
Normal file
43
sim/csrc/rmapats.c
Normal file
@@ -0,0 +1,43 @@
|
||||
// file = 0; split type = patterns; threshold = 100000; total count = 0.
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <strings.h>
|
||||
#include "rmapats.h"
|
||||
|
||||
void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685);
|
||||
void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685)
|
||||
{
|
||||
U I1546;
|
||||
U I1547;
|
||||
U I1548;
|
||||
struct futq * I1549;
|
||||
struct dummyq_struct * pQ = I1288;
|
||||
I1546 = ((U )vcs_clocks) + I685;
|
||||
I1548 = I1546 & ((1 << fHashTableSize) - 1);
|
||||
I1282->I727 = (EBLK *)(-1);
|
||||
I1282->I731 = I1546;
|
||||
if (I1546 < (U )vcs_clocks) {
|
||||
I1547 = ((U *)&vcs_clocks)[1];
|
||||
sched_millenium(pQ, I1282, I1547 + 1, I1546);
|
||||
}
|
||||
else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
|
||||
I1282->I733 = (struct eblk *)peblkFutQ1Tail;
|
||||
peblkFutQ1Tail->I727 = I1282;
|
||||
peblkFutQ1Tail = I1282;
|
||||
}
|
||||
else if ((I1549 = pQ->I1189[I1548].I745)) {
|
||||
I1282->I733 = (struct eblk *)I1549->I744;
|
||||
I1549->I744->I727 = (RP )I1282;
|
||||
I1549->I744 = (RmaEblk *)I1282;
|
||||
}
|
||||
else {
|
||||
sched_hsopt(pQ, I1282, I1546);
|
||||
}
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void SinitHsimPats(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
2453
sim/csrc/rmapats.h
Normal file
2453
sim/csrc/rmapats.h
Normal file
File diff suppressed because it is too large
Load Diff
0
sim/csrc/rmapats.m
Normal file
0
sim/csrc/rmapats.m
Normal file
BIN
sim/csrc/rmapats.o
Normal file
BIN
sim/csrc/rmapats.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmapats_mop.o
Normal file
BIN
sim/csrc/rmapats_mop.o
Normal file
Binary file not shown.
13
sim/csrc/rmar.c
Normal file
13
sim/csrc/rmar.c
Normal file
@@ -0,0 +1,13 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "rmar0.h"
|
||||
|
||||
// stubs for Hil functions
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void __Hil__Static_Init_Func__(void) {}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
18
sim/csrc/rmar.h
Normal file
18
sim/csrc/rmar.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef _RMAR1_H_
|
||||
#define _RMAR1_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __DO_RMAHDR_
|
||||
#include "rmar0.h"
|
||||
#endif /*__DO_RMAHDR_*/
|
||||
|
||||
extern UP rmaFunctionRtlArray[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
BIN
sim/csrc/rmar.o
Normal file
BIN
sim/csrc/rmar.o
Normal file
Binary file not shown.
13
sim/csrc/rmar0.h
Normal file
13
sim/csrc/rmar0.h
Normal file
@@ -0,0 +1,13 @@
|
||||
#ifndef _RMAR0_H_
|
||||
#define _RMAR0_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
BIN
sim/csrc/rmar_llvm_0_0.o
Normal file
BIN
sim/csrc/rmar_llvm_0_0.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmar_llvm_0_1.o
Normal file
BIN
sim/csrc/rmar_llvm_0_1.o
Normal file
Binary file not shown.
BIN
sim/csrc/rmar_nd.o
Normal file
BIN
sim/csrc/rmar_nd.o
Normal file
Binary file not shown.
20
sim/novas.conf
Normal file
20
sim/novas.conf
Normal file
@@ -0,0 +1,20 @@
|
||||
[qBaseWindow_saveRestoreSession_group]
|
||||
10=/home/ICer/ic_prjs/IPA/sim/verdiLog/novas_autosave.ses
|
||||
|
||||
[qDockerWindow_C]
|
||||
Verdi_1\position.x=-1
|
||||
Verdi_1\position.y=27
|
||||
Verdi_1\width=1280
|
||||
Verdi_1\height=921
|
||||
|
||||
[QwMainWindow]
|
||||
window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x5\0\0\0\x2\xfe\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\x7f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x2\xcb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x3\x32\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x3\x99\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)"
|
||||
window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xff\0\0\x3J\0\0\0\0\0\0\0\x1b\0\0\x4\xff\0\0\x3J\0\0\0\0\0\0)
|
||||
window\nWave_2\menubar=true
|
||||
window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x1:\x1\0\0\0\x1\0\0\0\0\x2)
|
||||
window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xe2\0\0\x4\x1e\x1\0\0\0\x1\0\0\0\0\x1)
|
||||
window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0[\0\0\0\0\0\0\x3\xbd\x1\0\0\0\x1\0\0\0\0\x1)
|
||||
window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xe2\0\0\x4\x1b\x1\0\0\0\x1\0\0\0\0\x1)
|
||||
window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0[\0\0\x3\xbd\x1\0\0\0\x1\0\0\0\0\x1)
|
||||
window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1)
|
||||
window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2)
|
||||
1369
sim/novas.rc
Normal file
1369
sim/novas.rc
Normal file
File diff suppressed because it is too large
Load Diff
359
sim/novas_dump.log
Normal file
359
sim/novas_dump.log
Normal file
@@ -0,0 +1,359 @@
|
||||
#######################################################################################
|
||||
# log primitive debug message of FSDB dumping #
|
||||
# This is for R&D to analyze when there are issues happening when FSDB dump #
|
||||
#######################################################################################
|
||||
ANF: vcsd_get_serial_mode_status('simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_thread_id('simv: undefined symbol: vcsd_get_thread_id')
|
||||
ANF: vcsd_get_power_scope_name('simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vcsd_node_check_native_callback('simv: undefined symbol: vcsd_node_check_native_callback')
|
||||
ANF: vcsd_node_add_native_callback('simv: undefined symbol: vcsd_node_add_native_callback')
|
||||
ANF: vcsdIsNativeVc('simv: undefined symbol: vcsdIsNativeVc')
|
||||
ANF: vhpi_get_cb_info('simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vdi_fn_trigger_native_init_force('simv: undefined symbol: vdi_fn_trigger_native_init_force')
|
||||
ANF: vdi_set_native_callback('simv: undefined symbol: vdi_set_native_callback')
|
||||
ANF: vdi_fn_check_native_callback('simv: undefined symbol: vdi_fn_check_native_callback')
|
||||
ANF: vdi_fn_add_native_callback('simv: undefined symbol: vdi_fn_add_native_callback')
|
||||
ANF: vhdi_dt_get_type('simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
VCS compile option:
|
||||
option[0]: simv
|
||||
option[1]: +vc
|
||||
option[2]: +v2k
|
||||
option[3]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
option[4]: -Mcc=gcc
|
||||
option[5]: -Mcplusplus=g++
|
||||
option[6]: -Masflags=
|
||||
option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
option[9]: -Mldflags= -rdynamic
|
||||
option[10]: -Mout=simv
|
||||
option[11]: -Mamsrun=
|
||||
option[12]: -Mvcsaceobjs=
|
||||
option[13]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
option[14]: -Mexternalobj=
|
||||
option[15]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
option[16]: -Mcrt0=
|
||||
option[17]: -Mcrtn=
|
||||
option[18]: -Mcsrc=
|
||||
option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[20]: -Xvcs_run_simv=1
|
||||
option[21]: -timescale=1ns/1ps
|
||||
option[22]: -full64
|
||||
option[23]: +vc
|
||||
option[24]: +v2k
|
||||
option[25]: -debug_access+all
|
||||
option[26]: +vpi
|
||||
option[27]: +vcsd1
|
||||
option[28]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
option[29]: -picarchive
|
||||
option[30]: -P
|
||||
option[31]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[32]: -fsdb
|
||||
option[33]: -sverilog
|
||||
option[34]: -gen_obj
|
||||
option[35]: -f
|
||||
option[36]: rtl.f
|
||||
option[37]: -f
|
||||
option[38]: tb.f
|
||||
option[39]: -load
|
||||
option[40]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[41]: timescale=1ns/1ps
|
||||
Chronologic Simulation VCS Release O-2018.09-1_Full64
|
||||
Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
|
||||
CPU cores: 8
|
||||
Limit information:
|
||||
======================================
|
||||
cputime unlimited
|
||||
filesize unlimited
|
||||
datasize unlimited
|
||||
stacksize 8192 kbytes
|
||||
coredumpsize 0 kbytes
|
||||
memoryuse unlimited
|
||||
vmemoryuse unlimited
|
||||
descriptors 4096
|
||||
memorylocked 64 kbytes
|
||||
maxproc 4096
|
||||
======================================
|
||||
(Special)Runtime environment variables:
|
||||
|
||||
Runtime environment variables:
|
||||
XDG_SESSION_ID=2
|
||||
HOSTNAME=IC_EDA
|
||||
TERM_PROGRAM=vscode
|
||||
UNAME=/bin/uname
|
||||
SELINUX_ROLE_REQUESTED=
|
||||
SCRNAME=vcs
|
||||
VCS_DEPTH=0
|
||||
SHELL=/bin/bash
|
||||
TERM=xterm-256color
|
||||
MAKEFLAGS=
|
||||
HISTSIZE=1000
|
||||
SSH_CLIENT=192.168.223.1 58217 22
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
SELINUX_USE_CURRENT_RANGE=
|
||||
TERM_PROGRAM_VERSION=1.85.2
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
LC_ALL=C
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
USER=ICer
|
||||
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib::/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib
|
||||
SCRIPT_NAME=vcs
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
VCS_MX_HOME_INTERNAL=1
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
SNPSLMD_LICENSE_FILE=27000@IC_EDA
|
||||
MAKELEVEL=1
|
||||
OVA_UUM=0
|
||||
MFLAGS=
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
VCS_MODE_FLAG=64
|
||||
PATH=.:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/remote-cli:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/bin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user:/usr/local/sbin:/usr/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
|
||||
MAIL=/var/spool/mail/ICer
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
PWD=/home/ICer/ic_prjs/IPA/sim
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
LANG=zh_CN.UTF-8
|
||||
KDEDIRS=/usr
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
VSCODE_GIT_ASKPASS_EXTRA_ARGS=
|
||||
VMR_MODE_FLAG=64
|
||||
SELINUX_LEVEL_REQUESTED=
|
||||
CDSHOME=/home/cadence/IC617
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
HISTCONTROL=ignoredups
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
SNPS_VCS_TMPDIR=/tmp/vcs_20250826084555_15976
|
||||
HOME=/home/ICer
|
||||
RISCV=/home/Riscv_Tools
|
||||
SHLVL=7
|
||||
VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js
|
||||
MGC_HOME=/home/mentor/
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
MGC_LICENSE_FILE=/home/mentor//license/license.dat
|
||||
CADHOME=/home/cadence
|
||||
VCS_COM=/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
LOGNAME=ICer
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
|
||||
SSH_CONNECTION=192.168.223.1 58217 192.168.223.129 22
|
||||
VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock
|
||||
VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-1591ffa4-a3ad-479f-90eb-871a7ef0f2ac.sock
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
BROWSER=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/helpers/browser.sh
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/IPA/sim
|
||||
VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node
|
||||
GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
VCS_ARCH=linux64
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
COLORTERM=truecolor
|
||||
_=./simv
|
||||
OLDPWD=/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch
|
||||
VCS_HEAP_EXEC=true
|
||||
VCS_PATHMAP_PRELOAD_DONE=1
|
||||
VCS_EXEC_DONE=1
|
||||
DVE=/home/synopsys/vcs-mx/O-2018.09-1/gui/dve
|
||||
SPECMAN_OUTPUT_TO_TTY=1
|
||||
Runtime command line arguments:
|
||||
argv[0]=simv
|
||||
argv[1]=+vc
|
||||
argv[2]=+v2k
|
||||
273 profile - 100
|
||||
CPU/Mem usage: 0.080 sys, 0.480 user, 245.62M mem
|
||||
274 Tue Aug 26 16:45:57 2025
|
||||
275 pliAppInit
|
||||
276 FSDB_GATE is set.
|
||||
277 FSDB_RTL is set.
|
||||
278 Enable Parallel Dumping.
|
||||
279 pliAppMiscSet: New Sim Round
|
||||
280 pliEntryInit
|
||||
281 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
282 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
283 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
284 sps_call_fsdbDumpfile_main at 0 : ../tb/data_cache/tb_data_cache.v(166)
|
||||
285 argv[0]: (tb.fsdb)
|
||||
286 *Verdi* : Create FSDB file 'tb.fsdb'
|
||||
287 compile option from '/home/ICer/ic_prjs/IPA/sim/simv.daidir/vcs_rebuild'.
|
||||
288 "vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1"
|
||||
289 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
290 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/data_cache/tb_data_cache.v(167)
|
||||
291 argv[0]: (0)
|
||||
292 argv[1]: (handle) tb_data_cache
|
||||
293 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
294 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
295 *Verdi* : Begin traversing the scope (tb_data_cache), layer (0).
|
||||
296 *Verdi* : End of traversing.
|
||||
297 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.130 sys, 0.490 user, 340.83M mem
|
||||
incr: 0.010 sys, 0.010 user, 7.38M mem
|
||||
accu: 0.010 sys, 0.010 user, 7.38M mem
|
||||
accu incr: 0.010 sys, 0.010 user, 7.38M mem
|
||||
|
||||
Count usage: 258 var, 214 idcode, 106 callback
|
||||
incr: 258 var, 214 idcode, 106 callback
|
||||
accu: 258 var, 214 idcode, 106 callback
|
||||
accu incr: 258 var, 214 idcode, 106 callback
|
||||
298 Tue Aug 26 16:45:57 2025
|
||||
299 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.130 sys, 0.490 user, 341.88M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.010 sys, 0.010 user, 8.43M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 258 var, 214 idcode, 106 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 258 var, 214 idcode, 106 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
300 Tue Aug 26 16:45:57 2025
|
||||
301 sps_call_fsdbDumpMDA_vd_main at 0 : ../tb/data_cache/tb_data_cache.v(168)
|
||||
302 argv[0]: (0)
|
||||
303 argv[1]: (handle) tb_data_cache
|
||||
304 *Verdi* : Begin traversing the MDAs under scope (tb_data_cache), layer (0).
|
||||
305 *Verdi* : Enable +mda and +packedmda dumping.
|
||||
306 *Verdi* : End of traversing the MDAs.
|
||||
307 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.140 sys, 0.490 user, 341.88M mem
|
||||
incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.00M mem
|
||||
accu incr: 0.010 sys, 0.000 user, 0.00M mem
|
||||
|
||||
Count usage: 4098 var, 4054 idcode, 111 callback
|
||||
incr: 3840 var, 3840 idcode, 5 callback
|
||||
accu: 3840 var, 3840 idcode, 5 callback
|
||||
accu incr: 3840 var, 3840 idcode, 5 callback
|
||||
308 Tue Aug 26 16:45:57 2025
|
||||
309 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.140 sys, 0.490 user, 342.16M mem
|
||||
incr: 0.000 sys, 0.000 user, 0.28M mem
|
||||
accu: 0.010 sys, 0.000 user, 0.28M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 0.28M mem
|
||||
|
||||
Count usage: 4098 var, 4054 idcode, 111 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 3840 var, 3840 idcode, 5 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
310 Tue Aug 26 16:45:57 2025
|
||||
311 End of simulation at 36076000
|
||||
312 Tue Aug 26 16:45:57 2025
|
||||
313 Begin FSDB profile info:
|
||||
314 FSDB Writer : bc1(35379) bcn(99202) mtf/stf(0/0)
|
||||
FSDB Writer elapsed time : flush(0.033912) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
315 End FSDB profile info
|
||||
316 Parallel profile - Flush:4 Expand:0 ProduceWait:0 ConsumerWait:1 BlockUsed:2
|
||||
317 ProduceTime:0.730205081 ConsumerTime:0.021449033 Buffer:64MB
|
||||
318 SimExit
|
||||
319 Sim process exit
|
||||
7
sim/rtl.f
Normal file
7
sim/rtl.f
Normal file
@@ -0,0 +1,7 @@
|
||||
../rtl/data_cache/sync_fifo.v
|
||||
../rtl/data_cache/async_fifo.v
|
||||
../rtl/data_cache/histogram_ctrl.v
|
||||
../rtl/data_cache/data_assemble.v
|
||||
../rtl/data_cache/axi_write_ctrl.v
|
||||
../rtl/data_cache/rst_sync.v
|
||||
../rtl/data_cache/data_cache.v
|
||||
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.normal_done
Normal file
0
sim/simv.daidir/.normal_done
Normal file
129
sim/simv.daidir/.vcs.timestamp
Normal file
129
sim/simv.daidir/.vcs.timestamp
Normal file
@@ -0,0 +1,129 @@
|
||||
0
|
||||
34
|
||||
+itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
+v2k
|
||||
+vc
|
||||
+vcsd1
|
||||
+vpi
|
||||
-Mamsrun=
|
||||
-Masflags=
|
||||
-Mcc=gcc
|
||||
-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
-Mcplusplus=g++
|
||||
-Mcrt0=
|
||||
-Mcrtn=
|
||||
-Mcsrc=
|
||||
-Mexternalobj=
|
||||
-Mldflags= -rdynamic
|
||||
-Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
-Mout=simv
|
||||
-Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
|
||||
-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
-Mvcsaceobjs=
|
||||
-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
|
||||
-P
|
||||
-Xvcs_run_simv=1
|
||||
-debug_access+all
|
||||
-f rtl.f
|
||||
-f tb.f
|
||||
-fsdb
|
||||
-full64
|
||||
-gen_obj
|
||||
-picarchive
|
||||
-sverilog
|
||||
-timescale=1ns/1ps
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
|
||||
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
71
|
||||
sysc_uni_pwd=/home/ICer/ic_prjs/IPA/sim
|
||||
XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
|
||||
XDG_SESSION_ID=2
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
|
||||
VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-1591ffa4-a3ad-479f-90eb-871a7ef0f2ac.sock
|
||||
VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock
|
||||
VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node
|
||||
VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js
|
||||
VSCODE_GIT_ASKPASS_EXTRA_ARGS=
|
||||
VMR_MODE_FLAG=64
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
VCS_MX_HOME_INTERNAL=1
|
||||
VCS_MODE_FLAG=64
|
||||
VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
VCS_DEPTH=0
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
VCS_ARCH=linux64
|
||||
UNAME=/bin/uname
|
||||
TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
|
||||
TERM_PROGRAM_VERSION=1.85.2
|
||||
TERM_PROGRAM=vscode
|
||||
SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
|
||||
SSH_CONNECTION=192.168.223.1 58217 192.168.223.129 22
|
||||
SSH_CLIENT=192.168.223.1 58217 22
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
|
||||
SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
|
||||
SELINUX_USE_CURRENT_RANGE=
|
||||
SELINUX_ROLE_REQUESTED=
|
||||
SELINUX_LEVEL_REQUESTED=
|
||||
SCRNAME=vcs
|
||||
SCRIPT_NAME=vcs
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
RISCV=/home/Riscv_Tools
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
OVA_UUM=0
|
||||
MMSIMHOME=/home/cadence/MMSIM151
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
MGC_LICENSE_FILE=/home/mentor//license/license.dat
|
||||
MGC_HOME=/home/mentor/
|
||||
MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
|
||||
MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
|
||||
MFLAGS=
|
||||
MAKE_TERMOUT=/dev/pts/1
|
||||
MAKE_TERMERR=/dev/pts/1
|
||||
MAKELEVEL=1
|
||||
MAKEFLAGS=
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
LC_ALL=C
|
||||
KDEDIRS=/usr
|
||||
INCISIVE_HOME=/home/cadence/INCISIVE152
|
||||
ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
|
||||
HISTCONTROL=ignoredups
|
||||
GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh
|
||||
DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
COLORTERM=truecolor
|
||||
CDS_LIC_FILE=/home/cadence/license/cadence.dat
|
||||
CDSHOME=/home/cadence/IC617
|
||||
CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
|
||||
CADHOME=/home/cadence
|
||||
0
|
||||
12
|
||||
1756197905 ../tb/data_cache/tb_data_cache.v
|
||||
1756194528 ../rtl/data_cache/data_cache.v
|
||||
1756115099 ../rtl/data_cache/rst_sync.v
|
||||
1756112329 ../rtl/data_cache/axi_write_ctrl.v
|
||||
1756197232 ../rtl/data_cache/data_assemble.v
|
||||
1756109175 ../rtl/data_cache/histogram_ctrl.v
|
||||
1756107950 ../rtl/data_cache/async_fifo.v
|
||||
1756106550 ../rtl/data_cache/sync_fifo.v
|
||||
1756197951 tb.f
|
||||
1756197943 rtl.f
|
||||
1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
|
||||
4
|
||||
1539402341 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so
|
||||
1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
|
||||
1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
|
||||
1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
|
||||
1756197957 simv.daidir
|
||||
-1 partitionlib
|
||||
BIN
sim/simv.daidir/_16331_archive_1.so
Executable file
BIN
sim/simv.daidir/_16331_archive_1.so
Executable file
Binary file not shown.
BIN
sim/simv.daidir/binmap.sdb
Normal file
BIN
sim/simv.daidir/binmap.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/build_db
Executable file
4
sim/simv.daidir/build_db
Executable file
@@ -0,0 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1
|
||||
7
sim/simv.daidir/cc/cc_bcode.db
Normal file
7
sim/simv.daidir/cc/cc_bcode.db
Normal file
@@ -0,0 +1,7 @@
|
||||
sid tb_data_cache
|
||||
bcid 0 0 WIDTH,4 OPT_CONST,0 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU CALL_ARG_VAL,4,0 NOT OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,1 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,26 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,2 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,16 CALL_ARG_VAL,8,0 CALL_ARG_VAL,9,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,3 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,3 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 NOT AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,4 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,5 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,13,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 OPT_CONST,5 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 1 1 WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OR OR OPT_CONST,1 EQU WIDTH,2 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,4 PAD OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 NOT AND AND RET
|
||||
bcid 3 3 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,11 SHIFT_R XOR RET
|
||||
bcid 4 4 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,1 M_EQU AND RET
|
||||
bcid 5 5 WIDTH,12 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
||||
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
@@ -0,0 +1,2 @@
|
||||
Dummy_file
|
||||
Missing line/file info
|
||||
20
sim/simv.daidir/cgname.json
Normal file
20
sim/simv.daidir/cgname.json
Normal file
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
3
|
||||
],
|
||||
"tb_data_cache": [
|
||||
"tb_data_cache",
|
||||
"EULYA",
|
||||
"module",
|
||||
2
|
||||
]
|
||||
}
|
||||
0
sim/simv.daidir/covg_defs
Normal file
0
sim/simv.daidir/covg_defs
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
@@ -0,0 +1,4 @@
|
||||
O-2018.09-1_Full64
|
||||
Build Date = Oct 12 2018 20:38:10
|
||||
RedHat
|
||||
Compile Location: /home/ICer/ic_prjs/IPA/sim
|
||||
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
Binary file not shown.
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
@@ -0,0 +1,9 @@
|
||||
#!/bin/sh -h
|
||||
PYTHONHOME=/home/synopsys/vcs-mx/O-2018.09-1/etc/search/pyh
|
||||
export PYTHONHOME
|
||||
PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_s87tOh.xml.gz" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh -h
|
||||
|
||||
FILE_PATH="/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch"
|
||||
lockfile="${FILE_PATH}"/lock
|
||||
|
||||
FSearch_lock_release() {
|
||||
echo "" > /dev/null
|
||||
}
|
||||
create_fsearch_db_ctrl() {
|
||||
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
|
||||
if [ -s "${FILE_PATH}"/fsearch.log ]; then
|
||||
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
|
||||
else
|
||||
cat "${FILE_PATH}"/fsearch.stat
|
||||
fi
|
||||
return
|
||||
fi
|
||||
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
|
||||
MY_PID=`echo $!`
|
||||
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
|
||||
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
|
||||
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
|
||||
return
|
||||
}
|
||||
|
||||
dir_name=`/bin/dirname "$0"`
|
||||
if [ "${dir_name}" = "." ]; then
|
||||
cd $dir_name
|
||||
dir_name=`/bin/pwd`
|
||||
fi
|
||||
if [ -d "$dir_name"/../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../..
|
||||
fi
|
||||
|
||||
if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
||||
trap FSearch_lock_release EXIT
|
||||
(
|
||||
flock 193
|
||||
create_fsearch_db_ctrl "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
exit 193
|
||||
) 193> "$lockfile"
|
||||
rstat=$?
|
||||
if [ "${rstat}"x != "193x" ]; then
|
||||
exit $rstat
|
||||
fi
|
||||
else
|
||||
"/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
elif [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
Binary file not shown.
8
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
8
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
@@ -0,0 +1,8 @@
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/async_fifo.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/axi_write_ctrl.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/data_assemble.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/data_cache.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/histogram_ctrl.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/rst_sync.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/sync_fifo.v
|
||||
/home/ICer/ic_prjs/IPA/tb/data_cache/tb_data_cache.v
|
||||
1
sim/simv.daidir/debug_dump/topmodules
Normal file
1
sim/simv.daidir/debug_dump/topmodules
Normal file
@@ -0,0 +1 @@
|
||||
<02>E<EFBFBD>d
|
||||
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/eblklvl.db
Normal file
BIN
sim/simv.daidir/eblklvl.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
Binary file not shown.
78
sim/simv.daidir/external_functions
Normal file
78
sim/simv.daidir/external_functions
Normal file
@@ -0,0 +1,78 @@
|
||||
pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC
|
||||
pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC
|
||||
pli $dumpportson DumpPortsOnCALL - DumpPortsMISC
|
||||
pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC
|
||||
pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC
|
||||
pli $simlearn simLearnCall simLearnCheck simLearnMisc
|
||||
pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC
|
||||
pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC
|
||||
pli $countdrivers CountDriversCALL - -
|
||||
pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC
|
||||
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcc.sdb
Normal file
BIN
sim/simv.daidir/pcc.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/prof.sdb
Normal file
BIN
sim/simv.daidir/prof.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.dat
Normal file
BIN
sim/simv.daidir/rmapats.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.so
Executable file
BIN
sim/simv.daidir/rmapats.so
Executable file
Binary file not shown.
1
sim/simv.daidir/saifNetInfo.db
Normal file
1
sim/simv.daidir/saifNetInfo.db
Normal file
@@ -0,0 +1 @@
|
||||
0
|
||||
16
sim/simv.daidir/simv.kdb
Normal file
16
sim/simv.daidir/simv.kdb
Normal file
@@ -0,0 +1,16 @@
|
||||
rc file Version 1.0
|
||||
|
||||
[Design]
|
||||
COMPILE_PATH=/home/ICer/ic_prjs/IPA/sim
|
||||
SystemC=FALSE
|
||||
UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=tb_data_cache
|
||||
OPTION=-ssv -ssy
|
||||
ELAB_OPTION=-ssv -ssy
|
||||
|
||||
[Value]
|
||||
WREALX=ffff534e50535f58
|
||||
WREALZ=ffff534e50535f5a
|
||||
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/tt.sdb
Normal file
BIN
sim/simv.daidir/tt.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/vcs_rebuild
Executable file
4
sim/simv.daidir/vcs_rebuild
Executable file
@@ -0,0 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1
|
||||
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
@@ -0,0 +1,673 @@
|
||||
hsDirType 1
|
||||
fHsimDesignHasDebugNodes 61
|
||||
fNSParam 1024
|
||||
fLargeSizeSdfTest 0
|
||||
fHsimDelayGateMbme 0
|
||||
fNoMergeDelays 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimCertRaptMode 0
|
||||
fSharedMasterElab 0
|
||||
hsimLevelizeDone 1
|
||||
fHsimCompressDiag 1
|
||||
fHsimPowerOpt 0
|
||||
fLoopReportElab 0
|
||||
fHsimRtl 0
|
||||
fHsimCbkOptVec 1
|
||||
fHsimDynamicCcnHeur 1
|
||||
fHsimPvcs 0
|
||||
fHsimPvcsCcn 0
|
||||
fHsimOldLdr 0
|
||||
fHsimSingleDB 1
|
||||
uVfsGcLimit 50
|
||||
fHsimCompatSched 0
|
||||
fHsimCompatOrder 0
|
||||
fHsimTransUsingdoMpd32 0
|
||||
fHsimDynamicElabForGates 1
|
||||
fHsimDynamicElabForVectors 0
|
||||
fHsimDynamicElabForVectorsAlways 0
|
||||
fHsimDynamicElabForVectorsMinputs 0
|
||||
fHsimDeferForceSelTillReElab 0
|
||||
fHsimModByModElab 1
|
||||
fSvNettRealResType 0
|
||||
fHsimExprID 1
|
||||
fHsimSequdpon 0
|
||||
fHsimDatapinOpt 0
|
||||
fHsimExprPrune 0
|
||||
fHsimMimoGate 0
|
||||
fHsimNewChangeCheckFrankch 1
|
||||
fHsimNoSched0Front 0
|
||||
fHsimNoSched0FrontForMd 1
|
||||
fHsimScalReg 0
|
||||
fHsimNtbVl 0
|
||||
fHsimICTimeStamp 0
|
||||
fHsimICDiag 0
|
||||
fHsimNewCSDF 1
|
||||
vcselabIncrMode 2
|
||||
fHsimMPPackDelay 0
|
||||
fHsimMultDriver 0
|
||||
fHsimPart 0
|
||||
fHsimPrlComp 0
|
||||
fHsimPartTest 0
|
||||
fHsimTestChangeCheck 0
|
||||
fHsimTestFlatNodeOrder 0
|
||||
fHsimTestNState 0
|
||||
fHsimPartDebug 0
|
||||
fHsimPartFlags 0
|
||||
fHsimOdeSched0 0
|
||||
fHsimNewRootSig 1
|
||||
fHsimDisableRootSigModeOpt 0
|
||||
fHsimTestRootSigModeOpt 0
|
||||
fHsimIncrWriteOnce 0
|
||||
fHsimUnifInterfaceFlow 1
|
||||
fHsimUnifInterfaceFlowDiag 0
|
||||
fHsimUnifInterfaceFlowXmrDiag 0
|
||||
fHsimUnifInterfaceMultiDrvChk 1
|
||||
fHsimXVirForGenerateScope 0
|
||||
fHsimCongruencyIntTestI 0
|
||||
fHsimCongruencySVA 0
|
||||
fHsimCongruencySVADbg 0
|
||||
fHsimCongruencyLatchEdgeFix 0
|
||||
fHsimCongruencyFlopEdgeFix 0
|
||||
fHsimCongruencyXprop 0
|
||||
fHsimCongruencyXpropFix 0
|
||||
fHsimCongruencyXpropDbsEdge 0
|
||||
fHsimCongruencyResetRecoveryDbs 0
|
||||
fHsimCongruencyClockControlDiag 0
|
||||
fHsimCongruencySampleUpdate 0
|
||||
fHsimCongruencyFFDbsFix 0
|
||||
fHsimCongruency 0
|
||||
fHsimCongruencySlave 0
|
||||
fHsimCongruencyCombinedLoads 0
|
||||
fHsimCongruencyFGP 0
|
||||
fHsimDeraceClockDataUdp 0
|
||||
fHsimDeraceClockDataLERUpdate 0
|
||||
fHsimCongruencyPC 0
|
||||
fHsimCongruencyPCInl 0
|
||||
fHsimCongruencyPCDbg 0
|
||||
fHsimCongruencyPCNoReuse 0
|
||||
fHsimCongruencyDumpHier 0
|
||||
fHsimCongruencyResolution 0
|
||||
fHsimCongruencyEveBus 0
|
||||
fHsimHcExpr 0
|
||||
fHsCgOptModOpt 0
|
||||
fHsCgOptSlowProp 0
|
||||
fHsimCcnOpt 1
|
||||
fHsimCcnOpt2 1
|
||||
fHsimCcnOpt3 0
|
||||
fHsimSmdMap 0
|
||||
fHsimSmdDiag 0
|
||||
fHsimSmdSimProf 0
|
||||
fHsimSgdDiag 0
|
||||
fHsimRtDiagLite 0
|
||||
fHsimRtDiagLiteCevent 100
|
||||
fHsimRtDiag 0
|
||||
fHsimSkRtDiag 0
|
||||
fHsimDDBSRtdiag 0
|
||||
fHsimDbg 0
|
||||
fHsimCompWithGates 0
|
||||
fHsimMdbDebugOpt 0
|
||||
fHsimMdbDebugOptP1 0
|
||||
fHsimMdbDebugOptP2 0
|
||||
fHsimMdbPruneOpt 1
|
||||
fHsimMdbMemOpt 0
|
||||
hsimRandValue 0
|
||||
fHsimSimMemProfile 0
|
||||
fHsimSimTimeProfile 0
|
||||
fHsimElabMemProfile 0
|
||||
fHsimElabTimeProfile 0
|
||||
fHsimElabMemNodesProfile 0
|
||||
fHsimElabMemAllNodesProfile 0
|
||||
fHsimDisableVpdGatesProfile 0
|
||||
fHsimFileProfile 0
|
||||
fHsimCountProfile 0
|
||||
fHsimXmrDefault 1
|
||||
fHsimFuseWireAndReg 0
|
||||
fHsimFuseSelfDrvLogic 0
|
||||
fHsimFuseProcess 0
|
||||
fHsimAllXmrs 1
|
||||
fHsimMvsimDb 0
|
||||
fHsimTaskFuncXmrs 0
|
||||
fHsimTaskFuncXmrsDbg 0
|
||||
fHsimAllTaskFuncXmrs 0
|
||||
fHsimPageArray 16383
|
||||
fHsimPageControls 16383
|
||||
hsDfsNodePageElems 0
|
||||
hsNodePageElems 0
|
||||
hsFlatNodePageElems 0
|
||||
hsGateMapPageElems 0
|
||||
hsGateOffsetPageElems 0
|
||||
hsGateInputOffsetPageElems 0
|
||||
hsDbsOffsetPageElems 0
|
||||
hsMinPulseWidthPageElems 0
|
||||
hsNodeUpPatternPageElems 0
|
||||
hsNodeDownPatternPageElems 0
|
||||
hsNodeUpOffsetPageElems 0
|
||||
hsNodeEblkOffsetPageElems 0
|
||||
hsNodeDownOffsetPageElems 0
|
||||
hsNodeUpdateOffsetPageElems 0
|
||||
hsSdfOffsetPageElems 0
|
||||
fHsimPageAllLevelData 0
|
||||
fHsimAggrCg 0
|
||||
fHsimViWire 1
|
||||
fHsimPcCbOpt 1
|
||||
fHsimAmsTunneling 0
|
||||
fHsimAmsTunnelingDiag 0
|
||||
fHsimScUpwardXmrNoSplit 1
|
||||
fHsimOrigNdbViewOnly 0
|
||||
fHsimVcsInterface 1
|
||||
fHsimVcsInterfaceAlias 1
|
||||
fHsimSVTypesIntf 1
|
||||
fUnifiedAssertCtrlDiag 0
|
||||
fHsimEnable2StateScal 0
|
||||
fHsimDisable2StateScalIbn 0
|
||||
fHsimVcsInterfaceAliasDbg 0
|
||||
fHsimVcsInterfaceDbg 0
|
||||
fHsimVcsVirtIntfDbg 0
|
||||
fHsimVcsAllIntfVarMem 0
|
||||
fHsimCheckVIDynLoadOffsets 0
|
||||
fHsimModInline 1
|
||||
fHsimModInlineDbg 0
|
||||
fHsimPCDrvLoadDbg 0
|
||||
fHsimDrvChk 1
|
||||
fHsimRtlProcessingNeeded 0
|
||||
fHsimGrpByGrpElab 0
|
||||
fHsimGrpByGrpElabMaster 0
|
||||
fHsimNoParentSplitPC 0
|
||||
fHsimNusymMode 0
|
||||
fHsimOneIntfPart 0
|
||||
fHsimCompressInSingleDb 2
|
||||
fHsimCompressFlatDb 0
|
||||
fHsimNoTime0Sched 1
|
||||
fHsimMdbVectorizeInstances 0
|
||||
fHsimMdbSplitGates 0
|
||||
fHsimDeleteInstances 0
|
||||
fHsimUserDeleteInstances 0
|
||||
fHsimDeleteGdb 0
|
||||
fHsimDeleteInstancesMdb 0
|
||||
fHsimShortInstMap 0
|
||||
fHsimMdbVectorizationDump 0
|
||||
fHsimScanVectorize 0
|
||||
fHsimParallelScanVectorize 0
|
||||
noInstsInVectorization 0
|
||||
cHsimNonReplicatedInstances 0
|
||||
fHsimScanRaptor 0
|
||||
fHsimConfigFileCount 0
|
||||
fHsimVectorConstProp 0
|
||||
fHsimPromoteParam 0
|
||||
fHsimNoVecInRaptor 0
|
||||
fRaptorDumpVal 0
|
||||
fRaptorVecNodes 0
|
||||
fRaptorVecNodes2 0
|
||||
fRaptorNonVecNodes 0
|
||||
fRaptorBdrNodes 0
|
||||
fRaptorVecGates 0
|
||||
fRaptorNonVecGates 0
|
||||
fRaptorTotalNodesBeforeVect 0
|
||||
fRaptorTotalGatesBeforeVect 0
|
||||
fHsimCountRaptorBits 0
|
||||
fHsimNewEvcd 1
|
||||
fHsimNewEvcdMX 0
|
||||
fHsimNewEvcdVecRoot 1
|
||||
fHsimNewEvcdForce 1
|
||||
fHsimNewEvcdTest 0
|
||||
fHsimNewEvcdObnDrv 1
|
||||
fHsimNewEvcdW 1
|
||||
fHsimNewEvcdWTest 0
|
||||
fHsimEvcdDbgFlags 0
|
||||
fHsimDumpOffsetData 1
|
||||
fFlopGlitchDetect 0
|
||||
fHsimClkGlitch 0
|
||||
fHsimGlitchDumpOnce 0
|
||||
fHsimDynamicElab 1
|
||||
fHsimCgVectors2Debug 0
|
||||
fHsimOdeDynElab 0
|
||||
fHsimOdeDynElabDiag 0
|
||||
fHsimOdeSeqUdp 0
|
||||
fHsimOdeSeqUdpXEdge 0
|
||||
fHsimOdeSeqUdpDbg 0
|
||||
fHsimOdeRmvSched0 0
|
||||
fHsimAllLevelSame 0
|
||||
fHsimRtlDbsList 0
|
||||
fHsimPePort 0
|
||||
fHsimPeXmr 0
|
||||
fHsimPePortDiag 0
|
||||
fHsimUdpDbs 0
|
||||
fHsimRemoveDbgCaps 0
|
||||
fFsdbGateOnepassTraverse 0
|
||||
fHsimAllowVecGateInVpd 1
|
||||
fHsimAllowAllVecGateInVpd 0
|
||||
fHsimAllowUdpInVpd 1
|
||||
fHsimAllowAlwaysCombInVpd 1
|
||||
fHsimAllowAlwaysCombCmpDvcSimv 0
|
||||
fHsimAllowAlwaysCombDbg 0
|
||||
fHsimMakeAllP2SPrimary 0
|
||||
fHsimMakeAllSeqPrimary 0
|
||||
fHsimNoCcnDump 0
|
||||
fHsimFsdbProfDiag 0
|
||||
fVpdSeqGate 0
|
||||
fVpdHsIntVecGate 0
|
||||
fVpdHsCmplxVecGate 0
|
||||
fVpdHsVecGateDiags 0
|
||||
fSeqGateCodePatch 0
|
||||
fVpdLongFaninOpt 0
|
||||
fVpdSeqLongFaninOpt 0
|
||||
fVpdNoLoopDetect 0
|
||||
fVpdNoSeqLoopDetect 0
|
||||
fVpdOptAllowConstDriver 0
|
||||
fVpdAllowCellReconstruction 0
|
||||
fVpdRtlForSharedLib 0
|
||||
fHsimVpdOptGate 1
|
||||
fHsimVpdOptDelay 0
|
||||
fHsimVpdOptMPDelay 0
|
||||
fHsimCbkOptDiag 0
|
||||
fHsimSK 0
|
||||
fHsimSharedKernel 1
|
||||
fHsimOnepass 0
|
||||
fHsimStitchNew 0
|
||||
fHsimParallelLevelize 0
|
||||
fHsimParallelLevelizeDbg 0
|
||||
fHsimSeqUdpDbsByteArray 0
|
||||
fHsimCoLocate 0
|
||||
fHsimSeqUdpEblkOpt 0
|
||||
fHsimSeqUdpEblkOptDiag 0
|
||||
fHsimGateInputAndDbsOffsetsOpt 1
|
||||
fHsimUdpDynElab 0
|
||||
fHsimCompressData 4
|
||||
fHsimIgnoreZForDfuse 1
|
||||
fHsimIgnoreDifferentCaps 0
|
||||
fHandleGlitchQC 1
|
||||
fGlitchDetectForAllRtlLoads 0
|
||||
fHsimFuseConstDriversOpt 1
|
||||
fHsimIgnoreReElab 0
|
||||
fHsimFuseMultiDrivers 0
|
||||
fHsimNoSched0Reg 0
|
||||
fHsimAmsFusionEnabled 0
|
||||
fHsimRtlDbs 0
|
||||
fHsimWakeupId 0
|
||||
fHsimPassiveIbn 0
|
||||
fHsimBcOpt 1
|
||||
fHsimCertitude 0
|
||||
fHsimCertRapAutoTest 0
|
||||
fHsimRaceDetect 0
|
||||
fCheckTcCond 0
|
||||
fHsimScanOptRelaxDbg 0
|
||||
fHsimScanOptRelaxDbgDynamic 0
|
||||
fHsimScanOptRelaxDbgDynamicPli 0
|
||||
fHsimScanOptRelaxDbgDiag 0
|
||||
fHsimScanOptRelaxDbgDiagHi 0
|
||||
fHsimScanOptNoErrorOnPliAccess 0
|
||||
fHsimScanOptTiming 0
|
||||
fRelaxIbnSchedCheck 0
|
||||
fHsimScanOptNoDumpCombo 0
|
||||
fHsimScanOptPrintSwitchState 0
|
||||
fHsimScanOptSelectiveSwitchOn 0
|
||||
fHsimScanOptSingleSEPliOpt 1
|
||||
fHsimScanOptDesignHasDebugAccessOnly 0
|
||||
fHsimScanOptPrintPcode 0
|
||||
fHsimScanDbgPerf 0
|
||||
fHsimNoStitchMap 0
|
||||
fHsimUnifiedModName 0
|
||||
fHsimCbkMemOptDebug 0
|
||||
fHsimMasterModuleOnly 0
|
||||
fHsimMdbOptimizeSelects 0
|
||||
fHsimMdbScalarizePorts 0
|
||||
fHsimMdbOptimizeSelectsHeuristic 1
|
||||
fHsimMdb1006Partition 0
|
||||
fHsimVectorPgate 0
|
||||
fHsimNoHs 0
|
||||
fHsimXmrPartition 0
|
||||
fHsimNewPartition 0
|
||||
fHsimElabPart 0
|
||||
fHsimNewPartTHold 0
|
||||
fHsimParitionCellInstNum 1000
|
||||
fHsimParitionCellNodeNum 1000
|
||||
fHsimParitionCellXMRNum 1000
|
||||
fHsimNewPartCutSingleInstLimit 268435455
|
||||
fHsimElabModDistNum 0
|
||||
fHsimNewPartAutoUpperLimit 0
|
||||
fHsimPCPortPartition 0
|
||||
fHsimPortPartition 0
|
||||
fHsimDumpMdb 0
|
||||
fHsimElabDiag 0
|
||||
fHsimSimpCollect 0
|
||||
fHsimPcodeDiag 0
|
||||
fHsimFastelab 0
|
||||
fHsimMacroOpt 0
|
||||
fHsimSkipOpt 0
|
||||
fHsimSkipOptFanoutlimit 0
|
||||
fHsimSkipOptRootlimit 0
|
||||
fHsimFuseDelayChains 0
|
||||
fFusempchainsFanoutlimit 0
|
||||
fFusempchainsDiagCount 0
|
||||
fHsimCgVectorGates 0
|
||||
fHsimCgVectorGates1 0
|
||||
fHsimCgVectorGates2 0
|
||||
fHsimCgVectorGatesNoReElab 0
|
||||
fHsimCgScalarGates 0
|
||||
fHsimCgScalarGatesExpr 0
|
||||
fHsimCgScalarGatesLut 0
|
||||
fHsimCgRtl 1
|
||||
fHsimCgRtlFilter 0
|
||||
fHsimCgRtlDebug 0
|
||||
fHsimCgRtlSize 15
|
||||
fHsimNewCgRt 0
|
||||
fHsimNewCgMPRt 0
|
||||
fHsimNewCgMPRetain 0
|
||||
fHsimCgRtlInfra 1
|
||||
fHsimGlueOpt 0
|
||||
fHsimPGatePatchOpt 0
|
||||
fHsimCgNoPic 0
|
||||
fHsimElabModCg 0
|
||||
fPossibleNullChecks 0
|
||||
fHsimProcessNoSplit 1
|
||||
fHsimMdbOptInSchedDelta 0
|
||||
fScaleTimeValue 0
|
||||
fDebugTimeScale 0
|
||||
fPartCompSDF 0
|
||||
fHsimNbaGate 1
|
||||
fDumpSDFBasedMod 1
|
||||
fOptimisticNtcSolver 0
|
||||
fHsimAllMtm 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimSdgOptEnable 0
|
||||
fHsimSVTypesRefPorts 0
|
||||
fHsimGrpByGrpElabIncr 0
|
||||
fHsimMarkRefereeInVcsElab 0
|
||||
fHsimStreamOpFix 1
|
||||
fHsimInterface 0
|
||||
fHsimMxWrapOpt 0
|
||||
fHsimMxTopBdryOpt 0
|
||||
fHsimClasses 0
|
||||
fHsimAggressiveDce 0
|
||||
fHsimDceDebug 1
|
||||
fHsimDceDebugUseHeuristics 1
|
||||
fHsimMdbNewDebugOpt 0
|
||||
fHsimMdbNewDebugOptExitOnError 1
|
||||
fHsimNewDebugOptMemDiag 0
|
||||
hsGlobalVerboseLevel 0
|
||||
fHsimMdbVectorConstProp 1
|
||||
fHsimEnableSeqUdpWrite 1
|
||||
fHsimDumpMDBOnlyForSeqUdp 0
|
||||
fHsimInitRegRandom 0
|
||||
fHsimInitRegRandomVcs 1
|
||||
fEnableNewFinalStrHash 0
|
||||
fEnableNewAssert 1
|
||||
fRunDbgDmma 0
|
||||
fAssrtCtrlSigChk 1
|
||||
fCheckSigValidity 0
|
||||
fUniqPriToAstRewrite 0
|
||||
fUniqPriToAstCtrl 0
|
||||
fAssertcontrolUniqPriNewImpl 0
|
||||
fRTLoopDectEna 0
|
||||
fCmplLoopDectEna 0
|
||||
fHsimMopFlow 1
|
||||
fUCaseLabelCtrl 0
|
||||
fUniSolRtSvaEna 1
|
||||
fUniSolSvaEna 1
|
||||
fXpropRtCtrlCallerOnly 0
|
||||
fHsimRaptorPart 0
|
||||
fHsimEnableDbsMemOpt 1
|
||||
fHsimDebugDbsMemOpt 0
|
||||
fHsimRenPart 0
|
||||
fHsimShortElabInsts 0
|
||||
fHsimXmrAllWires 0
|
||||
fHsimXmrDiag 0
|
||||
fHsimXmrPort 0
|
||||
fHsimFalcon 1
|
||||
fHsimGenForProfile 0
|
||||
fCompressSDF 0
|
||||
fDlpSvtbExclElab 0
|
||||
fHsimGates1209 0
|
||||
fHsimCgRtlNoShareSmd 0
|
||||
fHsimGenForErSum 0
|
||||
fVpdOpt 1
|
||||
fHsimMdbCell 0
|
||||
fHsimCellDebug 0
|
||||
fHsimNoPeekInMdbCell 0
|
||||
igetOpcodeSmdPtrLayoutId -1
|
||||
igetFieldSmdPtr -1
|
||||
fDebugDump 1
|
||||
fHsimOrigNodeNames 0
|
||||
fHsimCgVectors2VOnly 0
|
||||
fHsimMdbDeltaGate 0
|
||||
fHsimMdbVecDeltaGate 1
|
||||
fHsimVpdOptVfsDB 1
|
||||
fHsimMdbPruneVpdGates 1
|
||||
fHsimPcPe 0
|
||||
fHsimVpdGateOnlyFlag 1
|
||||
fHsimMxConnFrc 0
|
||||
fHsimNewForceCbkVec 0
|
||||
fHsimNewForceCbkVecDiag 0
|
||||
fHsimMdbReplaceVpdHighConn 1
|
||||
fHsimVpdOptSVTypes 1
|
||||
fHsHasPeUpXmr 0
|
||||
fHsimCompactVpdFn 1
|
||||
fHsimPIP 0
|
||||
fHsimRTLoopDectOrgName 0
|
||||
fHsimVpdOptPC 0
|
||||
fHsimFusePeXmrFo 0
|
||||
fHsimXmrSched 0
|
||||
fHsimNoMdg 0
|
||||
fHsimVectorGates 0
|
||||
fHsimRtlLite 0
|
||||
fHsimMdbcgLut 0
|
||||
fHsimMdbcgSelective 0
|
||||
fHsimVcselabGates 0
|
||||
fHsimMdbcgLevelize 0
|
||||
fHsimParGateEvalMode 0
|
||||
fHsimDFuseVectors 0
|
||||
fHsimDFuseZero 0
|
||||
fHsimDFuseOpt 1
|
||||
fHsimPruneOpt 0
|
||||
fHsimSeqUdpPruneWithConstInputs 0
|
||||
fHsimSafeDFuse 0
|
||||
fHsimVpdOptExpVec 0
|
||||
fHsimVpdOptSelGate 1
|
||||
fHsimVpdOptSkipFuncPorts 0
|
||||
fHsimVpdOptAlways 1
|
||||
fHsimVpdOptMdbCell 0
|
||||
fHsimVpdOptPartialMdb 1
|
||||
fHsimVpdOptPartitionGate 1
|
||||
fHsimVpdOptXmr 1
|
||||
fHsimVpdHilRtl 0
|
||||
fHsimSWave 0
|
||||
fHsimNoSched0InCell 1
|
||||
fHsimPartialMdb 0
|
||||
hsimPdbLargeOffsetThreshold 1048576
|
||||
fHsimFlatCell 0
|
||||
fHsimFlatCellLimit 0
|
||||
fHsimRegBank 0
|
||||
fHsimHmetisMaxPartSize 0
|
||||
fHsimHmetisGateWt 0
|
||||
fHsimHmetisUbFactor 0
|
||||
fHsimHmetis 0
|
||||
fHsimHmetisDiag 0
|
||||
fHsimRenumGatesForMdbCell 0
|
||||
fHsimHmetisMinPart 0
|
||||
fHsim2stCell 0
|
||||
fHsim2stCellMinSize 0
|
||||
fHsimMdbcgDebug 0
|
||||
fHsimMdbcgDebugLite 0
|
||||
fHsimMdbcgDistrib 0
|
||||
fHsimMdbcgSepmem 1
|
||||
fHsimMdbcgObjDiag 0
|
||||
fHsimMdbcg2stDiag 0
|
||||
fHsimMdbcgRttrace 0
|
||||
fHsimMdbVectorGateGroup 1
|
||||
fHsimMdbProcDfuse 1
|
||||
fHsimMdbHilPrune 0
|
||||
fHsCgOpt 1
|
||||
fHsCgOptUdp 1
|
||||
fHsCgOptRtl 1
|
||||
fHsCgOptDiag 0
|
||||
fHsCgOptAggr 0
|
||||
fHsCgOptNoZCheck 0
|
||||
fHsCgOptEnableZSupport 0
|
||||
fHsCgOpt4StateInfra 0
|
||||
fHsCgOptUdpChkDataForWakeup 1
|
||||
fHsCgOptXprop 0
|
||||
fHsimMdbcgDiag 0
|
||||
fHsCgMaxInputs 6
|
||||
fHsCgOptFwdPass 1
|
||||
fHsimHpnodes 0
|
||||
fLightDump 0
|
||||
fHDLCosim 0
|
||||
fHDLCosimDebug 0
|
||||
fHDLCosimTimeCoupled 0
|
||||
fHDLCosimTimeCoupledPorts 0
|
||||
HDLCosimMaxDataPerDpi 1
|
||||
HDLCosimMaxCallsPerDpi 2147483647
|
||||
fHDLCosimCompileDUT 0
|
||||
fHDLCosimCustomCompile 0
|
||||
fHDLCosimBoundaryAnalysis 0
|
||||
fVpdBeforeScan 1
|
||||
fHsCgOptMiSched0 0
|
||||
fgcAddSched0 0
|
||||
fParamClassOptRtDiag 0
|
||||
fHsRegress 0
|
||||
fHsBenchmark 0
|
||||
fHsimCgScalarVerilogForce 1
|
||||
fVcsElabToRoot 1
|
||||
fHilIbnObnCallByName 0
|
||||
fHsimMdbcgCellPartition 0
|
||||
fHsimCompressVpdSig 0
|
||||
fHsimLowPowerOpt 0
|
||||
fHsimUdpOpt 1
|
||||
fHsVecOneld 0
|
||||
fNativeVpdDebug 0
|
||||
fHsimVcsGenTLS 1
|
||||
fAssertSuccDebugLevelDump 0
|
||||
fHsimMinputsChangeCheck 0
|
||||
fHsimClkLayout 0
|
||||
fHsimIslandLayout 0
|
||||
fHsimConfigSched0 0
|
||||
fHsimSelectFuseAfterDfuse 0
|
||||
fHsimFoldedCell 0
|
||||
fHsimSWaveEmul 0
|
||||
fHsimSWaveDumpMDB 0
|
||||
fHsimSWaveDumpFlatData 0
|
||||
fHsimRenumberAlias 0
|
||||
fHsimAliasRenumbered 0
|
||||
fHilCgMode 115
|
||||
fHsimUnionOpt 0
|
||||
fHsimFuseSGDBoundaryNodes 0
|
||||
fHsimRemoveCapsVec 0
|
||||
fHsimCertRaptScal 0
|
||||
fHsimCertRaptMdbClock 0
|
||||
fHsCgOptMux 0
|
||||
fHsCgOptFrc 0
|
||||
fHsCgOpt30 0
|
||||
fHsLpNoCapsOpt 0
|
||||
fHsCgOpt4State 1
|
||||
fSkipStrChangeOnDelay 1
|
||||
fHsimTcheckOpt 0
|
||||
fHsCgOptMuxMClk 0
|
||||
fHsCgOptMuxFrc 0
|
||||
fHsCgOptNoPcb 0
|
||||
fHsCgOptMin1 0
|
||||
fHsCgOptUdpChk 0
|
||||
fHsChkXForSlowSigProp 1
|
||||
fHsimVcsParallelDbg 0
|
||||
fHsimVcsParallelStrategy 0
|
||||
fHsimVcsParallelOpt 0
|
||||
fHsimVcsParallelSubLevel 4
|
||||
fHsimParallelEblk 0
|
||||
fHsimByteCodeParts 1
|
||||
fFgpNovlInComp 0
|
||||
fFutEventPRL 0
|
||||
fFgpNbaDelay 0
|
||||
fHsimDbsFlagsByteArray 0
|
||||
fHsimDbsFlagsByteArrayTC 0
|
||||
fHsimDbsFlagsThreadArray 0
|
||||
fHsimGateEdgeEventSched 0
|
||||
fHsimEgschedDynelab 0
|
||||
fHsimUdpClkDynelab 0
|
||||
fUdpLayoutOnClk 0
|
||||
fDbsPreCheck 0
|
||||
fHsimSched0Analysis 0
|
||||
fHsimMultiDriverSched0 0
|
||||
fHsimLargeIbnSched 0
|
||||
fFgpHierarchical 0
|
||||
fFgpHierAllElabModAsRoot 0
|
||||
fFgpHierPCElabModAsRoot 0
|
||||
fFgpAdjustDataLevelOfLatch 1
|
||||
fHsimUdpXedgeEval 0
|
||||
fFgpRaceCheck 0
|
||||
fFgpUnifyClk 0
|
||||
fFgpSmallClkTree 0
|
||||
fFgpSmallRtlClkTree 4
|
||||
fFgpNoRtlUnlink 0
|
||||
fFgpNoRtlAuxLevel 0
|
||||
fFgpNumPartitions 8
|
||||
fFgpMultiSocketCompile 0
|
||||
fFgpDataDepOn 0
|
||||
fFgpDDIgnore 0
|
||||
fFgpTbCbOn 0
|
||||
fFgpTbEvOn 1
|
||||
fFgpTbNoVSA 0
|
||||
fFgpTbEvXmr 0
|
||||
fFgpDisabledLevel 512
|
||||
fFgpSched0User 0
|
||||
fFgpNoSdDelayedNbas 1
|
||||
fFgpTimingFlags 0
|
||||
fFgpSched0Level 0
|
||||
fHsimFgpMultiClock 0
|
||||
fFgpScanOptFix 0
|
||||
fFgpSched0UdpData 0
|
||||
fFgpDepositDiag 0
|
||||
fFgpEvtDiag.diagOn 0
|
||||
fFgpEvtDiag.printAllNodes 0
|
||||
fFgpMangleDiagLog 0
|
||||
fFgpMultiExclDiag 0
|
||||
fFgpSingleExclReason 0
|
||||
fHsDoFaninFanoutSanity 0
|
||||
fHsFgpNonDbsOva 1
|
||||
fFgpParallelTask 1
|
||||
fFgpIbnSched 0
|
||||
fFgpIbnSchedOpt 0
|
||||
fFgpIbnSchedThreshold 0
|
||||
fFgpIbnSchedDyn 0
|
||||
fFgpMpStateByte 0
|
||||
fFgpTcStateByte 0
|
||||
fHsimVirtIntfDynLoadSched 0
|
||||
fFgpNoRtimeFgp 0
|
||||
fHsFgpGlSched0 0
|
||||
fFgpExclReason 0
|
||||
fHsimIslandByIslandElab 0
|
||||
fHsimIslandByIslandFlat 151652416
|
||||
fHsimIslandByIslandFlat1 4
|
||||
fHsimVpdIBIF 0
|
||||
fHsimXmrIBIF 0
|
||||
fHsimReportTime 0
|
||||
fHsimElabJ 0
|
||||
hf_fHsimElabJ 0
|
||||
fHsimElabJOpt 0
|
||||
fHsimSchedMinput 0
|
||||
fHsimSchedSeqPrim 0
|
||||
fHsimSchedSelectFanout 0
|
||||
fHsimSchedSelectFanoutDebug 0
|
||||
fSpecifyInDesign 0
|
||||
fFgpDynamicReadOn 0
|
||||
fHsCgOptAllUc 0
|
||||
fHsimXmrRepl 0
|
||||
fZoix 0
|
||||
fHsimDfuseNewOpt 0
|
||||
fHsimBfuseNewOpt 0
|
||||
fFgpXmrSched 0
|
||||
fHsimClearClkCaps 0
|
||||
fHsimDiagClkConfig 0
|
||||
fHsimDiagClkConfigDebug 0
|
||||
fHsimDiagClkConfigDumpAll 0
|
||||
fHsDiagClkConfigPara 0
|
||||
fHsimDiagClkConfigAn 0
|
||||
fHsimCanDumpClkConfig 0
|
||||
fFgpInitRout 0
|
||||
fFgpIgnoreExclSD 0
|
||||
fHsCgOptNoClockFusing 0
|
||||
fHsClkWheelLimit 50000
|
||||
fHsimPCSharedLibSpecified 0
|
||||
fHsFgpSchedCgUcLoads 1
|
||||
fHsCgOptNewSelCheck 1
|
||||
fFgpReportUnsafeFuncs 0
|
||||
fHsCgOptUncPrlThreshold 4
|
||||
fHsimLowPowerRetAnalysisInChild 0
|
||||
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
Binary file not shown.
1190
sim/simv.daidir/vcselab_misc_hsim_elab.db
Normal file
1190
sim/simv.daidir/vcselab_misc_hsim_elab.db
Normal file
File diff suppressed because it is too large
Load Diff
BIN
sim/simv.daidir/vcselab_misc_hsim_fegate.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_fegate.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_hsim_lvl.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_lvl.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_hsim_name.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_name.db
Normal file
Binary file not shown.
3
sim/simv.daidir/vcselab_misc_hsim_uds.db
Normal file
3
sim/simv.daidir/vcselab_misc_hsim_uds.db
Normal file
@@ -0,0 +1,3 @@
|
||||
vcselab_misc_midd.db 749
|
||||
vcselab_misc_mnmn.db 26
|
||||
vcselab_misc_hsim_name.db 217
|
||||
BIN
sim/simv.daidir/vcselab_misc_midd.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_midd.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_mnmn.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_mnmn.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_partition.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_partition.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_vcselabref.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_vcselabref.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_vpdnodenums
Normal file
BIN
sim/simv.daidir/vcselab_misc_vpdnodenums
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user