commit 79dee10db1bd223e8fb83d63691d3d0a9a8e7691 Author: Core_kingdom <2972880695@qq.com> Date: Tue Aug 26 16:53:22 2025 +0800 cache module diff --git a/rtl/data_cache/async_fifo.v b/rtl/data_cache/async_fifo.v new file mode 100644 index 0000000..de5917e --- /dev/null +++ b/rtl/data_cache/async_fifo.v @@ -0,0 +1,85 @@ +module async_fifo #( + parameter DATA_WIDTH = 8, + parameter FIFO_DEPTH = 16 +)( + input wr_clk, + input wr_rst_n, + input wr_en, + input [DATA_WIDTH-1:0] wr_data, + output full, + + input rd_clk, + input rd_rst_n, + input rd_en, + output [DATA_WIDTH-1:0] rd_data, + output empty +); + + reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH -1 : 0]; + reg [$clog2(FIFO_DEPTH) : 0] wr_ptr, rd_ptr; + + integer i; + always@(posedge wr_clk or negedge wr_rst_n) begin + if(!wr_rst_n) begin + wr_ptr <= 'd0; + for(i=0;i>1); + assign rd_ptr_g = rd_ptr ^(rd_ptr >>1); + + reg [$clog2(FIFO_DEPTH):0] wr_ptr_gr , wr_ptr_grr; + reg [$clog2(FIFO_DEPTH):0] rd_ptr_gr , rd_ptr_grr; + + always@(posedge rd_clk or negedge rd_rst_n) begin + if(!rd_rst_n) begin + wr_ptr_gr <= 0; + wr_ptr_grr <=0; + end else begin + wr_ptr_gr <= wr_ptr_g; + wr_ptr_grr <= wr_ptr_gr; + end + end + + always@(posedge wr_clk or negedge wr_rst_n) begin + if(!wr_rst_n) begin + rd_ptr_gr <= 0; + rd_ptr_grr <=0; + end else begin + rd_ptr_gr <= rd_ptr_g; + rd_ptr_grr <= rd_ptr_gr; + end + end + + assign rd_data = mem[rd_ptr[$clog2(FIFO_DEPTH)-1:0]]; + + + assign full = ((wr_ptr_g[$clog2(FIFO_DEPTH)] != + rd_ptr_grr[$clog2(FIFO_DEPTH)]) && (wr_ptr_g[$clog2(FIFO_DEPTH)-1] != + rd_ptr_grr[$clog2(FIFO_DEPTH)]-1) && (wr_ptr_g[$clog2(FIFO_DEPTH)-2:0] == + rd_ptr_grr[$clog2(FIFO_DEPTH)-2 : 0])) ? 1:0; + + assign empty = (rd_ptr_g[$clog2(FIFO_DEPTH) : 0] == + wr_ptr_grr[$clog2(FIFO_DEPTH) :0]) ? 1:0; + +endmodule diff --git a/rtl/data_cache/axi_write_ctrl.v b/rtl/data_cache/axi_write_ctrl.v new file mode 100644 index 0000000..aa2d0ec --- /dev/null +++ b/rtl/data_cache/axi_write_ctrl.v @@ -0,0 +1,196 @@ +module axi_write_ctrl #( + parameter AXI_ID_W = 8, // AXI ID位宽 + parameter AXI_ADDR_W = 32, // AXI地址位宽 + parameter AXI_DATA_W = 256, // AXI数据位宽 + parameter AXI_STRB_W = AXI_DATA_W / 8 // 字节选通位宽(256bit对应32字节) +) ( + input wire clk, // 系统时钟 + input wire rst_n, // 异步复位，低有效 + + // 控制与数据输入 + input wire start_en, // 写事务启动使能 + input wire [AXI_ADDR_W-1:0] sram_base_addr, // SRAM基地址 + input wire [AXI_DATA_W-1:0] fifo_rd_data, // FIFO读数据 + input wire fifo_empty, // FIFO空标志 + output reg fifo_rd_en, // FIFO读使能 + + // AXI AW通道 + output reg [AXI_ID_W-1:0] axi_m_awid, // 写地址ID + output reg [AXI_ADDR_W-1:0] axi_m_awaddr, // 写地址 + output reg [3:0] axi_m_awlen, // 突发长度(0表示1个数据) + output reg [2:0] axi_m_awsize, // 数据宽度(5对应32字节) + output reg [1:0] axi_m_awburst, // 突发类型(0表示增量) + output reg axi_m_awlock, // 锁定信号(0表示普通访问) + output reg [4:0] axi_m_awcache, // 缓存属性(0表示非缓存) + output reg [2:0] axi_m_awprot, // 保护属性(0表示普通) + output reg [4:0] axi_m_awqos, // QoS优先级(0表示默认) + output reg axi_m_awvalid, // 写地址有效 + input wire axi_m_awready, // 写地址就绪 + + // AXI W通道 + output reg [AXI_ID_W-1:0] axi_m_wid, // 写数据ID + output reg [AXI_DATA_W-1:0] axi_m_wdata, // 写数据 + output reg [AXI_STRB_W-1:0] axi_m_wstrb, // 字节选通(全1表示所有字节有效) + output reg axi_m_wlast, // 突发结束标志 + output reg axi_m_wvalid, // 写数据有效 + input wire axi_m_wready, // 写数据就绪 + + // AXI B通道 + input wire [AXI_ID_W-1:0] axi_m_bid, // 写响应ID + input wire [1:0] axi_m_bresp, // 写响应(0表示OKAY) + input wire axi_m_bvalid, // 写响应有效 + output reg axi_m_bready, // 写响应就绪 + + // 状态输出 + output reg axi_busy, // AXI写事务忙 + output reg axi_done // AXI写事务完成 +); + +// 内部信号定义 +reg [AXI_ADDR_W-1:0] curr_addr; // 当前写地址(基于基地址递增) +reg [1:0] axi_state; // AXI状态机状态寄存器 + +// 状态定义 +localparam AXI_IDLE = 2'd0; // 空闲状态 +localparam AXI_AW = 2'd1; // 地址通道传输状态 +localparam AXI_W = 2'd2; // 数据通道传输状态 +localparam AXI_B = 2'd3; // 响应通道传输状态 + +// 1. AXI状态机时序逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_state <= AXI_IDLE; + curr_addr <= {AXI_ADDR_W{1'b0}}; + axi_busy <= 1'b0; + axi_done <= 1'b0; + end else begin + axi_done <= 1'b0; // 单周期有效 + case (axi_state) + AXI_IDLE: begin + axi_busy <= 1'b0; + // 启动条件: 使能信号有效且FIFO非空 + if (start_en && !fifo_empty) begin + axi_state <= AXI_AW; + axi_busy <= 1'b1; + // 初始化当前地址为基地址(首次)或保持上次地址(连续传输) + curr_addr <= (curr_addr == {AXI_ADDR_W{1'b0}}) ? sram_base_addr : curr_addr; + end + end + + AXI_AW: begin + // 地址通道握手完成，进入数据通道 + if (axi_m_awvalid && axi_m_awready) begin + axi_state <= AXI_W; + // 预计算下一次地址(当前地址 + 数据宽度字节数) + curr_addr <= curr_addr + (AXI_DATA_W / 8); + end + end + + AXI_W: begin + // 数据通道握手完成，进入响应通道 + if (axi_m_wvalid && axi_m_wready) begin + axi_state <= AXI_B; + end + end + + AXI_B: begin + // 响应通道握手完成，事务结束 + if (axi_m_bvalid && axi_m_bready) begin + axi_state <= AXI_IDLE; + axi_done <= 1'b1; // 标记事务完成 + end + end + endcase + end +end + +// 2. AXI AW通道信号生成逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_awid <= {AXI_ID_W{1'b0}}; + axi_m_awaddr <= {AXI_ADDR_W{1'b0}}; + axi_m_awlen <= 4'd0; + axi_m_awsize <= 3'd5; // 5对应32字节(2^5 = 32) + axi_m_awburst <= 2'd0; // 0表示INCR(增量)突发 + axi_m_awlock <= 1'b0; + axi_m_awcache <= 5'd0; // 非缓存、非缓冲 + axi_m_awprot <= 3'd0; // 普通非特权数据访问 + axi_m_awqos <= 5'd0; // 默认QoS级别 + axi_m_awvalid <= 1'b0; + end else begin + case (axi_state) + AXI_AW: begin + axi_m_awid <= 8'd0; // 固定ID为0 + axi_m_awaddr <= curr_addr; // 当前地址 + axi_m_awlen <= 4'd0; // 突发长度为1(0+1) + axi_m_awsize <= 3'd5; // 保持32字节宽度 + axi_m_awburst <= 2'd0; // 保持增量突发 + axi_m_awvalid <= 1'b1; // 地址有效 + end + default: begin + axi_m_awvalid <= 1'b0; // 非地址状态时无效 + end + endcase + end +end + +// 3. AXI W通道信号生成逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_wid <= {AXI_ID_W{1'b0}}; + axi_m_wdata <= {AXI_DATA_W{1'b0}}; + axi_m_wstrb <= {AXI_STRB_W{1'b1}}; // 所有字节有效 + axi_m_wlast <= 1'b1; // 单拍突发，始终为1 + axi_m_wvalid <= 1'b0; + fifo_rd_en <= 1'b0; + end else begin + case (axi_state) + AXI_AW: begin + // 地址握手完成前预读FIFO + if (axi_m_awready) begin + fifo_rd_en <= 1'b1; // 读取FIFO数据 + axi_m_wid <= 8'd0; // 与AW通道ID保持一致 + axi_m_wdata <= fifo_rd_data; // 锁存FIFO数据 + axi_m_wvalid <= 1'b1; // 数据有效 + end else begin + fifo_rd_en <= 1'b0; + axi_m_wvalid <= 1'b0; + end + end + AXI_W: begin + fifo_rd_en <= 1'b0; // 停止读FIFO + // 数据握手完成后失效 + if (axi_m_wready) begin + axi_m_wvalid <= 1'b0; + end + end + default: begin + fifo_rd_en <= 1'b0; + axi_m_wvalid <= 1'b0; + end + endcase + end +end + +// 4. AXI B通道信号生成逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_bready <= 1'b0; + end else begin + case (axi_state) + AXI_B: begin + axi_m_bready <= 1'b1; // 准备接收响应 + // 响应握手完成后失效 + if (axi_m_bvalid) begin + axi_m_bready <= 1'b0; + end + end + default: begin + axi_m_bready <= 1'b0; + end + endcase + end +end + +endmodule + \ No newline at end of file diff --git a/rtl/data_cache/data_assemble.v b/rtl/data_cache/data_assemble.v new file mode 100644 index 0000000..76c0dd0 --- /dev/null +++ b/rtl/data_cache/data_assemble.v @@ -0,0 +1,109 @@ +module data_assemble #( + parameter PIXEL_WIDTH = 8, // 单通道像素位宽 + parameter GRAY_PIXEL_CNT = 32, // Gray模式：32个8bit→256bit + parameter RGB_PIXEL_CNT = 8 // RGB模式：8个32bit（24bit数据+8bit补零）→256bit +) ( + input wire clk, + input wire rst_n, + input wire en, // 拼接使能 + input wire input_pixel_type, // 0=Gray，1=RGB + input wire [PIXEL_WIDTH-1:0] ir_ch0, // CH0数据 + input wire [PIXEL_WIDTH-1:0] ir_ch1, // CH1数据 + input wire [PIXEL_WIDTH-1:0] ir_ch2, // CH2数据 + input wire pixel_valid, // 像素有效 + output reg done, // 拼接完成（256bit就绪） + output reg [255:0] assembled_data // 拼接后256bit数据 +); + +// 内部信号 +reg [4:0] gray_cnt; // Gray模式计数器（0~31） +reg [2:0] rgb_cnt; // RGB模式计数器（0~7） +reg [255:0] data_reg; // 拼接数据寄存器 +reg sync_out,sync_out_r; + + +// 拼接计数器复位逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + gray_cnt <= 5'd0; + rgb_cnt <= 3'd0; + end else if (!en) begin + gray_cnt <= 5'd0; + rgb_cnt <= 3'd0; + end else if (pixel_valid) begin + case (input_pixel_type) + 1'b0: begin // Gray模式 + gray_cnt <= (gray_cnt == GRAY_PIXEL_CNT ) ? 5'd0 : gray_cnt + 5'd1; + end + 1'b1: begin // RGB模式 + rgb_cnt <= (rgb_cnt == RGB_PIXEL_CNT ) ? 3'd0 : rgb_cnt + 3'd1; + end + endcase + end +end + +// 数据拼接逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + data_reg <= 256'd0; + assembled_data <= 256'd0; + sync_out <= 'd0; + sync_out_r <= 'd0; + end else if (!en) begin + sync_out <= 'd0; + data_reg <= 256'd0; + assembled_data <= 256'd0; + done <= 'd0; + end else if (pixel_valid) begin + + case (input_pixel_type) + 1'b0: begin // Gray模式：32x8bit→256bit（高位到低位拼接） + data_reg[(GRAY_PIXEL_CNT -1- gray_cnt) * PIXEL_WIDTH +: PIXEL_WIDTH] <= ir_ch0; + // 计数器满：拼接完成，锁存数据 + if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin + sync_out = 1'd1; + //data_reg <= 256'd0; // 复位寄存器，准备下一轮 + end + end + 1'b1: begin // RGB模式：8x32bit→256bit（32bit=8bit补零+CH2+CH1+CH0） + reg [31:0] rgb_pixel; + rgb_pixel = {8'd0, ir_ch2, ir_ch1, ir_ch0}; // 补零+三通道数据 + data_reg[(RGB_PIXEL_CNT - 1 - rgb_cnt) * 32 +: 32] <= rgb_pixel; + // 计数器满：拼接完成，锁存数据 + if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin + sync_out = 1'd1; + //data_reg <= 256'd0; // 复位寄存器，准备下一轮 + end + end + endcase + end +end + + + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + sync_out_r <= 'd0; + end else begin + sync_out_r <= sync_out; + end +end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + assembled_data <= 'd0; + done <= 'd0; + end else if (sync_out_r) begin + assembled_data <= data_reg; + done <= 1'b1; + end +end + +always @(posedge clk or negedge rst_n) begin + if (done == 1'b1) begin + done <= 'd0; + end +end + + +endmodule \ No newline at end of file diff --git a/rtl/data_cache/data_cache.v b/rtl/data_cache/data_cache.v new file mode 100644 index 0000000..c4865c6 --- /dev/null +++ b/rtl/data_cache/data_cache.v @@ -0,0 +1,470 @@ +module data_cache #( + // 异步FIFO参数（IR→系统时钟域） + parameter ASYNC_FIFO_DEPTH = 1024, // 异步FIFO深度 + parameter ASYNC_FIFO_DATA_W = 27, // 27bit=1(ir_valid)+1(ir_vs)+1(ir_hs)+8(ch0)+8(ch1)+8(ch2) + // 同步FIFO参数（系统时钟域，256bit数据缓存） + parameter SYNC_FIFO_DEPTH = 2048, // 同步FIFO深度（适配256x256图像） + parameter SYNC_FIFO_DATA_W = 256, // 同步FIFO数据位宽（AXI写数据位宽） + // 直方图RAM参数（1x256，每个通道1个） + parameter HIST_RAM_DEPTH = 256, // 直方图RAM深度（0~255，对应8bit像素值） + parameter HIST_RAM_DATA_W = 1, // 直方图RAM数据位宽（1bit：存在标记） + // AXI参数 + parameter AXI_ID_W = 8, // AXI AW/W ID位宽 + parameter AXI_ADDR_W = 32, // AXI地址位宽 + parameter AXI_DATA_W = 256, // AXI数据位宽（与SYNC_FIFO_DATA_W一致） + parameter AXI_STRB_W = AXI_DATA_W / 8 // AXI WSTRB位宽（32bit） +) ( + // -------------------------- Common 端口 -------------------------- + input wire clk, // 系统时钟（AXI/控制逻辑时钟） + input wire rst_n, // 系统复位（低有效，同步clk） + // -------------------------- 配置信号端口 -------------------------- + input wire ipa_en, // IPA总使能 + input wire update_src_trig, // 更新原始图像触发（高有效） + input wire input_pixel_type, // 输入像素类型：0=Gray，1=RGB + input wire [15:0] src_pixel_height, // 原始图像高度 + input wire [15:0] src_pixel_width, // 原始图像宽度 + input wire [15:0] histogram_low_num, // 直方图低位数（计算min用） + input wire [15:0] histogram_high_num, // 直方图高位数（计算max用） + output reg src_image_cache_done, // 原始图像缓存完成（高有效） + // -------------------------- 连接Windowed模块端口 -------------------------- + output reg [7:0] dwidth_conv_min_ch0, // CH0归一化min值 + output reg [7:0] dwidth_conv_max_ch0, // CH0归一化max值 + output reg [7:0] dwidth_conv_min_ch1, // CH1归一化min值 + output reg [7:0] dwidth_conv_max_ch1, // CH1归一化max值 + output reg [7:0] dwidth_conv_min_ch2, // CH2归一化min值 + output reg [7:0] dwidth_conv_max_ch2, // CH2归一化max值 + // -------------------------- IR图像输入端口（IR时钟域） -------------------------- + input wire ir_clk, // IR像素同步时钟 + input wire ir_valid, // IR像素有效信号 + input wire ir_vs, // IR垂直同步（帧起始） + input wire ir_hs, // IR水平同步（行起始） + input wire [7:0] ir_ch0, // IR CH0数据（Gray时有效） + input wire [7:0] ir_ch1, // IR CH1数据（RGB时有效） + input wire [7:0] ir_ch2, // IR CH2数据（RGB时有效） + // -------------------------- AXI写总线端口（系统时钟域） -------------------------- + output reg [AXI_ID_W-1:0] axi_m_awid, // AXI AW通道ID + output reg [AXI_ADDR_W-1:0] axi_m_awaddr, // AXI AW通道地址（SRAM起始地址） + output reg [3:0] axi_m_awlen, // AXI AW通道突发长度（0=1拍） + output reg [2:0] axi_m_awsize, // AXI AW通道数据宽度（5=32字节=256bit） + output reg [1:0] axi_m_awburst, // AXI AW通道突发类型（0=INCR） + output reg axi_m_awlock, // AXI AW通道锁定（0=普通） + output reg [3:0] axi_m_awcache, // AXI AW通道缓存属性（0=非缓存） + output reg [2:0] axi_m_awprot, // AXI AW通道保护属性（0=普通） + output reg [3:0] axi_m_awqos, // AXI AW通道QoS（0=默认） + output reg axi_m_awvalid, // AXI AW通道有效 + input wire axi_m_awready, // AXI AW通道就绪 + output reg [AXI_ID_W-1:0] axi_m_wid, // AXI W通道ID（与AW一致） + output reg [AXI_DATA_W-1:0] axi_m_wdata, // AXI W通道数据（256bit） + output reg [AXI_STRB_W-1:0] axi_m_wstrb, // AXI W通道字节使能（全1=有效） + output reg axi_m_wlast, // AXI W通道突发结束标记 + output reg axi_m_wvalid, // AXI W通道有效 + input wire axi_m_wready, // AXI W通道就绪 + input wire [AXI_ID_W-1:0] axi_m_bid, // AXI B通道ID + input wire [1:0] axi_m_bresp, // AXI B通道响应（0=OKAY） + input wire axi_m_bvalid, // AXI B通道有效 + output reg axi_m_bready // AXI B通道就绪 +); + +// -------------------------- 内部信号定义 -------------------------- +// 1. 复位同步（跨时钟域复位处理） +wire rst_n_ir; // IR时钟域同步后的复位 +wire rst_n_sys; // 系统时钟域同步后的复位 + +// 2. 异步FIFO信号（IR→系统时钟域） +wire async_fifo_wr_en; // 异步FIFO写使能（IR时钟域） +wire [ASYNC_FIFO_DATA_W-1:0] async_fifo_wr_data; // 异步FIFO写数据（IR时钟域） +wire async_fifo_full; // 异步FIFO满（IR时钟域） +wire async_fifo_rd_en; // 异步FIFO读使能（系统时钟域） +wire [ASYNC_FIFO_DATA_W-1:0] async_fifo_rd_data; // 异步FIFO读数据（系统时钟域） +wire async_fifo_empty; // 异步FIFO空（系统时钟域） + +// 3. 跨域后像素信号（系统时钟域） +wire ir_valid_sys; // 跨域后像素有效 +wire ir_vs_sys; // 跨域后帧起始 +wire ir_hs_sys; // 跨域后行起始 +wire [7:0] ir_ch0_sys; // 跨域后CH0数据 +wire [7:0] ir_ch1_sys; // 跨域后CH1数据 +wire [7:0] ir_ch2_sys; // 跨域后CH2数据 +reg flag; + +// 4. 直方图控制信号 +wire hist_rst; // 直方图RAM复位（帧起始/更新触发） +wire hist_wr_en_ch0; // CH0直方图写使能 +wire [7:0] hist_wr_addr_ch0; // CH0直方图写地址（像素值） +wire hist_wr_en_ch1; // CH1直方图写使能 +wire [7:0] hist_wr_addr_ch1; // CH1直方图写地址（像素值） +wire hist_wr_en_ch2; // CH2直方图写使能 +wire [7:0] hist_wr_addr_ch2; // CH2直方图写地址（像素值） +reg hist_calc_en; // 直方图min/max计算使能（帧结束后） +wire hist_calc_done; // 直方图min/max计算完成 + +// 5. 数据拼接信号 +wire assemble_en; // 数据拼接使能 +wire assemble_done; // 数据拼接完成（256bit就绪） +wire [255:0] assemble_data; // 拼接后256bit数据 + +// 6. 同步FIFO信号（系统时钟域） +wire sync_fifo_wr_en; // 同步FIFO写使能 +wire [255:0] sync_fifo_wr_data;// 同步FIFO写数据（拼接后256bit） +wire sync_fifo_full; // 同步FIFO满 +wire sync_fifo_rd_en; // 同步FIFO读使能 +wire [255:0] sync_fifo_rd_data;// 同步FIFO读数据 +wire sync_fifo_empty; // 同步FIFO空 + +// 7. 帧计数与状态信号 +reg [15:0] col_cnt; // 列计数器（像素宽度计数） +reg [15:0] row_cnt; // 行计数器（像素高度计数） +reg frame_active; // 帧活跃标记（IR_VS后到帧结束） +reg axi_write_busy; // AXI写事务忙标记 +wire axi_write_done; // 来自 axi_write_ctrl 的写完成标志 + +// 8. 状态机定义 +// typedef enum logic [2:0] { +// S_IDLE, // 空闲（等待IPA使能） +// S_WAIT_VS, // 等待帧起始（IR_VS） +// S_RECEIVE_DATA, // 接收像素数据（写直方图+拼接） +// S_WRITE_FIFO, // 拼接完成写同步FIFO +// S_WAIT_AXI, // 等待AXI写完成 +// S_FRAME_DONE // 帧缓存完成（置位src_image_cache_done） +// } data_cache_state_t; + +localparam [3:0] S_IDLE = 3'b000; +localparam [3:0] S_WAIT_VS = 3'b001; +localparam [3:0] S_RECEIVE_DATA = 3'b010; +localparam [3:0] S_WRITE_FIFO = 3'b011; +localparam [3:0] S_WAIT_AXI = 3'b100; +localparam [3:0] S_FRAME_DONE = 3'b101; + +reg [2:0] curr_state; +reg [2:0] next_state; + + +// -------------------------- 子模块实例化 -------------------------- +// 1. 复位同步（确保跨时钟域复位稳定） +rst_sync #( + .SYNC_STAGE(2) // 2级同步 +) u_rst_sync_ir ( + .clk(ir_clk), + .rst_n_in(rst_n), + .rst_n_out(rst_n_ir) +); + +rst_sync #( + .SYNC_STAGE(2) +) u_rst_sync_sys ( + .clk(clk), + .rst_n_in(rst_n), + .rst_n_out(rst_n_sys) +); + +// 2. 异步FIFO（IR时钟域→系统时钟域，传输像素数据+控制信号） +async_fifo #( + .FIFO_DEPTH(ASYNC_FIFO_DEPTH), + .DATA_WIDTH(ASYNC_FIFO_DATA_W) +) u_async_fifo ( + // 写端口（IR时钟域） + .wr_clk(ir_clk), + .wr_rst_n(rst_n_ir), + .wr_en(async_fifo_wr_en), + .wr_data(async_fifo_wr_data), + .full(async_fifo_full), + // 读端口（系统时钟域） + .rd_clk(clk), + .rd_rst_n(rst_n_sys), + .rd_en(async_fifo_rd_en), + .rd_data(async_fifo_rd_data), + .empty(async_fifo_empty) +); + +// 3. 直方图控制模块（统计CH0/CH1/CH2直方图，计算min/max） +histogram_ctrl #( + .HIST_RAM_DEPTH(HIST_RAM_DEPTH), + .HIST_RAM_DATA_W(HIST_RAM_DATA_W) +) u_histogram_ctrl ( + .clk(clk), + .rst_n(rst_n_sys), + .hist_rst(hist_rst), + .input_pixel_type(input_pixel_type), + .hist_wr_en_ch0(hist_wr_en_ch0), + .hist_wr_addr_ch0(hist_wr_addr_ch0), + .hist_wr_en_ch1(hist_wr_en_ch1), + .hist_wr_addr_ch1(hist_wr_addr_ch1), + .hist_wr_en_ch2(hist_wr_en_ch2), + .hist_wr_addr_ch2(hist_wr_addr_ch2), + .histogram_low_num(histogram_low_num), + .histogram_high_num(histogram_high_num), + .calc_en(hist_calc_en), + .calc_done(hist_calc_done), + .dwidth_conv_min_ch0(dwidth_conv_min_ch0), + .dwidth_conv_max_ch0(dwidth_conv_max_ch0), + .dwidth_conv_min_ch1(dwidth_conv_min_ch1), + .dwidth_conv_max_ch1(dwidth_conv_max_ch1), + .dwidth_conv_min_ch2(dwidth_conv_min_ch2), + .dwidth_conv_max_ch2(dwidth_conv_max_ch2) +); + +// 4. 数据拼接模块（Gray:32x8bit→256bit；RGB:8x32bit→256bit） +data_assemble #( + .PIXEL_WIDTH(8), // 单通道像素位宽 + .GRAY_PIXEL_CNT(32), // Gray模式拼接像素数（32x8bit=256bit） + .RGB_PIXEL_CNT(8) // RGB模式拼接像素数（8x32bit=256bit） +) u_data_assemble ( + .clk(clk), + .rst_n(rst_n_sys), + .en(assemble_en), + .input_pixel_type(input_pixel_type), + .ir_ch0(ir_ch0_sys), + .ir_ch1(ir_ch1_sys), + .ir_ch2(ir_ch2_sys), + .pixel_valid(async_fifo_rd_data[26]), + .done(assemble_done), + .assembled_data(assemble_data) +); + +// 5. 同步FIFO（缓存拼接后的256bit数据，适配AXI写速度） +sync_fifo #( + .FIFO_DEPTH(SYNC_FIFO_DEPTH), + .DATA_WIDTH(SYNC_FIFO_DATA_W) +) u_sync_fifo ( + .clk(clk), + .rst_n(rst_n_sys), + .wr_en(sync_fifo_wr_en), + .wr_data(sync_fifo_wr_data), + .full(sync_fifo_full), + .rd_en(sync_fifo_rd_en), + .rd_data(sync_fifo_rd_data), + .empty(sync_fifo_empty) +); + +// 6. AXI写控制模块（从同步FIFO读数据，发起AXI写事务） +axi_write_ctrl #( + .AXI_ID_W(AXI_ID_W), + .AXI_ADDR_W(AXI_ADDR_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_STRB_W(AXI_STRB_W) +) u_axi_write_ctrl ( + .clk(clk), + .rst_n(rst_n_sys), + .start_en(!sync_fifo_empty && !axi_write_busy), // FIFO非空且AXI空闲时启动 + .sram_base_addr(32'h0000_0000), // SRAM基地址（可配置） + .fifo_rd_data(sync_fifo_rd_data), + .fifo_empty(sync_fifo_empty), + .fifo_rd_en(sync_fifo_rd_en), + .axi_m_awid(axi_m_awid), + .axi_m_awaddr(axi_m_awaddr), + .axi_m_awlen(axi_m_awlen), + .axi_m_awsize(axi_m_awsize), + .axi_m_awburst(axi_m_awburst), + .axi_m_awlock(axi_m_awlock), + .axi_m_awcache(axi_m_awcache), + .axi_m_awprot(axi_m_awprot), + .axi_m_awqos(axi_m_awqos), + .axi_m_awvalid(axi_m_awvalid), + .axi_m_awready(axi_m_awready), + .axi_m_wid(axi_m_wid), + .axi_m_wdata(axi_m_wdata), + .axi_m_wstrb(axi_m_wstrb), + .axi_m_wlast(axi_m_wlast), + .axi_m_wvalid(axi_m_wvalid), + .axi_m_wready(axi_m_wready), + .axi_m_bid(axi_m_bid), + .axi_m_bresp(axi_m_bresp), + .axi_m_bvalid(axi_m_bvalid), + .axi_m_bready(axi_m_bready), + .axi_busy(axi_write_busy), + .axi_done(axi_write_done) +); + + +// -------------------------- 核心逻辑实现 -------------------------- +// assign flag = (col_cnt == src_pixel_width-1'd1); +assign axi_write_done = (axi_m_bvalid && axi_m_bready); +// 1. 异步FIFO写控制（IR时钟域） +assign async_fifo_wr_data = {ir_valid, ir_vs, ir_hs, ir_ch2, ir_ch1, ir_ch0}; +assign async_fifo_wr_en = ir_valid && !async_fifo_full && ipa_en; // 像素有效且FIFO未满 + +// 2. 异步FIFO读控制（系统时钟域） +assign async_fifo_rd_en = !async_fifo_empty && + (curr_state == S_WAIT_VS || frame_active) && !flag; // 帧活跃且FIFO非空 + +// 3. 跨域后信号解析（系统时钟域） +assign ir_valid_sys = async_fifo_rd_data[26] && !flag; // [26] = ir_valid +assign ir_vs_sys = async_fifo_rd_data[25]; // [25] = ir_vs +assign ir_hs_sys = async_fifo_rd_data[24]; // [24] = ir_hs +assign ir_ch2_sys = async_fifo_rd_data[23:16];// [23:16] = ir_ch2 +assign ir_ch1_sys = async_fifo_rd_data[15:8]; // [15:8] = ir_ch1 +assign ir_ch0_sys = async_fifo_rd_data[7:0]; // [7:0] = ir_ch0 + +// 4. 直方图写控制（系统时钟域） +assign hist_rst = update_src_trig || ir_vs_sys; // 更新触发或帧起始时复位直方图 +assign hist_wr_en_ch0 = ir_valid_sys && frame_active; // CH0始终写（Gray/RGB均有效） +assign hist_wr_addr_ch0 = ir_ch0_sys; +assign hist_wr_en_ch1 = ir_valid_sys && frame_active && (input_pixel_type == 1'b1); // RGB时写CH1 +assign hist_wr_addr_ch1 = ir_ch1_sys; +assign hist_wr_en_ch2 = ir_valid_sys && frame_active && (input_pixel_type == 1'b1); // RGB时写CH2 +assign hist_wr_addr_ch2 = ir_ch2_sys; +//assign hist_calc_en = (row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1); // 帧结束后计算min/max + +// 5. 数据拼接使能控制 +assign assemble_en = frame_active && ir_valid_sys && !ir_vs_sys; + +// 6. 同步FIFO写控制 +assign sync_fifo_wr_en = assemble_done && !sync_fifo_full; +assign sync_fifo_wr_data = assemble_data; + +// 7. 帧计数逻辑 - 修复frame_active激活（关键：不依赖frame_active读FIFO） +always @(posedge clk or negedge rst_n_sys) begin + if (!rst_n_sys) begin + col_cnt <= 16'd0; + row_cnt <= 16'd0; + frame_active <= 1'b0; + end else if (update_src_trig) begin + col_cnt <= 16'd0; + row_cnt <= 16'd0; + frame_active <= 1'b0; + end else if (ir_vs_sys && curr_state == S_WAIT_VS) begin + // WAIT_VS状态下，ir_vs_sys=1 → 激活frame_active + col_cnt <= 16'd0; + row_cnt <= 16'd0; + frame_active <= 1'b1; + end else if (curr_state == S_RECEIVE_DATA) begin + // RECEIVE_DATA状态下保持frame_active=1，直到帧结束 + frame_active <= 1'b1; + if (ir_valid_sys && !ir_vs_sys) begin + col_cnt <= col_cnt + 16'd1; + if (col_cnt == src_pixel_width - 16'd1) begin + col_cnt <= 16'd0; + row_cnt <= row_cnt + 16'd1; + if (row_cnt == src_pixel_height - 16'd1) begin + frame_active <= 1'b0; + end + end + end + end else begin + frame_active <= 1'b0; + end +end + +// 8. 状态机时序逻辑 +always @(posedge clk or negedge rst_n_sys) begin + if (!rst_n_sys) begin + curr_state <= S_IDLE; + end else begin + curr_state <= next_state; + end +end + +// 9. 状态机组合逻辑（状态转移） +always @(*) begin + next_state = curr_state; + case (curr_state) + S_IDLE: begin + // 等待IPA使能 + if (ipa_en && !update_src_trig) begin + next_state = S_WAIT_VS; + end + end + S_WAIT_VS: begin + // 等待帧起始（IR_VS） + if (ir_vs_sys) begin + next_state = S_RECEIVE_DATA; + end else if (update_src_trig) begin + next_state = S_IDLE; + end + end + S_RECEIVE_DATA: begin + // 接收数据：直到帧结束（行/列计数满） + if ((row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1)) begin + next_state = S_WRITE_FIFO; + end else if (update_src_trig) begin + next_state = S_IDLE; + end + end + S_WRITE_FIFO: begin + // 条件1：同步FIFO已空（数据已全部读出到AXI控制器），但AXI仍在忙碌 → 等待AXI完成 + if (sync_fifo_empty && axi_write_busy) begin + next_state = S_WAIT_AXI; + end + // 条件2：同步FIFO已空，且AXI已完成所有写操作 → 直接进入帧完成 + else if (sync_fifo_empty && !axi_write_busy) begin + next_state = S_FRAME_DONE; + end + // 条件3：收到更新触发 → 强制回到IDLE + else if (update_src_trig) begin + next_state = S_IDLE; + end + end + S_WAIT_AXI: begin + // AXI写完成后进入帧完成状态 + if (axi_write_done) begin + next_state = S_FRAME_DONE; + end + // 收到更新触发 → 强制回到IDLE + else if (update_src_trig) begin + next_state = S_IDLE; + end + end + S_FRAME_DONE: begin + // 帧完成：保持1拍后回到等待VS（支持连续帧） + if (src_image_cache_done) begin + next_state = S_WAIT_VS; + end else begin + next_state = S_FRAME_DONE; + end + end + endcase +end + +// 10. 状态机输出逻辑（控制各模块行为） +always @(posedge clk or negedge rst_n_sys) begin + if (!rst_n_sys) begin + src_image_cache_done <= 1'b0; + end else begin + src_image_cache_done <= 1'b0; + case (curr_state) + S_FRAME_DONE: begin + // 帧完成：置位缓存完成信号，并等待直方图计算完成 + src_image_cache_done <= hist_calc_done; + end + default: begin + src_image_cache_done <= 1'b0; + end + endcase + end +end + +always @(posedge clk or negedge rst_n_sys) begin + if (!rst_n_sys) begin + hist_calc_en <= 'd0; + end else begin + hist_calc_en <= (row_cnt == src_pixel_height-1'd1) && (col_cnt == src_pixel_width-1'd1); + end + +end + +// always @(posedge clk or negedge rst_n_sys) begin +// if (!rst_n_sys) begin +// assemble_en <= 'd0; +// end else begin +// assemble_en <= frame_active && ir_valid_sys && !ir_vs_sys; +// end + +// end +reg [1:0] flag_cnt; +always @(posedge clk or negedge rst_n_sys) begin + if (!rst_n_sys) begin + flag <= 'd0; + flag_cnt <='d0; + end else if (flag == 1'b1)begin + flag_cnt <= flag_cnt + 1'b1; + if (flag_cnt == 2'd2) begin + flag <= 'd0; + flag_cnt <='d0; + end + end else if (col_cnt == src_pixel_width-1'd1) begin + flag <= 1'b1; + end +end + + +endmodule \ No newline at end of file diff --git a/rtl/data_cache/histogram_ctrl.v b/rtl/data_cache/histogram_ctrl.v new file mode 100644 index 0000000..4df65ab --- /dev/null +++ b/rtl/data_cache/histogram_ctrl.v @@ -0,0 +1,231 @@ +module histogram_ctrl #( + parameter HIST_RAM_DEPTH = 256, + parameter HIST_RAM_DATA_W = 1 +) ( + input wire clk, + input wire rst_n, + input wire hist_rst, // 直方图复位 + input wire input_pixel_type, // 0=Gray，1=RGB + input wire hist_wr_en_ch0, // CH0写使能 + input wire [7:0] hist_wr_addr_ch0, // CH0写地址（像素值0~255） + input wire hist_wr_en_ch1, // CH1写使能 + input wire [7:0] hist_wr_addr_ch1, // CH1写地址 + input wire hist_wr_en_ch2, // CH2写使能 + input wire [7:0] hist_wr_addr_ch2, // CH2写地址 + input wire [15:0] histogram_low_num, // 低位数（计算min） + input wire [15:0] histogram_high_num,// 高位数（计算max） + input wire calc_en, // 计算使能 + output reg calc_done, // 计算完成 + output reg [7:0] dwidth_conv_min_ch0, + output reg [7:0] dwidth_conv_max_ch0, + output reg [7:0] dwidth_conv_min_ch1, + output reg [7:0] dwidth_conv_max_ch1, + output reg [7:0] dwidth_conv_min_ch2, + output reg [7:0] dwidth_conv_max_ch2 +); + +// 内部信号 +reg [HIST_RAM_DATA_W-1:0] hist_ram_ch0 [HIST_RAM_DEPTH-1:0]; // CH0直方图RAM +reg [HIST_RAM_DATA_W-1:0] hist_ram_ch1 [HIST_RAM_DEPTH-1:0]; // CH1直方图RAM +reg [HIST_RAM_DATA_W-1:0] hist_ram_ch2 [HIST_RAM_DEPTH-1:0]; // CH2直方图RAM +reg [7:0] calc_addr; // 遍历地址（0~255） +reg [15:0] low_cnt_ch0; // CH0低位数计数器 +reg [15:0] high_cnt_ch0; // CH0高位数计数器 +reg [15:0] low_cnt_ch1; // CH1低位数计数器 +reg [15:0] high_cnt_ch1; // CH1高位数计数器 +reg [15:0] low_cnt_ch2; // CH2低位数计数器 +reg [15:0] high_cnt_ch2; // CH2高位数计数器 +reg calc_active; // 计算活跃标记 + +// 状态定义 + +localparam [1:0] S_HIST_IDLE = 2'b00; +localparam [1:0] S_HIST_CLEAR = 2'b01; +localparam [1:0] S_HIST_WRITE = 2'b10; +localparam [1:0] S_HIST_CALC = 2'b11; + +reg [1:0] curr_hist_state; +reg [1:0] next_hist_state; + +// 1. 状态机时序逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + curr_hist_state <= S_HIST_IDLE; + end else begin + curr_hist_state <= next_hist_state; + end +end + +// 2. 状态机组合逻辑 +always @(*) begin + next_hist_state = curr_hist_state; + case (curr_hist_state) + S_HIST_IDLE: begin + if (hist_rst) begin + next_hist_state = S_HIST_CLEAR; + end else if (hist_wr_en_ch0 || hist_wr_en_ch1 || hist_wr_en_ch2) begin + next_hist_state = S_HIST_WRITE; + end else if (calc_en) begin + next_hist_state = S_HIST_CALC; + end + end + S_HIST_CLEAR: begin + if (calc_addr == HIST_RAM_DEPTH - 1) begin + next_hist_state = S_HIST_IDLE; + end + end + S_HIST_WRITE: begin + if (hist_rst) begin + next_hist_state = S_HIST_CLEAR; + end else if (calc_en) begin + next_hist_state = S_HIST_CALC; + end + end + S_HIST_CALC: begin + if (calc_addr == HIST_RAM_DEPTH - 1) begin + next_hist_state = S_HIST_IDLE; + end + end + endcase +end + +// 3. 直方图RAM复位/写逻辑 +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + // 复位所有RAM + integer i; + for (i = 0; i < HIST_RAM_DEPTH; i = i+1) begin + hist_ram_ch0[i] <= 1'b0; + hist_ram_ch1[i] <= 1'b0; + hist_ram_ch2[i] <= 1'b0; + end + calc_addr <= 8'd0; + end else begin + case (curr_hist_state) + S_HIST_CLEAR: begin + // 清空RAM（地址递增） + hist_ram_ch0[calc_addr] <= 1'b0; + hist_ram_ch1[calc_addr] <= 1'b0; + hist_ram_ch2[calc_addr] <= 1'b0; + calc_addr <= calc_addr + 8'd1; + end + S_HIST_WRITE: begin + // CH0写（始终有效） + if (hist_wr_en_ch0) begin + hist_ram_ch0[hist_wr_addr_ch0] <= 1'b1; // 标记像素值存在 + end + // CH1/CH2写（仅RGB模式有效） + if (hist_wr_en_ch1 && (input_pixel_type == 1'b1)) begin + hist_ram_ch1[hist_wr_addr_ch1] <= 1'b1; + end + if (hist_wr_en_ch2 && (input_pixel_type == 1'b1)) begin + hist_ram_ch2[hist_wr_addr_ch2] <= 1'b1; + end + calc_addr <= 8'd0; + end + S_HIST_CALC: begin + // 遍历地址递增 + calc_addr <= calc_addr + 8'd1; + end + default: begin + calc_addr <= 8'd0; + end + endcase + end +end + +// 4. 修复后的直方图min/max计算逻辑（关键修复点） +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + low_cnt_ch0 <= 16'd0; + high_cnt_ch0 <= 16'd0; + low_cnt_ch1 <= 16'd0; + high_cnt_ch1 <= 16'd0; + low_cnt_ch2 <= 16'd0; + high_cnt_ch2 <= 16'd0; + dwidth_conv_min_ch0 <= 8'd0; + dwidth_conv_max_ch0 <= 8'd255; + dwidth_conv_min_ch1 <= 8'd0; + dwidth_conv_max_ch1 <= 8'd255; + dwidth_conv_min_ch2 <= 8'd0; + dwidth_conv_max_ch2 <= 8'd255; + calc_done <= 1'b0; + calc_active <= 1'b0; + end else begin + calc_done <= 1'b0; + case (curr_hist_state) + S_HIST_CALC: begin + calc_active <= 1'b1; + // -------------------------- 关键修复1：计算开始时强制清零计数器 -------------------------- + if (calc_addr == 8'd0) begin // 遍历地址为0时（计算起始），清零所有计数器 + low_cnt_ch0 <= 16'd0; + high_cnt_ch0 <= 16'd0; + low_cnt_ch1 <= 16'd0; + high_cnt_ch1 <= 16'd0; + low_cnt_ch2 <= 16'd0; + high_cnt_ch2 <= 16'd0; + end + + // -------------------------- CH0计算 -------------------------- + // min：0→255遍历，找第histogram_low_num个1 + if (low_cnt_ch0 < histogram_low_num && hist_ram_ch0[calc_addr] == 1'b1) begin + low_cnt_ch0 <= low_cnt_ch0 + 16'd1; + if (low_cnt_ch0 == histogram_low_num - 16'd1) begin + dwidth_conv_min_ch0 <= calc_addr; + end + end + // max：255→0遍历，找第histogram_high_num个1 + if (high_cnt_ch0 < histogram_high_num && hist_ram_ch0[255 - calc_addr] == 1'b1) begin + high_cnt_ch0 <= high_cnt_ch0 + 16'd1; + if (high_cnt_ch0 == histogram_high_num - 16'd1) begin + dwidth_conv_max_ch0 <= 255 - calc_addr; + end + end + + // -------------------------- CH1计算（仅RGB模式） -------------------------- + if (input_pixel_type == 1'b1) begin + if (low_cnt_ch1 < histogram_low_num && hist_ram_ch1[calc_addr] == 1'b1) begin + low_cnt_ch1 <= low_cnt_ch1 + 16'd1; + if (low_cnt_ch1 == histogram_low_num - 16'd1) begin + dwidth_conv_min_ch1 <= calc_addr; + end + end + if (high_cnt_ch1 < histogram_high_num && hist_ram_ch1[255 - calc_addr] == 1'b1) begin + high_cnt_ch1 <= high_cnt_ch1 + 16'd1; + if (high_cnt_ch1 == histogram_high_num - 16'd1) begin + dwidth_conv_max_ch1 <= 255 - calc_addr; + end + end + end + + // -------------------------- CH2计算（仅RGB模式） -------------------------- + if (input_pixel_type == 1'b1) begin + if (low_cnt_ch2 < histogram_low_num && hist_ram_ch2[calc_addr] == 1'b1) begin + low_cnt_ch2 <= low_cnt_ch2 + 16'd1; + if (low_cnt_ch2 == histogram_low_num - 16'd1) begin + dwidth_conv_min_ch2 <= calc_addr; + end + end + if (high_cnt_ch2 < histogram_high_num && hist_ram_ch2[255 - calc_addr] == 1'b1) begin + high_cnt_ch2 <= high_cnt_ch2 + 16'd1; + if (high_cnt_ch2 == histogram_high_num - 16'd1) begin + dwidth_conv_max_ch2 <= 255 - calc_addr; + end + end + end + + // -------------------------- 遍历结束：置位完成信号 -------------------------- + if (calc_addr == HIST_RAM_DEPTH - 1) begin + calc_done <= 1'b1; + calc_active <= 1'b0; + end + end + default: begin + calc_active <= 1'b0; + calc_done <= 1'b0; + end + endcase + end +end + +endmodule \ No newline at end of file diff --git a/rtl/data_cache/rst_sync.v b/rtl/data_cache/rst_sync.v new file mode 100644 index 0000000..9b00a7c --- /dev/null +++ b/rtl/data_cache/rst_sync.v @@ -0,0 +1,27 @@ +module rst_sync #( + parameter SYNC_STAGE = 2 // 同步级数（推荐2级） +) ( + input wire clk, + input wire rst_n_in, + output reg rst_n_out +); + +reg [SYNC_STAGE-1:0] rst_sync_reg; + +always @(posedge clk or negedge rst_n_in) begin + if (!rst_n_in) begin + rst_sync_reg <= {SYNC_STAGE{1'b0}}; + end else begin + rst_sync_reg <= {rst_sync_reg[SYNC_STAGE-2:0], 1'b1}; + end +end + +always @(posedge clk or negedge rst_n_in) begin + if (!rst_n_in) begin + rst_n_out <= 1'b0; + end else begin + rst_n_out <= rst_sync_reg[SYNC_STAGE-1]; + end +end + +endmodule \ No newline at end of file diff --git a/rtl/data_cache/sync_fifo.v b/rtl/data_cache/sync_fifo.v new file mode 100644 index 0000000..5e644ad --- /dev/null +++ b/rtl/data_cache/sync_fifo.v @@ -0,0 +1,73 @@ +module sync_fifo #( + parameter DATA_WIDTH = 8, + parameter FIFO_DEPTH = 16 +)( + input clk, + input rst_n, + input wr_en, + input [DATA_WIDTH-1:0] wr_data, + output full, + input rd_en, + output [DATA_WIDTH-1:0] rd_data, + output empty +); + localparam ADDR_WIDTH = $clog2(FIFO_DEPTH); + reg [DATA_WIDTH-1:0] mem [0 : FIFO_DEPTH -1]; + reg [ADDR_WIDTH : 0] wr_ptr, rd_ptr; + wire [ADDR_WIDTH -1:0] wr_addr ,rd_addr; + + assign wr_addr = wr_ptr[ADDR_WIDTH -1:0]; + assign rd_addr = rd_ptr[ADDR_WIDTH -1:0]; + + always@(posedge clk or negedge rst_n) begin + if(!rst_n) begin + wr_ptr <= 'd0; + end else if(wr_en && !full) begin + wr_ptr <= wr_ptr + 1'b1; + end else begin + wr_ptr <= wr_ptr; + end + end + + always@(posedge clk or negedge rst_n) begin + if(!rst_n) begin + rd_ptr <= 'd0; + end else if(rd_en && !empty) begin + rd_ptr <= rd_ptr + 1'b1; + end else begin + rd_ptr <= rd_ptr; + + end + end + + integer i; + always@(posedge clk or negedge rst_n) begin + if(!rst_n) begin + for(i=0;i>rtl.f + find ../tb -name "*.v" >>tb.f +#------------------------------------------------------------------------------------------------------- +comp : clean vcs +#------------------------------------------------------------------------------------------------------- +vcs : + vcs \ + -f rtl.f \ + -f tb.f \ + -timescale=1ns/1ps \ + -full64 -R +vc +v2k -sverilog -debug_access+all\ + | tee vcs.log +#------------------------------------------------------------------------------------------------------- +verdi : + verdi -f rtl.f tb.f -ssf tb.fsdb & +#------------------------------------------------------------------------------------------------------- +clean : + rm -rf *~ *.f core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd +#------------------------------------------------------------------------------------------------------- diff --git a/sim/csrc/Makefile b/sim/csrc/Makefile new file mode 100644 index 0000000..9e1ccbe --- /dev/null +++ b/sim/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include + +CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + -if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + $(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsnew.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsimprofile.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libuclinative.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/sim/csrc/Makefile.hsopt b/sim/csrc/Makefile.hsopt new file mode 100644 index 0000000..445b794 --- /dev/null +++ b/sim/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/sim/csrc/SIM_l.o b/sim/csrc/SIM_l.o new file mode 100644 index 0000000..220c622 Binary files /dev/null and b/sim/csrc/SIM_l.o differ diff --git a/sim/csrc/_16331_archive_1.so b/sim/csrc/_16331_archive_1.so new file mode 120000 index 0000000..b1379c8 --- /dev/null +++ b/sim/csrc/_16331_archive_1.so @@ -0,0 +1 @@ +.//../simv.daidir//_16331_archive_1.so \ No newline at end of file diff --git a/sim/csrc/_vcs_pli_stub_.c b/sim/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/sim/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/sim/csrc/_vcs_pli_stub_.o b/sim/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/sim/csrc/_vcs_pli_stub_.o differ diff --git a/sim/csrc/archive.0/_16331_archive_1.a b/sim/csrc/archive.0/_16331_archive_1.a new file mode 100644 index 0000000..beff135 Binary files /dev/null and b/sim/csrc/archive.0/_16331_archive_1.a differ diff --git a/sim/csrc/archive.0/_16331_archive_1.a.info b/sim/csrc/archive.0/_16331_archive_1.a.info new file mode 100644 index 0000000..d1ab9e4 --- /dev/null +++ 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4 + } + }, + "reusePaths": {} +} \ No newline at end of file diff --git a/sim/csrc/filelist b/sim/csrc/filelist new file mode 100644 index 0000000..0657ffe --- /dev/null +++ b/sim/csrc/filelist @@ -0,0 +1,31 @@ + + +AR=ar +DOTLIBS=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/sim/csrc/filelist.cu b/sim/csrc/filelist.cu new file mode 100644 index 0000000..b3dc8ef --- /dev/null +++ b/sim/csrc/filelist.cu @@ -0,0 +1,33 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _16331_archive_1.so +_16331_archive_1.so : archive.0/_16331_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_16331_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_16331_archive_1.so $@ + + + + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ +objs/amcQw_d.o + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/sim/csrc/filelist.dpi b/sim/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/filelist.hsopt b/sim/csrc/filelist.hsopt new file mode 100644 index 0000000..6a9a029 --- /dev/null +++ b/sim/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/sim/csrc/filelist.hsopt.llvm2_0.objs b/sim/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/sim/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/sim/csrc/filelist.hsopt.objs b/sim/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/sim/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/sim/csrc/filelist.pli b/sim/csrc/filelist.pli new file mode 100644 index 0000000..6000e0d --- /dev/null +++ b/sim/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/home/synopsys/vcs-mx/O-2018.09-1/include -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/sim/csrc/hsim/hsim.sdb b/sim/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..a1d63f7 Binary files /dev/null and b/sim/csrc/hsim/hsim.sdb differ diff --git a/sim/csrc/import_dpic.h b/sim/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/objs/amcQw_d.o b/sim/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..b178051 Binary files /dev/null and b/sim/csrc/objs/amcQw_d.o differ diff --git a/sim/csrc/product_timestamp b/sim/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/rmapats.c b/sim/csrc/rmapats.c new file mode 100644 index 0000000..a682a66 --- /dev/null +++ b/sim/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685); +void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685) +{ + U I1546; + U I1547; + U I1548; + struct futq * I1549; + struct dummyq_struct * pQ = I1288; + I1546 = ((U )vcs_clocks) + I685; + I1548 = I1546 & ((1 << fHashTableSize) - 1); + I1282->I727 = (EBLK *)(-1); + I1282->I731 = I1546; + if (I1546 < (U )vcs_clocks) { + I1547 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1282, I1547 + 1, I1546); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1282->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1282; + peblkFutQ1Tail = I1282; + } + else if ((I1549 = pQ->I1189[I1548].I745)) { + I1282->I733 = (struct eblk *)I1549->I744; + I1549->I744->I727 = (RP )I1282; + I1549->I744 = (RmaEblk *)I1282; + } + else { + sched_hsopt(pQ, I1282, I1546); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/sim/csrc/rmapats.h b/sim/csrc/rmapats.h new file mode 100644 index 0000000..3c38f59 --- /dev/null +++ b/sim/csrc/rmapats.h @@ -0,0 +1,2453 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I368 :5; + HsimExprChar * I904; + UB * I905; + UB * I906; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I908; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I954; + U I955; +} HsCgPeriod; +typedef struct { + U I956[2]; + U I957 :1; + U I958 :1; + U I959 :8; + U I960 :8; + U I961 :8; + U I962 :4; + U I963 :1; + U I964 :1; + unsigned long long I965; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I955; + U I954; + U I969; + U I970; + U I971; + U I972; + U I973; + HsCgPeriod * I974[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I975; + InstNum I976; + U I914; + scalar I977; + UB I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + U I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + HsimSignalMonitor * I993; + RP I994; + RmaTimeStamp64 I995; + U I996; + RmaTimeStamp64 I997; + U I998; + UB I999; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1004; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1004; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I935[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1005; +} SchedSelectGateEblk; +typedef struct { + RP I1006; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1007; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1005; + RP I1007; + vec32 I1008; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1005; + RP I1007; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1005; + RP I1007; + scalar I1009[1]; +} RmaAnySchedECg; +typedef struct { + U I1010; + U I714; + U I914; + U I1011; + RmaIbfIp * I1012; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1013; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1014; +} RmaRootCbkCg; +typedef struct { + RP I1015; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1016; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1017 :1; + vec32 I808; + U I1018; + RP I1019; + RP I1020; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1026; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1026[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1026; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1027; + U I1028 :3; + U I1029 :1; + U I1030 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1031; + RmaIbfPcode I1027; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1034; + U state; + U I1035; + RP I1036; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1038; + RP I1039; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1038; + RP I1039; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1040; + UB I1038; + U * I1041; +} RmaMacroState; +typedef struct { + U iinput; + RP I1042; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1042; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1043; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1044; + RP I1045; + RP I1046; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I914; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1289; + RP I1577; + RP I1591; + } I781; + RmaIbfPcode I1027; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1047; + RmaIbfPcode I1027; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1027; + RmaMps I1048; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1049; + RmaIbfPcode I1027; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1027; + RmaMpspNewCsdf I1050; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1050; + RmaIbfPcode I1027; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I920; + RP I804; + RmaIbfPcode I1027; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I920; + RP I804; + RmaIbfPcode I1027; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1051; + U I1052; + RmaTransEventHdr I920; + RP I804; + RmaIbfPcode I1027; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1051; + U I1052; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1053; + RmaTransEventHdr I920; + RP I804; + RmaIbfPcode I1027; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1053; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1577; + RP I1591; + } I781; + RmaIbfPcode I1027; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1027; +} RmaPortDelay; +typedef struct { + U I890; + RP I1057; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1057[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1058; + US I1059 :1; + US I368 :15; + RP I1060; + RP I1061; + RP I1062; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1063; + RP I1064; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1065; + RP I1066; + U I1067 :16; + U I1068 :2; + U I1069 :2; + U I1070 :1; + U I1071 :8; + U I368 :3; + U I471; + RP I1072; + RP I811[(5)]; + RP I813[(5)]; + US I1073; + US I1074; + RemoteDbsedLoad I1075[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1077 :1; + U I1078 :1; + U I1079 :2; + U I1080 :1; + U I706 :8; + U I1081 :1; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I368 :13; + RP ptable; + RP I1042; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1077 :1; + U I1078 :1; + U I1079 :2; + U I1080 :1; + U I706 :8; + U I1081 :1; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I368 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1088; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1089; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1091; + U I1077 :1; + U I1078 :1; + U I1079 :2; + U I1080 :1; + U I706 :8; + U I1081 :1; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I368 :13; + RmaSeqPrimOutputOnClkOpt I1088; + RmaSeqPrimOutputEblkData I1092; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1093; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1093; + RP I1094; + RP I1036; + US I706; + UB I977; + UB I1095; + UB I1096; + UB I772; + RP I1097[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1094; + RP I1036; + US I706; + UB I977; + UB I1095; + UB I1096; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1063; +} RmaWakeupListCg; +typedef struct { + RP I1063; +} RmaWakeupArrayCg; +typedef struct { + RP I1063; + RP I1098; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1063; + RP I1098; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1099; + U I706; + RmaTimeStamp I1100[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1101; +} RmaConditionsMdb; +typedef struct { + RP I1102; + RP I1103; + U I1104; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1105; + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1105; + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1116; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1105; + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1116; + RP I1117; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1105; + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1117; + RP I1118; + U I1119; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1034; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1116; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1116; + RP I1117; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1117; + RP I1118; + U I1119; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1117; + RP I1118; + RP I1034; + U I1119; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + RP I1116; + RP I1034; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1106; + RP I721; + U I1107; + scalar I890; + scalar I1108; + US I1109 :1; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :5; + U I1121; + RP I1122; + RP I1123; + RP I1116; + RP I1124; + RP I1125; + RmaTimeStamp I1126; +} RmaTcCoreNochange; +typedef struct { + RP I1127; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1101; + RmaTimeStamp I1128; + scalar I1129; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1101; + RmaTimeStamp I1128; + scalar I1129; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1128; + scalar I1129; + US I890; + RP I1117; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1128; + scalar I1129; + US I890; + RP I1117; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1117; + RP I1130; + U I1119; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1034; + RP I1117; + RP I1130; + U I1119; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1117; + RP I1130; + U I1119; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1131; + U I1132; + FlatNodeNum I1003; + U I914; + U I1133; + U I1134; + RmaIbfPcode I1027; + union { + scalar I1135; + vec32 I1136; + scalar * I1137; + vec32 * I1138; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1139; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1140; + U I1141 :1; + U I1142 :1; + U I1143 :1; + U I1144 :4; + U I368 :25; + U I1145; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1639; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1027; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1146; + scalar val; + scalar I1147 :1; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + U I1152; + RP I811; + RP I1153; + RP I1003; + RP I1154; + RP I1155; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1147; + UB I1156; + UB I977; + RmaNonEdgeLoadData1 * I1057; + RmaNonEdgeLoadData1 * I798; + void * I1157; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1158; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1159; + RP I1003; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1057; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1160; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1161; + UB I1162 :1; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I368 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1166; + UB I1167; + UB I1168; + UB I1169; + U cedges :30; + U I1163 :1; + U I1170 :1; + U I1171; + U I1172; + RP I1173; + RP I1174; + RmaRtlEdgeBlockHdr * I1175; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1176; + RP I1177; + U I1178; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1176; + RP I1179; + RP I1180; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1181; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1182; + EBLK * I1183; + EBLK * I1184; + EBLK * I1185; + struct futq * I1186; + struct futq * I1187; + struct futq * I1188; + struct sched_table * I1189; + struct futq_info * I1191; + struct futq_info * I1193; + U I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + struct millenium * I1201; + EBLK * I1203; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + MPS * I1221; + struct retain_t * I1222; + EBLK * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK I1249; + EBLK * I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + int I1254; + int I1255; + struct vcs_globals_t * I1256; + clock_struct I1257; + unsigned long long I1258; + EBLK * I1259; + EBLK * I1260; + void * I1261; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1262; + int I1263; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1265; + void * I1266; + void * I1267[2]; + void * I1268; +} ClkLevel; +typedef struct { + unsigned long long I1269; + EBLK I1170; + U I1270; + U I1271; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1272; + ClkLevel I1273; + Queue I1274[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_0_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_0_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1302, U did); +void hs_0_M_0_2__simv_daidir (UB * pcode); +void hs_0_M_0_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_1_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_1_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1302, U did); +void hs_0_M_1_2__simv_daidir (UB * pcode); +void hs_0_M_1_11__simv_daidir (UB * pcode, scalar val); +void hsG_0__0 (struct dummyq_struct * I1288, EBLK * I1282, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/sim/csrc/rmapats.m b/sim/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/rmapats.o b/sim/csrc/rmapats.o new file mode 100644 index 0000000..f7e34a8 Binary files /dev/null and b/sim/csrc/rmapats.o differ diff --git a/sim/csrc/rmapats_mop.o b/sim/csrc/rmapats_mop.o new file mode 100644 index 0000000..1a9f8c5 Binary files /dev/null and b/sim/csrc/rmapats_mop.o differ diff --git a/sim/csrc/rmar.c b/sim/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/sim/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/sim/csrc/rmar.h b/sim/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/sim/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/sim/csrc/rmar.o b/sim/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/sim/csrc/rmar.o differ diff --git a/sim/csrc/rmar0.h b/sim/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/sim/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/sim/csrc/rmar_llvm_0_0.o b/sim/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/sim/csrc/rmar_llvm_0_0.o differ diff --git a/sim/csrc/rmar_llvm_0_1.o b/sim/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/sim/csrc/rmar_llvm_0_1.o differ diff --git a/sim/csrc/rmar_nd.o b/sim/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/sim/csrc/rmar_nd.o differ diff --git a/sim/novas.conf b/sim/novas.conf new file mode 100644 index 0000000..33aad78 --- /dev/null +++ b/sim/novas.conf @@ -0,0 +1,20 @@ +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/IPA/sim/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=1280 +Verdi_1\height=921 + +[QwMainWindow] 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+window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xe2\0\0\x4\x1e\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0[\0\0\0\0\0\0\x3\xbd\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xe2\0\0\x4\x1b\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0[\0\0\x3\xbd\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) diff --git a/sim/novas.rc b/sim/novas.rc new file mode 100644 index 0000000..a90cce1 --- /dev/null +++ b/sim/novas.rc @@ -0,0 +1,1369 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/IPA/sim/tb.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[InteractiveDebug] +tbvLocalWatchArrayLimit = 50 +Watch_0 = 150 80 1032 0 +Watch_1 = 150 80 80 948 +Watch_2 = 150 80 80 200 +Watch_3 = 150 80 80 200 +Watch_4 = 150 80 80 200 +Watch_5 = 150 80 80 200 +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +highlightColor = 301,361,675,327 +ActiveFileDialog = 410,388,458,272 +SignalTypeDialog = 365,239,507,391 +importDesignForm = 281,237,715,574 +QwWarnMsgDlg = 330,736,600,250 +openFileDlg = 338,283,602,483 +qWaveSignalDialog = 239,285,800,479 +QwUserAskDlg = 478,459,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/IPA/sim/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +vcs_svOption = -sml=verdi +smartlog = TRUE +[SimulationPlus2] +dumpPowerRoot = FALSE +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +DataViewTooltip = TRUE +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 1280 921 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleInterForm = "share/VIA/Apps/PredefinedRules/UVM_OVM_i_rule.rc" +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.interactiveDebug.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.interactiveDebug.preference.vgifColumnSettingRC] +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0] +parRuleSets = "/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_OVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_UVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRule\ +s/par_rule_LP.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_VCS.rc " +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column1] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.parRule] +parRulePathInterForm = "" +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 239 248 800 479 245 381 505 183 +viewPort = 0 27 1280 816 226 91 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/IPA/sim/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/IPA/sim/tb.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1280 816 226 91 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/sim/novas_dump.log b/sim/novas_dump.log new file mode 100644 index 0000000..faa8081 --- /dev/null +++ b/sim/novas_dump.log @@ -0,0 +1,359 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_thread_id('simv: undefined symbol: vcsd_get_thread_id') +ANF: vcsd_get_power_scope_name('simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vcsd_node_check_native_callback('simv: undefined symbol: vcsd_node_check_native_callback') +ANF: vcsd_node_add_native_callback('simv: undefined symbol: vcsd_node_add_native_callback') +ANF: vcsdIsNativeVc('simv: undefined symbol: vcsdIsNativeVc') +ANF: vhpi_get_cb_info('simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('simv: undefined symbol: msvGetForceStatus') +ANF: vdi_fn_trigger_native_init_force('simv: undefined symbol: vdi_fn_trigger_native_init_force') +ANF: vdi_set_native_callback('simv: undefined symbol: vdi_set_native_callback') +ANF: vdi_fn_check_native_callback('simv: undefined symbol: vdi_fn_check_native_callback') +ANF: vdi_fn_add_native_callback('simv: undefined symbol: vdi_fn_add_native_callback') +ANF: vhdi_dt_get_type('simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: simv + option[1]: +vc + option[2]: +v2k + option[3]: /home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include + option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl + option[20]: -Xvcs_run_simv=1 + option[21]: -timescale=1ns/1ps + option[22]: -full64 + option[23]: +vc + option[24]: +v2k + option[25]: -debug_access+all + option[26]: +vpi + option[27]: +vcsd1 + option[28]: +itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab + option[29]: -picarchive + option[30]: -P + option[31]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[32]: -fsdb + option[33]: -sverilog + option[34]: -gen_obj + option[35]: -f + option[36]: rtl.f + option[37]: -f + option[38]: tb.f + option[39]: -load + option[40]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[41]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-1_Full64 +Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 +CPU cores: 8 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +XDG_SESSION_ID=2 +HOSTNAME=IC_EDA +TERM_PROGRAM=vscode +UNAME=/bin/uname +SELINUX_ROLE_REQUESTED= +SCRNAME=vcs +VCS_DEPTH=0 +SHELL=/bin/bash +TERM=xterm-256color +MAKEFLAGS= +HISTSIZE=1000 +SSH_CLIENT=192.168.223.1 58217 22 +QUESTASIM_HOME=/home/mentor/questasim +SELINUX_USE_CURRENT_RANGE= +TERM_PROGRAM_VERSION=1.85.2 +QTDIR=/usr/lib/qt-3.3 +QTINC=/usr/lib/qt-3.3/include +LC_ALL=C +QT_GRAPHICSSYSTEM_CHECKED=1 +USER=ICer +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib::/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot:/home/cadence/INCISIVE152/tools.lnx86/lib +SCRIPT_NAME=vcs +MAKE_TERMOUT=/dev/pts/1 +VCS_MX_HOME_INTERNAL=1 +DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1 +SNPSLMD_LICENSE_FILE=27000@IC_EDA +MAKELEVEL=1 +OVA_UUM=0 +MFLAGS= +MMSIMHOME=/home/cadence/MMSIM151 +VCS_MODE_FLAG=64 +PATH=.:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/remote-cli:/home/Xilinx/SDK/2019.1/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/Xilinx/Vivado/2019.1/bin:/home/Xilinx/DocNav:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/bin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user:/usr/local/sbin:/usr/sbin:/home/synopsys/fpga/N-2018.03-SP1/bin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/icc2/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs-mx/O-2018.09-1/gui/dve/bin:/home/synopsys/vcs-mx/O-2018.09-1/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/cadence/IC617/tools/dfII/bin:/home/cadence/IC617/tools/plot/bin:/home/cadence/INCISIVE152/tools/bin:/home/cadence/MMSIM151/bin:/home/cadence/MMSIM151/tools/relxpert/bin:/home/cadence/INCISIVE152/bin:/home/cadence/INCISIVE152/tools.lnx86/bin:/home/cadence/INCISIVE152/tools.lnx86/dfII/bin:/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +MAIL=/var/spool/mail/ICer +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189 +PWD=/home/ICer/ic_prjs/IPA/sim +VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1 +MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199 +LANG=zh_CN.UTF-8 +KDEDIRS=/usr +VCS_ARCH_OVERRIDE=linux +VSCODE_GIT_ASKPASS_EXTRA_ARGS= +VMR_MODE_FLAG=64 +SELINUX_LEVEL_REQUESTED= +CDSHOME=/home/cadence/IC617 +XILINX_VIVADO=/home/Xilinx/Vivado/2019.1 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +HISTCONTROL=ignoredups +SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn +VCS_ARG_ADDED_FOR_TMP=1 +SNPS_VCS_TMPDIR=/tmp/vcs_20250826084555_15976 +HOME=/home/ICer +RISCV=/home/Riscv_Tools +SHLVL=7 +VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js +MGC_HOME=/home/mentor/ +ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1 +MGC_LICENSE_FILE=/home/mentor//license/license.dat +CADHOME=/home/cadence +VCS_COM=/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1 +LOGNAME=ICer +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +QTLIB=/usr/lib/qt-3.3/lib +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +MAKE_TERMERR=/dev/pts/1 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +SSH_CONNECTION=192.168.223.1 58217 192.168.223.129 22 +VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock +VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-1591ffa4-a3ad-479f-90eb-871a7ef0f2ac.sock +CDS_LIC_FILE=/home/cadence/license/cadence.dat +SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/ +LESSOPEN=||/usr/bin/lesspipe.sh %s +BROWSER=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/bin/helpers/browser.sh +SCL_HOME=/home/synopsys/scl/2018.06 +sysc_uni_pwd=/home/ICer/ic_prjs/IPA/sim +VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node +GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh +XDG_RUNTIME_DIR=/run/user/1000 +SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1 +VCS_ARCH=linux64 +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64 +INCISIVE_HOME=/home/cadence/INCISIVE152 +COLORTERM=truecolor +_=./simv +OLDPWD=/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_EXEC_DONE=1 +DVE=/home/synopsys/vcs-mx/O-2018.09-1/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=simv +argv[1]=+vc +argv[2]=+v2k +273 profile - 100 + CPU/Mem usage: 0.080 sys, 0.480 user, 245.62M mem +274 Tue Aug 26 16:45:57 2025 +275 pliAppInit +276 FSDB_GATE is set. +277 FSDB_RTL is set. +278 Enable Parallel Dumping. +279 pliAppMiscSet: New Sim Round +280 pliEntryInit +281 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +282 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +283 (C) 1996 - 2019 by Synopsys, Inc. +284 sps_call_fsdbDumpfile_main at 0 : ../tb/data_cache/tb_data_cache.v(166) +285 argv[0]: (tb.fsdb) +286 *Verdi* : Create FSDB file 'tb.fsdb' +287 compile option from '/home/ICer/ic_prjs/IPA/sim/simv.daidir/vcs_rebuild'. +288 "vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1" +289 FSDB_VCS_ENABLE_FAST_VC is enable +290 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/data_cache/tb_data_cache.v(167) +291 argv[0]: (0) +292 argv[1]: (handle) tb_data_cache +293 [spi_vcs_vd_ppi_create_root]: no upf option +294 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +295 *Verdi* : Begin traversing the scope (tb_data_cache), layer (0). +296 *Verdi* : End of traversing. +297 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.130 sys, 0.490 user, 340.83M mem + incr: 0.010 sys, 0.010 user, 7.38M mem + accu: 0.010 sys, 0.010 user, 7.38M mem + accu incr: 0.010 sys, 0.010 user, 7.38M mem + + Count usage: 258 var, 214 idcode, 106 callback + incr: 258 var, 214 idcode, 106 callback + accu: 258 var, 214 idcode, 106 callback + accu incr: 258 var, 214 idcode, 106 callback +298 Tue Aug 26 16:45:57 2025 +299 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.130 sys, 0.490 user, 341.88M mem + incr: 0.000 sys, 0.000 user, 1.05M mem + accu: 0.010 sys, 0.010 user, 8.43M mem + accu incr: 0.000 sys, 0.000 user, 1.05M mem + + Count usage: 258 var, 214 idcode, 106 callback + incr: 0 var, 0 idcode, 0 callback + accu: 258 var, 214 idcode, 106 callback + accu incr: 0 var, 0 idcode, 0 callback +300 Tue Aug 26 16:45:57 2025 +301 sps_call_fsdbDumpMDA_vd_main at 0 : ../tb/data_cache/tb_data_cache.v(168) +302 argv[0]: (0) +303 argv[1]: (handle) tb_data_cache +304 *Verdi* : Begin traversing the MDAs under scope (tb_data_cache), layer (0). +305 *Verdi* : Enable +mda and +packedmda dumping. +306 *Verdi* : End of traversing the MDAs. +307 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.140 sys, 0.490 user, 341.88M mem + incr: 0.010 sys, 0.000 user, 0.00M mem + accu: 0.010 sys, 0.000 user, 0.00M mem + accu incr: 0.010 sys, 0.000 user, 0.00M mem + + Count usage: 4098 var, 4054 idcode, 111 callback + incr: 3840 var, 3840 idcode, 5 callback + accu: 3840 var, 3840 idcode, 5 callback + accu incr: 3840 var, 3840 idcode, 5 callback +308 Tue Aug 26 16:45:57 2025 +309 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.140 sys, 0.490 user, 342.16M mem + incr: 0.000 sys, 0.000 user, 0.28M mem + accu: 0.010 sys, 0.000 user, 0.28M mem + accu incr: 0.000 sys, 0.000 user, 0.28M mem + + Count usage: 4098 var, 4054 idcode, 111 callback + incr: 0 var, 0 idcode, 0 callback + accu: 3840 var, 3840 idcode, 5 callback + accu incr: 0 var, 0 idcode, 0 callback +310 Tue Aug 26 16:45:57 2025 +311 End of simulation at 36076000 +312 Tue Aug 26 16:45:57 2025 +313 Begin FSDB profile info: +314 FSDB Writer : bc1(35379) bcn(99202) mtf/stf(0/0) +FSDB Writer elapsed time : flush(0.033912) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +315 End FSDB profile info +316 Parallel profile - Flush:4 Expand:0 ProduceWait:0 ConsumerWait:1 BlockUsed:2 +317 ProduceTime:0.730205081 ConsumerTime:0.021449033 Buffer:64MB +318 SimExit +319 Sim process exit diff --git a/sim/rtl.f b/sim/rtl.f new file mode 100644 index 0000000..3610372 --- /dev/null +++ b/sim/rtl.f @@ -0,0 +1,7 @@ +../rtl/data_cache/sync_fifo.v +../rtl/data_cache/async_fifo.v +../rtl/data_cache/histogram_ctrl.v +../rtl/data_cache/data_assemble.v +../rtl/data_cache/axi_write_ctrl.v +../rtl/data_cache/rst_sync.v +../rtl/data_cache/data_cache.v diff --git a/sim/simv b/sim/simv new file mode 100755 index 0000000..968a74f Binary files /dev/null and b/sim/simv differ diff --git a/sim/simv.daidir/.daidir_complete b/sim/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/.normal_done b/sim/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/.vcs.timestamp b/sim/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..f253175 --- /dev/null +++ b/sim/simv.daidir/.vcs.timestamp @@ -0,0 +1,129 @@ +0 +34 ++itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab ++v2k ++vc ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so +-Mout=simv +-Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include +-P +-Xvcs_run_simv=1 +-debug_access+all +-f rtl.f +-f tb.f +-fsdb +-full64 +-gen_obj +-picarchive +-sverilog +-timescale=1ns/1ps +/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1 +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +71 +sysc_uni_pwd=/home/ICer/ic_prjs/IPA/sim +XILINX_VIVADO=/home/Xilinx/Vivado/2019.1 +XDG_SESSION_ID=2 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-1591ffa4-a3ad-479f-90eb-871a7ef0f2ac.sock +VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock +VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node +VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js +VSCODE_GIT_ASKPASS_EXTRA_ARGS= +VMR_MODE_FLAG=64 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +VCS_MX_HOME_INTERNAL=1 +VCS_MODE_FLAG=64 +VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH_OVERRIDE=linux +VCS_ARCH=linux64 +UNAME=/bin/uname +TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64 +TERM_PROGRAM_VERSION=1.85.2 +TERM_PROGRAM=vscode +SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1 +SSH_CONNECTION=192.168.223.1 58217 192.168.223.129 22 +SSH_CLIENT=192.168.223.1 58217 22 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn +SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/ +SELINUX_USE_CURRENT_RANGE= +SELINUX_ROLE_REQUESTED= +SELINUX_LEVEL_REQUESTED= +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/home/synopsys/scl/2018.06 +RISCV=/home/Riscv_Tools +QUESTASIM_HOME=/home/mentor/questasim +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib/qt-3.3/lib +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +MMSIMHOME=/home/cadence/MMSIM151 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +MGC_LICENSE_FILE=/home/mentor//license/license.dat +MGC_HOME=/home/mentor/ +MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199 +MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189 +MFLAGS= +MAKE_TERMOUT=/dev/pts/1 +MAKE_TERMERR=/dev/pts/1 +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +KDEDIRS=/usr +INCISIVE_HOME=/home/cadence/INCISIVE152 +ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1 +HISTCONTROL=ignoredups +GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh +DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +COLORTERM=truecolor +CDS_LIC_FILE=/home/cadence/license/cadence.dat +CDSHOME=/home/cadence/IC617 +CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27 +CADHOME=/home/cadence +0 +12 +1756197905 ../tb/data_cache/tb_data_cache.v +1756194528 ../rtl/data_cache/data_cache.v +1756115099 ../rtl/data_cache/rst_sync.v +1756112329 ../rtl/data_cache/axi_write_ctrl.v +1756197232 ../rtl/data_cache/data_assemble.v +1756109175 ../rtl/data_cache/histogram_ctrl.v +1756107950 ../rtl/data_cache/async_fifo.v +1756106550 ../rtl/data_cache/sync_fifo.v +1756197951 tb.f +1756197943 rtl.f +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab +4 +1539402341 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so +1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so +1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so +1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so +1756197957 simv.daidir +-1 partitionlib diff --git a/sim/simv.daidir/_16331_archive_1.so b/sim/simv.daidir/_16331_archive_1.so new file mode 100755 index 0000000..fdea62e Binary files /dev/null and b/sim/simv.daidir/_16331_archive_1.so differ diff --git a/sim/simv.daidir/binmap.sdb b/sim/simv.daidir/binmap.sdb new file mode 100644 index 0000000..7b94165 Binary files /dev/null and b/sim/simv.daidir/binmap.sdb differ diff --git a/sim/simv.daidir/build_db b/sim/simv.daidir/build_db new file mode 100755 index 0000000..ad40996 --- /dev/null +++ b/sim/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1 diff --git a/sim/simv.daidir/cc/cc_bcode.db b/sim/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..bb33670 --- /dev/null +++ b/sim/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,7 @@ +sid tb_data_cache +bcid 0 0 WIDTH,4 OPT_CONST,0 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU CALL_ARG_VAL,4,0 NOT OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,1 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,26 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,2 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,16 CALL_ARG_VAL,8,0 CALL_ARG_VAL,9,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,3 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,3 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 NOT AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,4 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,5 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,13,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 OPT_CONST,5 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 1 1 WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OR OR OPT_CONST,1 EQU WIDTH,2 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,4 PAD OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 NOT AND AND RET +bcid 3 3 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,11 SHIFT_R XOR RET +bcid 4 4 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,1 M_EQU AND RET +bcid 5 5 WIDTH,12 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET diff --git a/sim/simv.daidir/cc/cc_dummy_file b/sim/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/sim/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/sim/simv.daidir/cgname.json b/sim/simv.daidir/cgname.json new file mode 100644 index 0000000..bb7d63d --- /dev/null +++ b/sim/simv.daidir/cgname.json @@ -0,0 +1,20 @@ +{ + "std": [ + "std", + "reYIK", + "module", + 1 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 3 + ], + "tb_data_cache": [ + "tb_data_cache", + "EULYA", + "module", + 2 + ] +} \ No newline at end of file diff --git a/sim/simv.daidir/covg_defs b/sim/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/.version b/sim/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..84cd60b --- /dev/null +++ b/sim/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-1_Full64 +Build Date = Oct 12 2018 20:38:10 +RedHat +Compile Location: /home/ICer/ic_prjs/IPA/sim diff --git a/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..d9ae5c9 Binary files /dev/null and b/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb b/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..9447455 Binary files /dev/null and b/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/sim/simv.daidir/debug_dump/dumpcheck.db b/sim/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/dve_debug.db.gz b/sim/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..2c58f91 Binary files /dev/null and b/sim/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100755 index 0000000..e30d318 --- /dev/null +++ b/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/home/synopsys/vcs-mx/O-2018.09-1/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_s87tOh.xml.gz" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db b/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100755 index 0000000..a71e3af --- /dev/null +++ b/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../.. +fi + +if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/sim/simv.daidir/debug_dump/fsearch/fsearch.stat b/sim/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz b/sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz new file mode 100644 index 0000000..6642cf1 Binary files /dev/null and b/sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz differ diff --git a/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..ef8e3f2 Binary files /dev/null and b/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/sim/simv.daidir/debug_dump/src_files_verilog b/sim/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..d492397 --- /dev/null +++ b/sim/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,8 @@ +/home/ICer/ic_prjs/IPA/rtl/data_cache/async_fifo.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/axi_write_ctrl.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/data_assemble.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/data_cache.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/histogram_ctrl.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/rst_sync.v +/home/ICer/ic_prjs/IPA/rtl/data_cache/sync_fifo.v +/home/ICer/ic_prjs/IPA/tb/data_cache/tb_data_cache.v diff --git a/sim/simv.daidir/debug_dump/topmodules b/sim/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..c357eb2 --- /dev/null +++ b/sim/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +Ed \ No newline at end of file diff --git a/sim/simv.daidir/debug_dump/vir.sdb b/sim/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..03664cd Binary files /dev/null and b/sim/simv.daidir/debug_dump/vir.sdb differ diff --git a/sim/simv.daidir/eblklvl.db b/sim/simv.daidir/eblklvl.db new file mode 100644 index 0000000..4ac5fc6 Binary files /dev/null and b/sim/simv.daidir/eblklvl.db differ diff --git a/sim/simv.daidir/elabmoddb.sdb b/sim/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..635b558 Binary files /dev/null and b/sim/simv.daidir/elabmoddb.sdb differ diff --git a/sim/simv.daidir/external_functions b/sim/simv.daidir/external_functions new file mode 100644 index 0000000..14a367b --- /dev/null +++ b/sim/simv.daidir/external_functions @@ -0,0 +1,78 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/sim/simv.daidir/hslevel_callgraph.sdb b/sim/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..59498f3 Binary files /dev/null and b/sim/simv.daidir/hslevel_callgraph.sdb differ diff --git a/sim/simv.daidir/hslevel_level.sdb b/sim/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..661ac66 Binary files /dev/null and b/sim/simv.daidir/hslevel_level.sdb differ diff --git a/sim/simv.daidir/hslevel_rtime_level.sdb b/sim/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..f6e4a9c Binary files /dev/null and b/sim/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/sim/simv.daidir/hsscan_cfg.dat b/sim/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/nsparam.dat b/sim/simv.daidir/nsparam.dat new file mode 100644 index 0000000..1c1eb11 Binary files /dev/null and b/sim/simv.daidir/nsparam.dat differ diff --git a/sim/simv.daidir/pcc.sdb b/sim/simv.daidir/pcc.sdb new file mode 100644 index 0000000..acee64e Binary files /dev/null and b/sim/simv.daidir/pcc.sdb differ diff --git a/sim/simv.daidir/pcxpxmr.dat b/sim/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..229151a Binary files /dev/null and b/sim/simv.daidir/pcxpxmr.dat differ diff --git a/sim/simv.daidir/prof.sdb b/sim/simv.daidir/prof.sdb new file mode 100644 index 0000000..a8a5605 Binary files /dev/null and b/sim/simv.daidir/prof.sdb differ diff --git a/sim/simv.daidir/rmapats.dat b/sim/simv.daidir/rmapats.dat new file mode 100644 index 0000000..a07d84c Binary files /dev/null and b/sim/simv.daidir/rmapats.dat differ diff --git a/sim/simv.daidir/rmapats.so b/sim/simv.daidir/rmapats.so new file mode 100755 index 0000000..86b5f9a Binary files /dev/null and b/sim/simv.daidir/rmapats.so differ diff --git a/sim/simv.daidir/saifNetInfo.db b/sim/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..573541a --- /dev/null +++ b/sim/simv.daidir/saifNetInfo.db @@ -0,0 +1 @@ +0 diff --git a/sim/simv.daidir/simv.kdb b/sim/simv.daidir/simv.kdb new file mode 100644 index 0000000..ed30022 --- /dev/null +++ b/sim/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/ICer/ic_prjs/IPA/sim +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=tb_data_cache +OPTION=-ssv -ssy +ELAB_OPTION=-ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/sim/simv.daidir/stitch_nsparam.dat b/sim/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/sim/simv.daidir/stitch_nsparam.dat differ diff --git a/sim/simv.daidir/tt.sdb b/sim/simv.daidir/tt.sdb new file mode 100644 index 0000000..f064caa Binary files /dev/null and b/sim/simv.daidir/tt.sdb differ diff --git a/sim/simv.daidir/vcs_rebuild b/sim/simv.daidir/vcs_rebuild new file mode 100755 index 0000000..f755ff8 --- /dev/null +++ b/sim/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1 diff --git a/sim/simv.daidir/vcselab_master_hsim_elabout.db b/sim/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..ebd1e76 --- /dev/null +++ b/sim/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,673 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 61 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 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+fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 0 +fHsimCoverageOptions 0 +fHsimCoverageDir NULL diff --git a/sim/simv.daidir/vcselab_misc_hsim_fegate.db b/sim/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..dca7e28 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/sim/simv.daidir/vcselab_misc_hsim_lvl.db b/sim/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..719a279 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/sim/simv.daidir/vcselab_misc_hsim_name.db b/sim/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..8cc11e0 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/sim/simv.daidir/vcselab_misc_hsim_uds.db b/sim/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..311d7af --- /dev/null +++ b/sim/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,3 @@ +vcselab_misc_midd.db 749 +vcselab_misc_mnmn.db 26 +vcselab_misc_hsim_name.db 217 diff --git a/sim/simv.daidir/vcselab_misc_midd.db b/sim/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..528ffbb Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_midd.db differ diff --git a/sim/simv.daidir/vcselab_misc_mnmn.db b/sim/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..b330718 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/sim/simv.daidir/vcselab_misc_partition.db b/sim/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..a453c68 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_partition.db differ diff --git a/sim/simv.daidir/vcselab_misc_vcselabref.db b/sim/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/sim/simv.daidir/vcselab_misc_vpdnodenums b/sim/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..88fcc28 Binary files /dev/null and b/sim/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/sim/tb.f b/sim/tb.f new file mode 100644 index 0000000..96cda98 --- /dev/null +++ b/sim/tb.f @@ -0,0 +1,5 @@ +// ../tb/data_cache/tb_sync_fifo.v +// ../tb/data_cache/tb_histogram_ctrl.v +// ../tb/data_cache/tb_data_assemble.v +// ../tb/data_cache/tb_axi_write_ctrl.v +../tb/data_cache/tb_data_cache.v diff --git a/sim/tb.fsdb b/sim/tb.fsdb new file mode 100644 index 0000000..c973637 Binary files /dev/null and b/sim/tb.fsdb differ diff --git a/sim/ucli.key b/sim/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/sim/vcs.log b/sim/vcs.log new file mode 100644 index 0000000..8b422e4 --- /dev/null +++ b/sim/vcs.log @@ -0,0 +1,201 @@ + Chronologic VCS (TM) + Version O-2018.09-1_Full64 -- Tue Aug 26 16:45:55 2025 + Copyright (c) 1991-2018 by Synopsys Inc. + ALL RIGHTS RESERVED + +This program is proprietary and confidential information of Synopsys Inc. +and may be used and disclosed only as authorized in a license agreement +controlling such use and disclosure. + +Parsing design file '../rtl/data_cache/sync_fifo.v' +Parsing design file '../rtl/data_cache/async_fifo.v' +Parsing design file '../rtl/data_cache/histogram_ctrl.v' +Parsing design file '../rtl/data_cache/data_assemble.v' +Parsing design file '../rtl/data_cache/axi_write_ctrl.v' +Parsing design file '../rtl/data_cache/rst_sync.v' +Parsing design file '../rtl/data_cache/data_cache.v' +Parsing design file '../tb/data_cache/tb_data_cache.v' +Top Level Modules: + tb_data_cache +TimeScale is 1 ns / 1 ps + +Warning-[PCWM-W] Port connection width mismatch +../rtl/data_cache/data_cache.v, 245 +"axi_write_ctrl #(AXI_ID_W, AXI_ADDR_W, AXI_DATA_W, AXI_STRB_W, , , , ) u_axi_write_ctrl( .clk (clk), .rst_n (rst_n_sys), .start_en (((!sync_fifo_empty) && (!axi_write_busy))), .sram_base_addr (32'b0), .fifo_rd_data (sync_fifo_rd_data), .fifo_empty (sync_fifo_empty), .fifo_rd_en (sync_fifo_rd_en), .axi_m_awid (axi_m_awid), .axi_m_awaddr (axi_m_awaddr), .axi_m_awlen (axi_m_awlen), .axi_m_awsize (axi_m_awsize), .axi_m_awburst (axi_m_awburst), .axi_m_awlock (axi_m_awlock), .axi_m_awcache (axi_m_awcache), .axi_m_awprot (axi_m_awprot), .axi_m_awqos (axi_m_awqos), .axi_m_awvalid (axi_m_awvalid), .axi_m_awready (axi_m_awready), .axi_m_wid (axi_m_wid), .axi_m_wdata (axi_m_wdata), .axi_m_wstrb (axi_m_wstrb), .axi_m_wlast (axi_m_wlast), .axi_ ... " + The following 4-bit expression is connected to 5-bit port "axi_m_awcache" of + module "axi_write_ctrl", instance "u_axi_write_ctrl". + Expression: axi_m_awcache + use +lint=PCWM for more details + + +Warning-[PCWM-W] Port connection width mismatch +../rtl/data_cache/data_cache.v, 245 +"axi_write_ctrl #(AXI_ID_W, AXI_ADDR_W, AXI_DATA_W, AXI_STRB_W, , , , ) u_axi_write_ctrl( .clk (clk), .rst_n (rst_n_sys), .start_en (((!sync_fifo_empty) && (!axi_write_busy))), .sram_base_addr (32'b0), .fifo_rd_data (sync_fifo_rd_data), .fifo_empty (sync_fifo_empty), .fifo_rd_en (sync_fifo_rd_en), .axi_m_awid (axi_m_awid), .axi_m_awaddr (axi_m_awaddr), .axi_m_awlen (axi_m_awlen), .axi_m_awsize (axi_m_awsize), .axi_m_awburst (axi_m_awburst), .axi_m_awlock (axi_m_awlock), .axi_m_awcache (axi_m_awcache), .axi_m_awprot (axi_m_awprot), .axi_m_awqos (axi_m_awqos), .axi_m_awvalid (axi_m_awvalid), .axi_m_awready (axi_m_awready), .axi_m_wid (axi_m_wid), .axi_m_wdata (axi_m_wdata), .axi_m_wstrb (axi_m_wstrb), .axi_m_wlast (axi_m_wlast), .axi_ ... " + The following 4-bit expression is connected to 5-bit port "axi_m_awqos" of + module "axi_write_ctrl", instance "u_axi_write_ctrl". + Expression: axi_m_awqos + use +lint=PCWM for more details + +Starting vcs inline pass... +1 module and 0 UDP read. +recompiling module tb_data_cache +make[1]: Entering directory '/home/ICer/ic_prjs/IPA/sim/csrc' +make[1]: Leaving directory '/home/ICer/ic_prjs/IPA/sim/csrc' +make[1]: Entering directory '/home/ICer/ic_prjs/IPA/sim/csrc' +rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so +if [ -x ../simv ]; then chmod -x ../simv; fi +g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _16331_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl +../simv up to date +make[1]: Leaving directory '/home/ICer/ic_prjs/IPA/sim/csrc' +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 26 16:45 2025 +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* : Create FSDB file 'tb.fsdb' +*Verdi* : Begin traversing the scope (tb_data_cache), layer (0). +*Verdi* : End of traversing. +*Verdi* : Begin traversing the MDAs under scope (tb_data_cache), layer (0). +*Verdi* : Enable +mda and +packedmda dumping. +*Verdi* : End of traversing the MDAs. +[150000] Test 1: Gray scale single frame test +[165000] Data Cache State: WAIT_VS +[185000] Data Cache State: RECEIVE_DATA +[595000] AXI Write Transaction: Address=0x00000000, Length= 0 +[605000] AXI Write Transaction: Address=0x00000000, Length= 0 +[615000] AXI Write Data: ID= 0, Data[31:0]=0x3c3d3e3f, Last=1 +[935000] AXI Write Transaction: Address=0x00000020, Length= 0 +[955000] AXI Write Data: ID= 0, Data[31:0]=0x5c5d5e5f, Last=1 +[1285000] AXI Write Transaction: Address=0x00000040, Length= 0 +[1295000] AXI Write Transaction: Address=0x00000040, Length= 0 +[1305000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 +[1635000] AXI Write Transaction: Address=0x00000060, Length= 0 +[1655000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 +[1985000] AXI Write Transaction: Address=0x00000080, Length= 0 +[2015000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 +[2335000] AXI Write Transaction: Address=0x000000a0, Length= 0 +[2345000] AXI Write Transaction: Address=0x000000a0, Length= 0 +[2355000] AXI Write Data: ID= 0, Data[31:0]=0x3b3c3d3e, Last=1 +[2715000] AXI Write Transaction: Address=0x000000c0, Length= 0 +[2735000] AXI Write Data: ID= 0, Data[31:0]=0x5b5c5d5e, Last=1 +[3035000] AXI Write Transaction: Address=0x000000e0, Length= 0 +[3045000] AXI Write Transaction: Address=0x000000e0, Length= 0 +[3065000] AXI Write Data: ID= 0, Data[31:0]=0x7b7c7d7e, Last=1 +[3385000] AXI Write Transaction: Address=0x00000100, Length= 0 +[3435000] AXI Write Data: ID= 0, Data[31:0]=0x9b9c9d9e, Last=1 +[3745000] AXI Write Transaction: Address=0x00000120, Length= 0 +[3755000] AXI Write Transaction: Address=0x00000120, Length= 0 +[3805000] AXI Write Data: ID= 0, Data[31:0]=0xbbbcbdbe, Last=1 +[4085000] AXI Write Transaction: Address=0x00000140, Length= 0 +[4095000] AXI Write Transaction: Address=0x00000140, Length= 0 +[4125000] AXI Write Data: ID= 0, Data[31:0]=0x3a3b3c3d, Last=1 +[4435000] AXI Write Transaction: Address=0x00000160, Length= 0 +[4455000] AXI Write Data: ID= 0, Data[31:0]=0x5a5b5c5d, Last=1 +[4795000] AXI Write Transaction: Address=0x00000180, Length= 0 +[4805000] AXI Write Transaction: Address=0x00000180, Length= 0 +[4815000] AXI Write Data: ID= 0, Data[31:0]=0x7a7b7c7d, Last=1 +[5135000] AXI Write Transaction: Address=0x000001a0, Length= 0 +[5155000] AXI Write Data: ID= 0, Data[31:0]=0x9a9b9c9d, Last=1 +[5515000] AXI Write Transaction: Address=0x000001c0, Length= 0 +[5525000] AXI Write Transaction: Address=0x000001c0, Length= 0 +[5545000] AXI Write Data: ID= 0, Data[31:0]=0xbabbbcbd, Last=1 +[5785000] Data Cache State: WRITE_FIFO +[5795000] Data Cache State: FRAME_DONE +[5835000] AXI Write Transaction: Address=0x000001e0, Length= 0 +[5845000] AXI Write Transaction: Address=0x000001e0, Length= 0 +[5865000] AXI Write Data: ID= 0, Data[31:0]=0x393a3b3c, Last=1 +[8375000] Data Cache State: WAIT_VS +[8455000] Test 1 Histogram Check: CH0 min=20 (exp=20), max=c0 (exp=c0) +[8455000] Test 1 Histogram Check PASSED! +[8505000] Test 2: RGB single frame test +[8515000] Data Cache State: IDLE +[8535000] Data Cache State: WAIT_VS +[8565000] Data Cache State: RECEIVE_DATA +[14165000] Data Cache State: WRITE_FIFO +[14175000] Data Cache State: FRAME_DONE +[16755000] Data Cache State: WAIT_VS +[16835000] Test 2 Histogram Check: CH0 min=37 (exp=30), max=3f (exp=70) +[16835000] Test 2 Histogram Check: CH1 min=50 (exp=50), max=6f (exp=90) +[16835000] Test 2 Histogram Check: CH2 min=78 (exp=70), max=9e (exp=b0) +[16835000] Test 2 Histogram Check FAILED! +[16885000] Test 3: Continuous frame test +[16895000] Data Cache State: IDLE +[16915000] Data Cache State: WAIT_VS +[16945000] Data Cache State: RECEIVE_DATA +[17345000] AXI Write Transaction: Address=0x00000200, Length= 0 +[17415000] AXI Write Data: ID= 0, Data[31:0]=0x5c5d5e5f, Last=1 +[17695000] AXI Write Transaction: Address=0x00000220, Length= 0 +[17705000] AXI Write Transaction: Address=0x00000220, Length= 0 +[17725000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 +[18065000] AXI Write Transaction: Address=0x00000240, Length= 0 +[18075000] AXI Write Transaction: Address=0x00000240, Length= 0 +[18085000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 +[18395000] AXI Write Transaction: Address=0x00000260, Length= 0 +[18405000] AXI Write Transaction: Address=0x00000260, Length= 0 +[18435000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 +[18765000] AXI Write Transaction: Address=0x00000280, Length= 0 +[18775000] AXI Write Transaction: Address=0x00000280, Length= 0 +[18795000] AXI Write Data: ID= 0, Data[31:0]=0xdcdddedf, Last=1 +[19115000] AXI Write Transaction: Address=0x000002a0, Length= 0 +[19135000] AXI Write Data: ID= 0, Data[31:0]=0x5b5c5d5e, Last=1 +[19445000] AXI Write Transaction: Address=0x000002c0, Length= 0 +[19455000] AXI Write Transaction: Address=0x000002c0, Length= 0 +[19465000] AXI Write Data: ID= 0, Data[31:0]=0x7b7c7d7e, Last=1 +[19825000] AXI Write Transaction: Address=0x000002e0, Length= 0 +[19845000] AXI Write Data: ID= 0, Data[31:0]=0x9b9c9d9e, Last=1 +[20175000] AXI Write Transaction: Address=0x00000300, Length= 0 +[20185000] AXI Write Transaction: Address=0x00000300, Length= 0 +[20215000] AXI Write Data: ID= 0, Data[31:0]=0xbbbcbdbe, Last=1 +[20525000] AXI Write Transaction: Address=0x00000320, Length= 0 +[20545000] AXI Write Data: ID= 0, Data[31:0]=0xdbdcddde, Last=1 +[20865000] AXI Write Transaction: Address=0x00000340, Length= 0 +[20885000] AXI Write Data: ID= 0, Data[31:0]=0x5a5b5c5d, Last=1 +[21225000] AXI Write Transaction: Address=0x00000360, Length= 0 +[21265000] AXI Write Data: ID= 0, Data[31:0]=0x7a7b7c7d, Last=1 +[21545000] AXI Write Transaction: Address=0x00000380, Length= 0 +[21565000] AXI Write Data: ID= 0, Data[31:0]=0x9a9b9c9d, Last=1 +[21915000] AXI Write Transaction: Address=0x000003a0, Length= 0 +[21925000] AXI Write Transaction: Address=0x000003a0, Length= 0 +[21935000] AXI Write Data: ID= 0, Data[31:0]=0xbabbbcbd, Last=1 +[22255000] AXI Write Transaction: Address=0x000003c0, Length= 0 +[22265000] AXI Write Transaction: Address=0x000003c0, Length= 0 +[22305000] AXI Write Data: ID= 0, Data[31:0]=0xdadbdcdd, Last=1 +[22545000] Data Cache State: WRITE_FIFO +[22555000] Data Cache State: FRAME_DONE +[22615000] AXI Write Transaction: Address=0x000003e0, Length= 0 +[22635000] AXI Write Data: ID= 0, Data[31:0]=0x595a5b5c, Last=1 +[25135000] Data Cache State: WAIT_VS +[25185000] Data Cache State: RECEIVE_DATA +[30785000] Data Cache State: WRITE_FIFO +[30795000] Data Cache State: FRAME_DONE +[33375000] Data Cache State: WAIT_VS +[33455000] Test 4: Update trigger test +[33475000] Data Cache State: RECEIVE_DATA +[33885000] AXI Write Transaction: Address=0x00000400, Length= 0 +[33905000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 +[34225000] AXI Write Transaction: Address=0x00000420, Length= 0 +[34255000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 +[34585000] AXI Write Transaction: Address=0x00000440, Length= 0 +[34625000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 +[34945000] AXI Write Transaction: Address=0x00000460, Length= 0 +[34955000] AXI Write Transaction: Address=0x00000460, Length= 0 +[34965000] AXI Write Data: ID= 0, Data[31:0]=0xdcdddedf, Last=1 +[35275000] AXI Write Transaction: Address=0x00000480, Length= 0 +[35285000] AXI Write Transaction: Address=0x00000480, Length= 0 +[35295000] AXI Write Data: ID= 0, Data[31:0]=0xfcfdfeff, Last=1 +[35625000] AXI Write Transaction: Address=0x000004a0, Length= 0 +[35645000] AXI Write Data: ID= 0, Data[31:0]=0x1c1d1e1f, Last=1 +[35945000] Data Cache State: IDLE +[35985000] AXI Write Transaction: Address=0x000004c0, Length= 0 +[35995000] AXI Write Transaction: Address=0x000004c0, Length= 0 +[35995000] Data Cache State: WAIT_VS +[36015000] AXI Write Data: ID= 0, Data[31:0]=0x3c3d3e3f, Last=1 +[36076000] All tests completed! +$finish called from file "../tb/data_cache/tb_data_cache.v", line 418. +$finish at simulation time 36076000 + V C S S i m u l a t i o n R e p o r t +Time: 36076000 ps +CPU Time: 0.740 seconds; Data structure size: 0.0Mb +Tue Aug 26 16:45:57 2025 +CPU time: .528 seconds to compile + .347 seconds to elab + .349 seconds to link + .789 seconds in simulation diff --git a/sim/verdiLog/.16693IC_EDA.conf b/sim/verdiLog/.16693IC_EDA.conf new file mode 100644 index 0000000..c7bcb5a --- /dev/null +++ b/sim/verdiLog/.16693IC_EDA.conf @@ -0,0 +1,336 @@ +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/IPA/sim/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=1280 +Verdi_1\height=921 + +[QwMainWindow] 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+Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(1280 921) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=0 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=0 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=1280 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=921 diff --git a/sim/verdiLog/.diagnose.oneSearch b/sim/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/ToNetlist.log b/sim/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/compiler.log b/sim/verdiLog/compiler.log new file mode 100644 index 0000000..a8a917e --- /dev/null +++ b/sim/verdiLog/compiler.log @@ -0,0 +1,107 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -f rtl.f + ../rtl/data_cache/sync_fifo.v + ../rtl/data_cache/async_fifo.v + ../rtl/data_cache/histogram_ctrl.v + ../rtl/data_cache/data_assemble.v + ../rtl/data_cache/axi_write_ctrl.v + ../rtl/data_cache/rst_sync.v + ../rtl/data_cache/data_cache.v + tb.f + + +*Error* nonconstant index +"../rtl/data_cache/async_fifo.v", 79: + +*Error* nonconstant index +"../rtl/data_cache/async_fifo.v", 80: + +*Error* nonconstant index +"../rtl/data_cache/async_fifo.v", 82: + +*Error* nonconstant index +"../rtl/data_cache/async_fifo.v", 83: + +*Error* Syntax error at . +"tb.f", 5: +Highest level modules: +data_cache + + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch0' +"../rtl/data_cache/data_cache.v", 198: + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch0' +"../rtl/data_cache/data_cache.v", 199: + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch1' +"../rtl/data_cache/data_cache.v", 200: + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch1' +"../rtl/data_cache/data_cache.v", 201: + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_min_ch2' +"../rtl/data_cache/data_cache.v", 202: + +*Error* illegal output port on instance 'u_histogram_ctrl' port 'dwidth_conv_max_ch2' +"../rtl/data_cache/data_cache.v", 203: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awid' +"../rtl/data_cache/data_cache.v", 253: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awaddr' +"../rtl/data_cache/data_cache.v", 254: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awlen' +"../rtl/data_cache/data_cache.v", 255: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awsize' +"../rtl/data_cache/data_cache.v", 256: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awburst' +"../rtl/data_cache/data_cache.v", 257: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awlock' +"../rtl/data_cache/data_cache.v", 258: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awcache' +"../rtl/data_cache/data_cache.v", 259: + +*Warning* port sizes differ (5 vs 4) in port connection (port axi_m_awcache) +"../rtl/data_cache/data_cache.v", 259: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awprot' +"../rtl/data_cache/data_cache.v", 260: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awqos' +"../rtl/data_cache/data_cache.v", 261: + +*Warning* port sizes differ (5 vs 4) in port connection (port axi_m_awqos) +"../rtl/data_cache/data_cache.v", 261: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_awvalid' +"../rtl/data_cache/data_cache.v", 262: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wid' +"../rtl/data_cache/data_cache.v", 264: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wdata' +"../rtl/data_cache/data_cache.v", 265: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wstrb' +"../rtl/data_cache/data_cache.v", 266: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wlast' +"../rtl/data_cache/data_cache.v", 267: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_wvalid' +"../rtl/data_cache/data_cache.v", 268: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_m_bready' +"../rtl/data_cache/data_cache.v", 273: + +*Error* illegal output port on instance 'u_axi_write_ctrl' port 'axi_busy' +"../rtl/data_cache/data_cache.v", 274: +Total 28 error(s), 2 warning(s) diff --git a/sim/verdiLog/exe.log b/sim/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/novas.log b/sim/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/sim/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/sim/verdiLog/novas.rc b/sim/verdiLog/novas.rc new file mode 100644 index 0000000..c9dcadb --- /dev/null +++ b/sim/verdiLog/novas.rc @@ -0,0 +1,1369 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/IPA/sim/tb.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[InteractiveDebug] +tbvLocalWatchArrayLimit = 50 +Watch_0 = 150 80 1032 0 +Watch_1 = 150 80 80 948 +Watch_2 = 150 80 80 200 +Watch_3 = 150 80 80 200 +Watch_4 = 150 80 80 200 +Watch_5 = 150 80 80 200 +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +highlightColor = 301,361,675,327 +ActiveFileDialog = 410,388,458,272 +SignalTypeDialog = 365,239,507,391 +importDesignForm = 281,237,715,574 +QwWarnMsgDlg = 330,736,600,250 +openFileDlg = 338,283,602,483 +qWaveSignalDialog = 239,285,800,479 +QwUserAskDlg = 478,459,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/IPA/sim/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +vcs_svOption = -sml=verdi +smartlog = TRUE +[SimulationPlus2] +dumpPowerRoot = FALSE +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VCS +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +DataViewTooltip = TRUE +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 1280 921 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleInterForm = "share/VIA/Apps/PredefinedRules/UVM_OVM_i_rule.rc" +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.interactiveDebug.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.interactiveDebug.preference.vgifColumnSettingRC] +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0] +parRuleSets = "/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_OVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_UVM.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRule\ +s/par_rule_LP.rc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/VIA/Apps/PredefinedParRules/par_rule_VCS.rc " +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column1] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.interactiveDebug.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.parRule] +parRulePathInterForm = "" +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 239 248 800 479 245 381 505 183 +viewPort = 0 27 1280 816 226 91 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/IPA/sim/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/IPA/sim/tb.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 1280 816 226 91 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/sim/verdiLog/novas_autosave.ses.config b/sim/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..eca9abe --- /dev/null +++ b/sim/verdiLog/novas_autosave.ses.config @@ -0,0 +1,35 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_encode_to_relative_window_id_name=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\ProductVersion=201809 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+Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(1280 921) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=1280 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=921 diff --git a/sim/verdiLog/novas_autosave.ses.png b/sim/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..ac388bd Binary files /dev/null and b/sim/verdiLog/novas_autosave.ses.png differ diff --git a/sim/verdiLog/novas_ones_IC_EDA_16693.log.result b/sim/verdiLog/novas_ones_IC_EDA_16693.log.result new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/pes.bat b/sim/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/sim/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/sim/verdiLog/tdc.list.oneSearch b/sim/verdiLog/tdc.list.oneSearch new file mode 100644 index 0000000..8331d62 --- /dev/null +++ b/sim/verdiLog/tdc.list.oneSearch @@ -0,0 +1,8 @@ +tb.f +../rtl/data_cache/data_cache.v +../rtl/data_cache/async_fifo.v +../rtl/data_cache/data_assemble.v +../rtl/data_cache/rst_sync.v +../rtl/data_cache/axi_write_ctrl.v +../rtl/data_cache/histogram_ctrl.v +../rtl/data_cache/sync_fifo.v diff --git a/sim/verdiLog/turbo.log b/sim/verdiLog/turbo.log new file mode 100644 index 0000000..cbfea46 --- /dev/null +++ b/sim/verdiLog/turbo.log @@ -0,0 +1,2 @@ +Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -f rtl.f tb.f -ssf tb.fsdb +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) diff --git a/sim/verdiLog/verdi.cmd b/sim/verdiLog/verdi.cmd new file mode 100644 index 0000000..3f844b5 --- /dev/null +++ b/sim/verdiLog/verdi.cmd @@ -0,0 +1,375 @@ +debImport "-f" "rtl.f" "tb.f" +debLoadSimResult /home/ICer/ic_prjs/IPA/sim/tb.fsdb +wvCreateWindow +wvGetSignalOpen -win $_nWave2 +wvGetSignalSetScope -win $_nWave2 "/tb_data_cache" +wvSetPosition -win $_nWave2 {("G1" 54)} +wvSetPosition -win $_nWave2 {("G1" 54)} +wvAddSignal -win $_nWave2 -clear +wvAddSignal -win $_nWave2 -group {"G1" \ +{/tb_data_cache/axi_m_awaddr\[31:0\]} \ +{/tb_data_cache/axi_m_awburst\[1:0\]} \ +{/tb_data_cache/axi_m_awcache\[3:0\]} \ +{/tb_data_cache/axi_m_awid\[7:0\]} \ +{/tb_data_cache/axi_m_awlen\[3:0\]} \ +{/tb_data_cache/axi_m_awlock} \ +{/tb_data_cache/axi_m_awprot\[2:0\]} \ +{/tb_data_cache/axi_m_awqos\[3:0\]} \ +{/tb_data_cache/axi_m_awready} \ +{/tb_data_cache/axi_m_awsize\[2:0\]} \ +{/tb_data_cache/axi_m_awvalid} \ +{/tb_data_cache/axi_m_bid\[7:0\]} \ +{/tb_data_cache/axi_m_bready} \ +{/tb_data_cache/axi_m_bresp\[1:0\]} \ +{/tb_data_cache/axi_m_bvalid} \ +{/tb_data_cache/axi_m_wdata\[255:0\]} \ +{/tb_data_cache/axi_m_wid\[7:0\]} \ +{/tb_data_cache/axi_m_wlast} \ +{/tb_data_cache/axi_m_wready} \ +{/tb_data_cache/axi_m_wstrb\[31:0\]} \ +{/tb_data_cache/axi_m_wvalid} \ +{/tb_data_cache/dwidth_conv_max_ch0\[7:0\]} \ +{/tb_data_cache/dwidth_conv_max_ch1\[7:0\]} \ +{/tb_data_cache/dwidth_conv_max_ch2\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch0\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch1\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch2\[7:0\]} \ +{/tb_data_cache/frame_cnt\[15:0\]} \ +{/tb_data_cache/golden_max_ch0\[7:0\]} \ +{/tb_data_cache/golden_max_ch1\[7:0\]} \ +{/tb_data_cache/golden_max_ch2\[7:0\]} \ +{/tb_data_cache/golden_min_ch0\[7:0\]} \ +{/tb_data_cache/golden_min_ch1\[7:0\]} \ +{/tb_data_cache/golden_min_ch2\[7:0\]} \ +{/tb_data_cache/histogram_high_num\[15:0\]} \ +{/tb_data_cache/histogram_low_num\[15:0\]} \ +{/tb_data_cache/input_pixel_type} \ +{/tb_data_cache/ipa_en} \ +{/tb_data_cache/ir_ch0\[7:0\]} \ +{/tb_data_cache/ir_ch1\[7:0\]} \ +{/tb_data_cache/ir_ch2\[7:0\]} \ +{/tb_data_cache/ir_clk} \ +{/tb_data_cache/ir_col_cnt\[15:0\]} \ +{/tb_data_cache/ir_hs} \ +{/tb_data_cache/ir_row_cnt\[15:0\]} \ +{/tb_data_cache/ir_valid} \ +{/tb_data_cache/ir_vs} \ +{/tb_data_cache/prev_state\[2:0\]} \ +{/tb_data_cache/rst_n} \ +{/tb_data_cache/src_image_cache_done} \ +{/tb_data_cache/src_pixel_height\[15:0\]} \ +{/tb_data_cache/src_pixel_width\[15:0\]} \ +{/tb_data_cache/sys_clk} \ +{/tb_data_cache/update_src_trig} \ +} +wvAddSignal -win $_nWave2 -group {"G2" \ +} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 \ + 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 \ + 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 )} +wvSetPosition -win $_nWave2 {("G1" 54)} +wvSetPosition -win $_nWave2 {("G1" 54)} +wvSetPosition -win $_nWave2 {("G1" 54)} +wvAddSignal -win $_nWave2 -clear +wvAddSignal -win $_nWave2 -group {"G1" \ +{/tb_data_cache/axi_m_awaddr\[31:0\]} \ +{/tb_data_cache/axi_m_awburst\[1:0\]} \ +{/tb_data_cache/axi_m_awcache\[3:0\]} \ +{/tb_data_cache/axi_m_awid\[7:0\]} \ +{/tb_data_cache/axi_m_awlen\[3:0\]} \ +{/tb_data_cache/axi_m_awlock} \ +{/tb_data_cache/axi_m_awprot\[2:0\]} \ +{/tb_data_cache/axi_m_awqos\[3:0\]} \ +{/tb_data_cache/axi_m_awready} \ +{/tb_data_cache/axi_m_awsize\[2:0\]} \ +{/tb_data_cache/axi_m_awvalid} \ +{/tb_data_cache/axi_m_bid\[7:0\]} \ +{/tb_data_cache/axi_m_bready} \ +{/tb_data_cache/axi_m_bresp\[1:0\]} \ +{/tb_data_cache/axi_m_bvalid} \ +{/tb_data_cache/axi_m_wdata\[255:0\]} \ +{/tb_data_cache/axi_m_wid\[7:0\]} \ +{/tb_data_cache/axi_m_wlast} \ +{/tb_data_cache/axi_m_wready} \ +{/tb_data_cache/axi_m_wstrb\[31:0\]} \ +{/tb_data_cache/axi_m_wvalid} \ +{/tb_data_cache/dwidth_conv_max_ch0\[7:0\]} \ +{/tb_data_cache/dwidth_conv_max_ch1\[7:0\]} \ +{/tb_data_cache/dwidth_conv_max_ch2\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch0\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch1\[7:0\]} \ +{/tb_data_cache/dwidth_conv_min_ch2\[7:0\]} \ +{/tb_data_cache/frame_cnt\[15:0\]} \ +{/tb_data_cache/golden_max_ch0\[7:0\]} \ +{/tb_data_cache/golden_max_ch1\[7:0\]} \ +{/tb_data_cache/golden_max_ch2\[7:0\]} \ +{/tb_data_cache/golden_min_ch0\[7:0\]} \ +{/tb_data_cache/golden_min_ch1\[7:0\]} \ +{/tb_data_cache/golden_min_ch2\[7:0\]} \ +{/tb_data_cache/histogram_high_num\[15:0\]} \ +{/tb_data_cache/histogram_low_num\[15:0\]} \ +{/tb_data_cache/input_pixel_type} \ +{/tb_data_cache/ipa_en} \ +{/tb_data_cache/ir_ch0\[7:0\]} \ +{/tb_data_cache/ir_ch1\[7:0\]} \ +{/tb_data_cache/ir_ch2\[7:0\]} \ +{/tb_data_cache/ir_clk} \ +{/tb_data_cache/ir_col_cnt\[15:0\]} \ +{/tb_data_cache/ir_hs} \ +{/tb_data_cache/ir_row_cnt\[15:0\]} \ +{/tb_data_cache/ir_valid} \ +{/tb_data_cache/ir_vs} \ +{/tb_data_cache/prev_state\[2:0\]} \ +{/tb_data_cache/rst_n} \ +{/tb_data_cache/src_image_cache_done} \ +{/tb_data_cache/src_pixel_height\[15:0\]} \ +{/tb_data_cache/src_pixel_width\[15:0\]} \ +{/tb_data_cache/sys_clk} \ +{/tb_data_cache/update_src_trig} \ +} +wvAddSignal -win $_nWave2 -group {"G2" \ +} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 \ + 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 \ + 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 )} +wvSetPosition -win $_nWave2 {("G1" 54)} +wvGetSignalClose -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvSelectSignal -win $_nWave2 {( "G1" 22 )} +wvSelectSignal -win $_nWave2 {( "G1" 20 )} +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 3 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 5 +wvScrollDown -win $_nWave2 4 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvSetCursor -win $_nWave2 622185.869797 -snap {("G1" 19)} +wvSetCursor -win $_nWave2 944944.789755 -snap {("G1" 19)} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 diff --git a/sim/verdiLog/verdi_perf_err.log b/sim/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/data_cache/tb_axi_write_ctrl.v b/tb/data_cache/tb_axi_write_ctrl.v new file mode 100644 index 0000000..4f4783c --- /dev/null +++ b/tb/data_cache/tb_axi_write_ctrl.v @@ -0,0 +1,314 @@ +`timescale 1ns/1ps + +module tb_axi_write_ctrl(); + +// -------------------------- 1. 参数定义 -------------------------- +parameter AXI_ID_W = 8; +parameter AXI_ADDR_W = 32; +parameter AXI_DATA_W = 256; +parameter AXI_STRB_W = AXI_DATA_W / 8; +parameter CLK_PERIOD = 10; +parameter FIFO_DEPTH = 4; + +// -------------------------- 2. 信号定义 -------------------------- +// 系统时钟/复位 +reg clk; +reg rst_n; + +// 控制与数据输入 +reg start_en; +reg [AXI_ADDR_W-1:0] sram_base_addr; +wire [AXI_DATA_W-1:0] fifo_rd_data; +wire fifo_empty; +wire fifo_rd_en_dut; // DUT输出的读使能（仅由DUT驱动） + +// Testbench控制的FIFO读使能（用于清空FIFO） +reg tb_fifo_rd_en; +// 合并后的FIFO读使能（仅驱动FIFO，避免直接驱动DUT输出） +wire fifo_rd_en = tb_fifo_rd_en | fifo_rd_en_dut; + +// AXI AW通道 +wire [AXI_ID_W-1:0] axi_m_awid; +wire [AXI_ADDR_W-1:0] axi_m_awaddr; +wire [3:0] axi_m_awlen; +wire [2:0] axi_m_awsize; +wire [1:0] axi_m_awburst; +wire axi_m_awlock; +wire [4:0] axi_m_awcache; +wire [2:0] axi_m_awprot; +wire [4:0] axi_m_awqos; +wire axi_m_awvalid; +reg axi_m_awready; + +// AXI W通道 +wire [AXI_ID_W-1:0] axi_m_wid; +wire [AXI_DATA_W-1:0] axi_m_wdata; +wire [AXI_STRB_W-1:0] axi_m_wstrb; +wire axi_m_wlast; +wire axi_m_wvalid; +reg axi_m_wready; + +// AXI B通道 +reg [AXI_ID_W-1:0] axi_m_bid; +reg [1:0] axi_m_bresp; +reg axi_m_bvalid; +wire axi_m_bready; + +// DUT状态输出 +wire axi_busy; +wire axi_done; + +// FIFO相关控制信号 +reg fifo_wr_en; +reg [AXI_DATA_W-1:0] fifo_wr_data; +wire fifo_full; +reg [$clog2(FIFO_DEPTH)-1:0] fifo_wr_ptr; + +// -------------------------- 3. 生成系统时钟 -------------------------- +initial begin + clk = 1'b0; + forever #(CLK_PERIOD/2) clk = ~clk; +end + +// -------------------------- 4. 实例化DUT（AXI写控制器） -------------------------- +axi_write_ctrl #( + .AXI_ID_W (AXI_ID_W), + .AXI_ADDR_W (AXI_ADDR_W), + .AXI_DATA_W (AXI_DATA_W), + .AXI_STRB_W (AXI_STRB_W) +) u_axi_write_ctrl ( + .clk (clk), + .rst_n (rst_n), + .start_en (start_en), + .sram_base_addr (sram_base_addr), + .fifo_rd_data (fifo_rd_data), + .fifo_empty (fifo_empty), + .fifo_rd_en (fifo_rd_en_dut), // DUT输出单独命名，避免冲突 + .axi_m_awid (axi_m_awid), + .axi_m_awaddr (axi_m_awaddr), + .axi_m_awlen (axi_m_awlen), + .axi_m_awsize (axi_m_awsize), + .axi_m_awburst (axi_m_awburst), + .axi_m_awlock (axi_m_awlock), + .axi_m_awcache (axi_m_awcache), + .axi_m_awprot (axi_m_awprot), + .axi_m_awqos (axi_m_awqos), + .axi_m_awvalid (axi_m_awvalid), + .axi_m_awready (axi_m_awready), + .axi_m_wid (axi_m_wid), + .axi_m_wdata (axi_m_wdata), + .axi_m_wstrb (axi_m_wstrb), + .axi_m_wlast (axi_m_wlast), + .axi_m_wvalid (axi_m_wvalid), + .axi_m_wready (axi_m_wready), + .axi_m_bid (axi_m_bid), + .axi_m_bresp (axi_m_bresp), + .axi_m_bvalid (axi_m_bvalid), + .axi_m_bready (axi_m_bready), + .axi_busy (axi_busy), + .axi_done (axi_done) +); + +// -------------------------- 5. 实例化sync_fifo模块 -------------------------- +sync_fifo #( + .DATA_WIDTH (AXI_DATA_W), + .FIFO_DEPTH (FIFO_DEPTH) +) u_sync_fifo ( + .clk (clk), + .rst_n (rst_n), + .wr_en (fifo_wr_en), + .wr_data (fifo_wr_data), + .full (fifo_full), + .rd_en (fifo_rd_en), // 使用合并后的读使能 + .rd_data (fifo_rd_data), + .empty (fifo_empty) +); + +// -------------------------- 6. 生成FSDB波形文件 -------------------------- +initial begin + $fsdbDumpfile("tb.fsdb"); + $fsdbDumpvars(0, tb_axi_write_ctrl); + $fsdbDumpMDA(0, tb_axi_write_ctrl); +end + +// -------------------------- 7. FIFO初始化与数据写入 -------------------------- +reg [AXI_DATA_W-1:0] fifo_init_data[FIFO_DEPTH-1:0]; + +initial begin + fifo_init_data[0] = 256'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f; + fifo_init_data[1] = 256'h20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f; + fifo_init_data[2] = 256'h40414243_44454647_48494a4b_4c4d4e4f_50515253_54555657_58595a5b_5c5d5e5f; + fifo_init_data[3] = 256'h60616263_64656667_68696a6b_6c6d6e6f_70717273_74757677_78797a7b_7c7d7e7f; +end + +task fill_fifo; + input integer count; + begin + fifo_wr_en = 1'b1; + repeat(count) begin + @(posedge clk); + if (!fifo_full) begin + fifo_wr_data = fifo_init_data[fifo_wr_ptr]; + fifo_wr_ptr = fifo_wr_ptr + 1'b1; + if (fifo_wr_ptr >= FIFO_DEPTH) fifo_wr_ptr = 0; + end + end + fifo_wr_en = 1'b0; + @(posedge clk); + end +endtask + +// -------------------------- 8. 模拟AXI从机 -------------------------- +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_awready <= 1'b0; + end else if (axi_m_awvalid) begin + axi_m_awready <= ($random % 2) ? 1'b1 : 1'b0; + if (!axi_m_awready && axi_m_awvalid) begin + axi_m_awready <= #(CLK_PERIOD) 1'b1; + end + end else begin + axi_m_awready <= 1'b0; + end +end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_wready <= 1'b0; + end else if (axi_m_wvalid) begin + axi_m_wready <= ($random % 2) ? 1'b1 : 1'b0; + if (!axi_m_wready && axi_m_wvalid) begin + axi_m_wready <= #(CLK_PERIOD) 1'b1; + end + end else begin + axi_m_wready <= 1'b0; + end +end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_bvalid <= 1'b0; + axi_m_bid <= 8'd0; + axi_m_bresp <= 2'd0; + end else if (axi_m_wvalid && axi_m_wready) begin + axi_m_bvalid <= #(CLK_PERIOD) 1'b1; + axi_m_bid <= axi_m_wid; + end else if (axi_m_bvalid && axi_m_bready) begin + axi_m_bvalid <= 1'b0; + end +end + +// -------------------------- 9. 核心测试场景 -------------------------- +initial begin + rst_n = 1'b0; + start_en = 1'b0; + sram_base_addr = 32'h1000_0000; + fifo_wr_en = 1'b0; + fifo_wr_data = {AXI_DATA_W{1'b0}}; + fifo_wr_ptr = 0; + tb_fifo_rd_en = 1'b0; + axi_m_bid = 8'd0; + axi_m_bresp = 2'd0; + axi_m_bvalid = 1'b0; + + #(CLK_PERIOD * 5); + rst_n = 1'b1; + #(CLK_PERIOD * 2); + + // 测试1：单事务写 + $display("[%0t] Test 1: Single AXI Write Transaction", $time); + fill_fifo(FIFO_DEPTH); + start_en = 1'b1; + #(CLK_PERIOD); + start_en = 1'b0; + + wait(axi_done == 1'b1); + #(CLK_PERIOD); + $display("[%0t] Test 1 Result: AWAddr=0x%08h (Expected:0x10000000), WData Match=%b", + $time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[0])); + #(CLK_PERIOD * 2); + + // 测试2：连续事务写 + $display("[%0t] Test 2: Continuous AXI Write Transactions", $time); + fill_fifo(FIFO_DEPTH); + #(CLK_PERIOD); + + start_en = 1'b1; + #(CLK_PERIOD); + start_en = 1'b0; + wait(axi_done == 1'b1); + #(CLK_PERIOD); + $display("[%0t] Test 2 Trans1: AWAddr=0x%08h (Expected:0x10000020), WData Match=%b", + $time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[1])); + + fill_fifo(FIFO_DEPTH); + #(CLK_PERIOD); + + start_en = 1'b1; + #(CLK_PERIOD); + start_en = 1'b0; + wait(axi_done == 1'b1); + #(CLK_PERIOD); + $display("[%0t] Test 2 Trans2: AWAddr=0x%08h (Expected:0x10000040), WData Match=%b", + $time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[2])); + #(CLK_PERIOD * 2); + + // 测试3：FIFO空阻塞 + $display("[%0t] Test 3: FIFO Empty Block Test", $time); + tb_fifo_rd_en = 1'b1; // 使用Testbench读使能清空FIFO + while (!fifo_empty) begin + @(posedge clk); + end + tb_fifo_rd_en = 1'b0; + #(CLK_PERIOD); + + start_en = 1'b1; + #(CLK_PERIOD * 3); + start_en = 1'b0; + + $display("[%0t] Test 3 Result: AXI Busy=%b (Expected:0), AWValid=%b (Expected:0)", + $time, axi_busy, axi_m_awvalid); + #(CLK_PERIOD * 2); + + // 测试4：AXI握手延迟 + $display("[%0t] Test 4: AXI Handshake Delay Test", $time); + fill_fifo(FIFO_DEPTH); + #(CLK_PERIOD); + + axi_m_awready <= 1'b0; + axi_m_wready <= 1'b0; + start_en = 1'b1; + #(CLK_PERIOD); + start_en = 1'b0; + + #(CLK_PERIOD * 2); + axi_m_awready <= 1'b1; + #(CLK_PERIOD); + axi_m_wready <= 1'b1; + + wait(axi_done == 1'b1); + #(CLK_PERIOD); + $display("[%0t] Test 4 Result: WData Match=%b (Expected:1), Done=%b (Expected:1)", + $time, (axi_m_wdata == fifo_init_data[3]), axi_done); + #(CLK_PERIOD * 2); + + $display("[%0t] All Tests Completed!", $time); + $finish; +end + +// -------------------------- 10. 状态监控 -------------------------- +reg [1:0] axi_state; +always @(posedge clk) begin + axi_state = u_axi_write_ctrl.axi_state; +end + +always @(posedge clk) begin + case (axi_state) + 2'd0: $display("[%0t] AXI State: IDLE", $time); + 2'd1: $display("[%0t] AXI State: AW (Address Channel)", $time); + 2'd2: $display("[%0t] AXI State: W (Data Channel)", $time); + 2'd3: $display("[%0t] AXI State: B (Response Channel)", $time); + endcase +end + +endmodule diff --git a/tb/data_cache/tb_data_assemble.v b/tb/data_cache/tb_data_assemble.v new file mode 100644 index 0000000..46e27ab --- /dev/null +++ b/tb/data_cache/tb_data_assemble.v @@ -0,0 +1,138 @@ +`timescale 1ns/1ps + +module tb_data_assemble(); + +// 参数定义 +parameter PIXEL_WIDTH = 8; +parameter GRAY_PIXEL_CNT = 32; +parameter RGB_PIXEL_CNT = 8; + +// 信号定义 +reg clk; +reg rst_n; +reg en; +reg input_pixel_type; +reg [PIXEL_WIDTH-1:0] ir_ch0; +reg [PIXEL_WIDTH-1:0] ir_ch1; +reg [PIXEL_WIDTH-1:0] ir_ch2; +reg pixel_valid; +wire done; +wire [255:0] assembled_data; + +// 生成时钟（100MHz） +initial begin + clk = 1'b0; + forever #5 clk = ~clk; +end + +// 实例化DUT +data_assemble #( + .PIXEL_WIDTH (PIXEL_WIDTH), + .GRAY_PIXEL_CNT (GRAY_PIXEL_CNT), + .RGB_PIXEL_CNT (RGB_PIXEL_CNT) +) u_data_assemble ( + .clk (clk), + .rst_n (rst_n), + .en (en), + .input_pixel_type(input_pixel_type), + .ir_ch0 (ir_ch0), + .ir_ch1 (ir_ch1), + .ir_ch2 (ir_ch2), + .pixel_valid (pixel_valid), + .done (done), + .assembled_data (assembled_data) +); + +// 生成FSDB波形 +initial begin + $fsdbDumpfile("tb.fsdb"); + $fsdbDumpvars(0, tb_data_assemble); + $fsdbDumpMDA(0, tb_data_assemble); +end + +// 测试场景 +initial begin + // 初始化 + rst_n = 1'b0; + en = 1'b0; + input_pixel_type = 1'b0; + ir_ch0 = 8'd0; + ir_ch1 = 8'd0; + ir_ch2 = 8'd0; + pixel_valid = 1'b0; + + // 释放复位 + #20; + rst_n = 1'b1; + #20; + + // -------------------------- 测试1：Gray模式拼接 -------------------------- + $display("[%0t] Test 1: Gray mode assembly", $time); + input_pixel_type = 1'b0; + en = 1'b1; + #10; + + // 输入32个数据（0x01~0x20） + repeat (GRAY_PIXEL_CNT) begin + @(posedge clk); + pixel_valid = 1'b1; + ir_ch0 = ir_ch0 + 8'd1; // 最后一个数据为0x20 + end + @(posedge clk); + pixel_valid = 1'b0; + + wait(done == 1'b1); + #10; + // 验证首8bit（0x01）和尾8bit（0x20） + $display("[%0t] Gray first 8bit: 0x%0h (Expected: 0x1)", + $time, assembled_data[255:248]); + $display("[%0t] Gray last 8bit: 0x%0h (Expected: 0x20)", + $time, assembled_data[7:0]); + #20; + + // -------------------------- 测试2：RGB模式拼接 -------------------------- + $display("[%0t] Test 2: RGB mode assembly", $time); + input_pixel_type = 1'b1; + ir_ch0 = 8'd0; + ir_ch1 = 8'd0; + ir_ch2 = 8'd0; + #10; + + // 输入8组数据：CH0=10*N, CH1=20*N, CH2=30*N（N=1~8） + repeat (RGB_PIXEL_CNT) begin + @(posedge clk); + pixel_valid = 1'b1; + ir_ch0 = ir_ch0 + 8'd10; // 10,20,...,80（0x0a,0x14,...,0x50） + ir_ch1 = ir_ch1 + 8'd20; // 20,40,...,160（0x14,0x28,...,0xa0） + ir_ch2 = ir_ch2 + 8'd30; // 30,60,...,240（0x1e,0x3c,...,0xf0） + end + @(posedge clk); + pixel_valid = 1'b0; + + wait(done == 1'b1); + #10; + // 验证首32bit（{8'd0,30,20,10}=0x00_1e_14_0a）和尾32bit（{8'd0,240,160,80}=0x00_f0_a0_50） + $display("[%0t] RGB first 32bit: 0x%08h (Expected: 0x001e140a)", + $time, assembled_data[255:224]); + $display("[%0t] RGB last 32bit: 0x%08h (Expected: 0x00f0a050)", + $time, assembled_data[31:0]); + #20; + + // -------------------------- 测试3：关闭使能 -------------------------- + $display("[%0t] Test 3: Disable assembly", $time); + en = 1'b0; + input_pixel_type = 1'b0; + @(posedge clk); + pixel_valid = 1'b1; + ir_ch0 = 8'd1; + @(posedge clk); + pixel_valid = 1'b0; + #10; + $display("[%0t] Disable check: done=%b (Expected:0)", $time, done); + #20; + + $display("[%0t] All tests completed!", $time); + $finish; +end + +endmodule \ No newline at end of file diff --git a/tb/data_cache/tb_data_cache.v b/tb/data_cache/tb_data_cache.v new file mode 100644 index 0000000..4444578 --- /dev/null +++ b/tb/data_cache/tb_data_cache.v @@ -0,0 +1,450 @@ +`timescale 1ns/1ps + +module tb_data_cache(); + +// -------------------------- 参数定义 -------------------------- +parameter ASYNC_FIFO_DEPTH = 1024; +parameter ASYNC_FIFO_DATA_W = 27; +parameter SYNC_FIFO_DEPTH = 2048; +parameter SYNC_FIFO_DATA_W = 256; +parameter HIST_RAM_DEPTH = 256; +parameter HIST_RAM_DATA_W = 1; +parameter AXI_ID_W = 8; +parameter AXI_ADDR_W = 32; +parameter AXI_DATA_W = 256; +parameter AXI_STRB_W = AXI_DATA_W / 8; + +// 测试用图像参数 +parameter IMAGE_WIDTH = 32; // 图像宽度（32像素，便于拼接256bit） +parameter IMAGE_HEIGHT = 16; // 图像高度 +parameter HIST_LOW_NUM = 1; // 直方图低位数量 +parameter HIST_HIGH_NUM = 1; // 直方图高位数量 + +// 时钟周期定义 +parameter SYS_CLK_PERIOD = 10; // 系统时钟周期(10ns=100MHz) +parameter IR_CLK_PERIOD = 5; // IR时钟周期(8ns=125MHz) + +// -------------------------- 信号定义 -------------------------- +// 系统时钟与复位 +reg sys_clk; +reg ir_clk; +reg rst_n; + +// 配置信号 +reg ipa_en; +reg update_src_trig; +reg input_pixel_type; +reg [15:0] src_pixel_height; +reg [15:0] src_pixel_width; +reg [15:0] histogram_low_num; +reg [15:0] histogram_high_num; +wire src_image_cache_done; + +// 与Windowed模块接口 +wire [7:0] dwidth_conv_min_ch0; +wire [7:0] dwidth_conv_max_ch0; +wire [7:0] dwidth_conv_min_ch1; +wire [7:0] dwidth_conv_max_ch1; +wire [7:0] dwidth_conv_min_ch2; +wire [7:0] dwidth_conv_max_ch2; + +// IR图像输入 +reg ir_valid; +reg ir_vs; +reg ir_hs; +reg [7:0] ir_ch0; +reg [7:0] ir_ch1; +reg [7:0] ir_ch2; + +// AXI写总线 +wire [AXI_ID_W-1:0] axi_m_awid; +wire [AXI_ADDR_W-1:0] axi_m_awaddr; +wire [3:0] axi_m_awlen; +wire [2:0] axi_m_awsize; +wire [1:0] axi_m_awburst; +wire axi_m_awlock; +wire [3:0] axi_m_awcache; +wire [2:0] axi_m_awprot; +wire [3:0] axi_m_awqos; +wire axi_m_awvalid; +reg axi_m_awready; +wire [AXI_ID_W-1:0] axi_m_wid; +wire [AXI_DATA_W-1:0] axi_m_wdata; +wire [AXI_STRB_W-1:0] axi_m_wstrb; +wire axi_m_wlast; +wire axi_m_wvalid; +reg axi_m_wready; +reg [AXI_ID_W-1:0] axi_m_bid; +reg [1:0] axi_m_bresp; +reg axi_m_bvalid; +wire axi_m_bready; + +// 内部测试信号 +reg [15:0] frame_cnt; // 帧计数器 +reg [15:0] ir_row_cnt; // IR行计数器 +reg [15:0] ir_col_cnt; // IR列计数器 +reg [7:0] golden_min_ch0; // 预期CH0最小值 +reg [7:0] golden_max_ch0; // 预期CH0最大值 +reg [7:0] golden_min_ch1; // 预期CH1最小值 +reg [7:0] golden_max_ch1; // 预期CH1最大值 +reg [7:0] golden_min_ch2; // 预期CH2最小值 +reg [7:0] golden_max_ch2; // 预期CH2最大值 + + +// -------------------------- 时钟生成 -------------------------- +initial begin + sys_clk = 1'b0; + forever #(SYS_CLK_PERIOD/2) sys_clk = ~sys_clk; +end + +initial begin + ir_clk = 1'b0; + forever #(IR_CLK_PERIOD/2) ir_clk = ~ir_clk; +end + +// -------------------------- 实例化DUT -------------------------- +data_cache #( + .ASYNC_FIFO_DEPTH(ASYNC_FIFO_DEPTH), + .ASYNC_FIFO_DATA_W(ASYNC_FIFO_DATA_W), + .SYNC_FIFO_DEPTH(SYNC_FIFO_DEPTH), + .SYNC_FIFO_DATA_W(SYNC_FIFO_DATA_W), + .HIST_RAM_DEPTH(HIST_RAM_DEPTH), + .HIST_RAM_DATA_W(HIST_RAM_DATA_W), + .AXI_ID_W(AXI_ID_W), + .AXI_ADDR_W(AXI_ADDR_W), + .AXI_DATA_W(AXI_DATA_W), + .AXI_STRB_W(AXI_STRB_W) +) u_data_cache ( + .clk(sys_clk), + .rst_n(rst_n), + .ipa_en(ipa_en), + .update_src_trig(update_src_trig), + .input_pixel_type(input_pixel_type), + .src_pixel_height(src_pixel_height), + .src_pixel_width(src_pixel_width), + .histogram_low_num(histogram_low_num), + .histogram_high_num(histogram_high_num), + .src_image_cache_done(src_image_cache_done), + .dwidth_conv_min_ch0(dwidth_conv_min_ch0), + .dwidth_conv_max_ch0(dwidth_conv_max_ch0), + .dwidth_conv_min_ch1(dwidth_conv_min_ch1), + .dwidth_conv_max_ch1(dwidth_conv_max_ch1), + .dwidth_conv_min_ch2(dwidth_conv_min_ch2), + .dwidth_conv_max_ch2(dwidth_conv_max_ch2), + .ir_clk(ir_clk), + .ir_valid(ir_valid), + .ir_vs(ir_vs), + .ir_hs(ir_hs), + .ir_ch0(ir_ch0), + .ir_ch1(ir_ch1), + .ir_ch2(ir_ch2), + .axi_m_awid(axi_m_awid), + .axi_m_awaddr(axi_m_awaddr), + .axi_m_awlen(axi_m_awlen), + .axi_m_awsize(axi_m_awsize), + .axi_m_awburst(axi_m_awburst), + .axi_m_awlock(axi_m_awlock), + .axi_m_awcache(axi_m_awcache), + .axi_m_awprot(axi_m_awprot), + .axi_m_awqos(axi_m_awqos), + .axi_m_awvalid(axi_m_awvalid), + .axi_m_awready(axi_m_awready), + .axi_m_wid(axi_m_wid), + .axi_m_wdata(axi_m_wdata), + .axi_m_wstrb(axi_m_wstrb), + .axi_m_wlast(axi_m_wlast), + .axi_m_wvalid(axi_m_wvalid), + .axi_m_wready(axi_m_wready), + .axi_m_bid(axi_m_bid), + .axi_m_bresp(axi_m_bresp), + .axi_m_bvalid(axi_m_bvalid), + .axi_m_bready(axi_m_bready) +); + +// -------------------------- 生成FSDB波形 -------------------------- +initial begin + $fsdbDumpfile("tb.fsdb"); + $fsdbDumpvars(0, tb_data_cache); + $fsdbDumpMDA(0, tb_data_cache); // 记录内存和内部信号 +end + +// -------------------------- AXI从机模拟 -------------------------- +// AW通道响应 +always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_awready <= 1'b0; + end else if (axi_m_awvalid) begin + // 随机延迟响应，模拟真实从机 + axi_m_awready <= ($random % 2) ? 1'b1 : 1'b0; + if (!axi_m_awready) begin + axi_m_awready <= #(SYS_CLK_PERIOD) 1'b1; + end + end else begin + axi_m_awready <= 1'b0; + end +end + +// W通道响应 +always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_wready <= 1'b0; + end else if (axi_m_wvalid) begin + axi_m_wready <= ($random % 2) ? 1'b1 : 1'b0; + if (!axi_m_wready) begin + axi_m_wready <= #(SYS_CLK_PERIOD) 1'b1; + end + end else begin + axi_m_wready <= 1'b0; + end +end + +// B通道响应 +always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + axi_m_bvalid <= 1'b0; + axi_m_bid <= 8'd0; + axi_m_bresp <= 2'd0; // 0=OKAY + end else if (axi_m_wvalid && axi_m_wready) begin + // W通道传输完成后，延迟1周期发送响应 + axi_m_bvalid <= #(SYS_CLK_PERIOD) 1'b1; + axi_m_bid <= axi_m_wid; + end else if (axi_m_bvalid && axi_m_bready) begin + axi_m_bvalid <= 1'b0; + end +end + +// -------------------------- 生成测试图像数据 -------------------------- +task generate_ir_data; + input integer frame_num; + input integer is_rgb; + begin + // 初始化计数器 + ir_row_cnt = 0; + ir_col_cnt = 0; + ir_vs = 1'b0; + ir_hs = 1'b0; + ir_valid = 1'b0; + ir_ch0 = 8'd0; + ir_ch1 = 8'd0; + ir_ch2 = 8'd0; + + // 发送帧起始信号（ir_vs至少持续2个ir_clk周期，确保被FIFO捕获） + @(posedge ir_clk); + ir_vs = 1'b1; + ir_valid = 1'b1; // 强制置1，配合DUT的async_fifo_wr_en逻辑 + @(posedge ir_clk); + @(posedge ir_clk); // 持续2个周期，避免单周期漏采 + ir_vs = 1'b0; + ir_valid = 1'b0; + // 计算预期的min/max值 + if (is_rgb) begin + golden_min_ch0 = 8'd32 + frame_num * 16; + golden_max_ch0 = 8'd96 + frame_num * 16; + golden_min_ch1 = 8'd64 + frame_num * 16; + golden_max_ch1 = 8'd128 + frame_num * 16; + golden_min_ch2 = 8'd96 + frame_num * 16; + golden_max_ch2 = 8'd160 + frame_num * 16; + end else begin + golden_min_ch0 = 8'd32 + frame_num * 16; + golden_max_ch0 = 8'd192 + frame_num * 16; + golden_min_ch1 = 8'd0; + golden_max_ch1 = 8'd0; + golden_min_ch2 = 8'd0; + golden_max_ch2 = 8'd0; + end + + // 逐行发送数据 + while (ir_row_cnt < IMAGE_HEIGHT) begin + // 行起始信号 + ir_hs = 1'b1; + @(posedge ir_clk); + ir_hs = 1'b0; + + // 逐像素发送数据 + ir_col_cnt = 0; + while (ir_col_cnt < IMAGE_WIDTH) begin + ir_valid = 1'b1; + + // 生成有规律的数据便于验证 + if (is_rgb) begin + // RGB模式：三个通道不同范围 + ir_ch0 = golden_min_ch0 + (ir_row_cnt % (golden_max_ch0 - golden_min_ch0 + 1)); + ir_ch1 = golden_min_ch1 + (ir_col_cnt % (golden_max_ch1 - golden_min_ch1 + 1)); + ir_ch2 = golden_min_ch2 + ((ir_row_cnt + ir_col_cnt) % (golden_max_ch2 - golden_min_ch2 + 1)); + end else begin + // 灰度模式：仅CH0有效 + ir_ch0 = golden_min_ch0 + ((ir_row_cnt * IMAGE_WIDTH + ir_col_cnt) % + (golden_max_ch0 - golden_min_ch0 + 1)); + ir_ch1 = 8'd0; + ir_ch2 = 8'd0; + end + + @(posedge ir_clk); + ir_col_cnt = ir_col_cnt + 1; + end + + // 行结束 + ir_valid = 1'b0; + ir_row_cnt = ir_row_cnt + 1; + // 行间隙 + repeat(2) @(posedge ir_clk); + end + + // 帧结束 + ir_valid = 1'b0; + // 帧间隙 + repeat(5) @(posedge ir_clk); + end +endtask + +// -------------------------- 核心测试流程 -------------------------- +initial begin + // 初始化 + rst_n = 1'b0; + ipa_en = 1'b0; + update_src_trig = 1'b0; + input_pixel_type = 1'b0; // 默认灰度模式 + src_pixel_height = IMAGE_HEIGHT; + src_pixel_width = IMAGE_WIDTH; + histogram_low_num = HIST_LOW_NUM; + histogram_high_num = HIST_HIGH_NUM; + frame_cnt = 16'd0; + axi_m_bid = 8'd0; + axi_m_bresp = 2'd0; + axi_m_bvalid = 1'b0; + + // 复位 + #(SYS_CLK_PERIOD * 10); + rst_n = 1'b1; + #(SYS_CLK_PERIOD * 5); + + // 测试1：灰度模式单帧测试 + $display("[%0t] Test 1: Gray scale single frame test", $time); + input_pixel_type = 1'b0; // 灰度模式 + ipa_en = 1'b1; + #(SYS_CLK_PERIOD * 2); + + // 发送一帧灰度图像 + generate_ir_data(frame_cnt, 0); + frame_cnt = frame_cnt + 1; + + // 等待缓存完成 + wait(src_image_cache_done == 1'b1); + #(SYS_CLK_PERIOD * 10); + + // 验证直方图结果 + $display("[%0t] Test 1 Histogram Check: CH0 min=%h (exp=%h), max=%h (exp=%h)", + $time, dwidth_conv_min_ch0, golden_min_ch0, + dwidth_conv_max_ch0, golden_max_ch0); + if (dwidth_conv_min_ch0 != golden_min_ch0 || dwidth_conv_max_ch0 != golden_max_ch0) begin + $display("[%0t] Test 1 Histogram Check FAILED!", $time); + end else begin + $display("[%0t] Test 1 Histogram Check PASSED!", $time); + end + #(SYS_CLK_PERIOD * 5); + + // 测试2：RGB模式单帧测试 + $display("[%0t] Test 2: RGB single frame test", $time); + update_src_trig = 1'b1; // 触发更新 + #(SYS_CLK_PERIOD * 2); + update_src_trig = 1'b0; + input_pixel_type = 1'b1; // RGB模式 + #(SYS_CLK_PERIOD * 2); + + // 发送一帧RGB图像 + generate_ir_data(frame_cnt, 1); + frame_cnt = frame_cnt + 1; + + // 等待缓存完成 + wait(src_image_cache_done == 1'b1); + #(SYS_CLK_PERIOD * 10); + + // 验证直方图结果 + $display("[%0t] Test 2 Histogram Check: CH0 min=%h (exp=%h), max=%h (exp=%h)", + $time, dwidth_conv_min_ch0, golden_min_ch0, + dwidth_conv_max_ch0, golden_max_ch0); + $display("[%0t] Test 2 Histogram Check: CH1 min=%h (exp=%h), max=%h (exp=%h)", + $time, dwidth_conv_min_ch1, golden_min_ch1, + dwidth_conv_max_ch1, golden_max_ch1); + $display("[%0t] Test 2 Histogram Check: CH2 min=%h (exp=%h), max=%h (exp=%h)", + $time, dwidth_conv_min_ch2, golden_min_ch2, + dwidth_conv_max_ch2, golden_max_ch2); + + if (dwidth_conv_min_ch0 != golden_min_ch0 || dwidth_conv_max_ch0 != golden_max_ch0 || + dwidth_conv_min_ch1 != golden_min_ch1 || dwidth_conv_max_ch1 != golden_max_ch1 || + dwidth_conv_min_ch2 != golden_min_ch2 || dwidth_conv_max_ch2 != golden_max_ch2) begin + $display("[%0t] Test 2 Histogram Check FAILED!", $time); + end else begin + $display("[%0t] Test 2 Histogram Check PASSED!", $time); + end + #(SYS_CLK_PERIOD * 5); + + // 测试3：连续两帧测试（验证FIFO和AXI写连续性） + $display("[%0t] Test 3: Continuous frame test", $time); + update_src_trig = 1'b1; + #(SYS_CLK_PERIOD * 2); + update_src_trig = 1'b0; + #(SYS_CLK_PERIOD * 2); + + // 发送第3帧（灰度） + input_pixel_type = 1'b0; + generate_ir_data(frame_cnt, 0); + frame_cnt = frame_cnt + 1; + wait(src_image_cache_done == 1'b1); + #(SYS_CLK_PERIOD * 5); + + // 发送第4帧（RGB） + input_pixel_type = 1'b1; + generate_ir_data(frame_cnt, 1); + frame_cnt = frame_cnt + 1; + wait(src_image_cache_done == 1'b1); + #(SYS_CLK_PERIOD * 10); + + // 测试4：更新触发测试（验证中途更新配置） + $display("[%0t] Test 4: Update trigger test", $time); + input_pixel_type = 1'b0; + generate_ir_data(frame_cnt, 0); + frame_cnt = frame_cnt + 1; + + // 中途发送更新触发 + #(SYS_CLK_PERIOD * 20); + update_src_trig = 1'b1; + #(SYS_CLK_PERIOD * 5); + update_src_trig = 1'b0; + #(SYS_CLK_PERIOD * 10); + + // 所有测试完成 + $display("[%0t] All tests completed!", $time); + $finish; +end + +// -------------------------- 监控AXI写事务 -------------------------- +always @(posedge sys_clk) begin + if (axi_m_awvalid && axi_m_awready) begin + $display("[%0t] AXI Write Transaction: Address=0x%08h, Length=%d", + $time, axi_m_awaddr, axi_m_awlen); + end + + if (axi_m_wvalid && axi_m_wready) begin + $display("[%0t] AXI Write Data: ID=%d, Data[31:0]=0x%08h, Last=%b", + $time, axi_m_wid, axi_m_wdata[31:0], axi_m_wlast); + end +end + +// -------------------------- 监控状态转换 -------------------------- +reg [2:0] prev_state; +always @(posedge sys_clk) begin + prev_state <= u_data_cache.curr_state; + if (prev_state != u_data_cache.curr_state) begin + case (u_data_cache.curr_state) + 3'b000: $display("[%0t] Data Cache State: IDLE", $time); + 3'b001: $display("[%0t] Data Cache State: WAIT_VS", $time); + 3'b010: $display("[%0t] Data Cache State: RECEIVE_DATA", $time); + 3'b011: $display("[%0t] Data Cache State: WRITE_FIFO", $time); + 3'b100: $display("[%0t] Data Cache State: WAIT_AXI", $time); + 3'b101: $display("[%0t] Data Cache State: FRAME_DONE", $time); + endcase + end +end + +endmodule diff --git a/tb/data_cache/tb_histogram_ctrl.v b/tb/data_cache/tb_histogram_ctrl.v new file mode 100644 index 0000000..a177b00 --- /dev/null +++ b/tb/data_cache/tb_histogram_ctrl.v @@ -0,0 +1,208 @@ +`timescale 1ns/1ps + +// 直方图控制模块Testbench（修复标识符未声明问题） +module tb_histogram_ctrl(); + +// -------------------------- 1. 参数定义（与待测试模块匹配） -------------------------- +parameter HIST_RAM_DEPTH = 256; // 直方图RAM深度（像素值0~255） +parameter HIST_RAM_DATA_W = 1; // 直方图RAM数据位宽（1bit标记像素存在） +parameter CLK_PERIOD = 10; // 时钟周期（10ns = 100MHz） +parameter RAM_CLEAR_CYCLES = 256; // 直方图复位需遍历256个地址（256个时钟周期） + +// -------------------------- 2. 信号定义（仅含模块接口信号，无内部信号引用） -------------------------- +reg clk; // 时钟 +reg rst_n; // 全局复位（低有效） +reg hist_rst; // 直方图复位 +reg input_pixel_type; // 像素类型（0=Gray，1=RGB） +// CH0 写信号（Gray模式有效/RGB模式R通道） +reg hist_wr_en_ch0; // CH0写使能 +reg [7:0] hist_wr_addr_ch0; // CH0写地址（像素值0~255） +// CH1 写信号（仅RGB模式G通道） +reg hist_wr_en_ch1; // CH1写使能 +reg [7:0] hist_wr_addr_ch1; // CH1写地址 +// CH2 写信号（仅RGB模式B通道） +reg hist_wr_en_ch2; // CH2写使能 +reg [7:0] hist_wr_addr_ch2; // CH2写地址 +// min/max计算配置 +reg [15:0] histogram_low_num; // 低位数（第N个有效像素作为min） +reg [15:0] histogram_high_num; // 高位数（第N个有效像素作为max） +reg calc_en; // 计算使能 +// 输出信号 +wire calc_done; // 计算完成 +wire [7:0] dwidth_conv_min_ch0;// CH0 min结果 +wire [7:0] dwidth_conv_max_ch0;// CH0 max结果 +wire [7:0] dwidth_conv_min_ch1;// CH1 min结果 +wire [7:0] dwidth_conv_max_ch1;// CH1 max结果 +wire [7:0] dwidth_conv_min_ch2;// CH2 min结果 +wire [7:0] dwidth_conv_max_ch2;// CH2 max结果 + +// -------------------------- 3. 生成时钟 -------------------------- +initial begin + clk = 1'b0; + forever #(CLK_PERIOD/2) clk = ~clk; // 5ns翻转，100MHz时钟 +end + +// -------------------------- 4. 实例化待测试模块 -------------------------- +histogram_ctrl #( + .HIST_RAM_DEPTH (HIST_RAM_DEPTH), + .HIST_RAM_DATA_W (HIST_RAM_DATA_W) +) u_histogram_ctrl ( + .clk (clk), + .rst_n (rst_n), + .hist_rst (hist_rst), + .input_pixel_type (input_pixel_type), + .hist_wr_en_ch0 (hist_wr_en_ch0), + .hist_wr_addr_ch0 (hist_wr_addr_ch0), + .hist_wr_en_ch1 (hist_wr_en_ch1), + .hist_wr_addr_ch1 (hist_wr_addr_ch1), + .hist_wr_en_ch2 (hist_wr_en_ch2), + .hist_wr_addr_ch2 (hist_wr_addr_ch2), + .histogram_low_num (histogram_low_num), + .histogram_high_num (histogram_high_num), + .calc_en (calc_en), + .calc_done (calc_done), + .dwidth_conv_min_ch0 (dwidth_conv_min_ch0), + .dwidth_conv_max_ch0 (dwidth_conv_max_ch0), + .dwidth_conv_min_ch1 (dwidth_conv_min_ch1), + .dwidth_conv_max_ch1 (dwidth_conv_max_ch1), + .dwidth_conv_min_ch2 (dwidth_conv_min_ch2), + .dwidth_conv_max_ch2 (dwidth_conv_max_ch2) +); + +// -------------------------- 5. 生成FSDB波形文件（Verdi可查看） -------------------------- +initial begin + $fsdbDumpfile("tb.fsdb"); // 波形文件命名为tb.fsdb + $fsdbDumpvars(0, tb_histogram_ctrl); // Dump顶层及所有子模块信号 + $fsdbDumpMDA(0, tb_histogram_ctrl); // Dump内部RAM（hist_ram_ch0/1/2）内容 +end + +// -------------------------- 6. 核心测试场景（无内部信号引用） -------------------------- +initial begin + // --------------- 步骤1：初始复位（清除不定态） --------------- + rst_n = 1'b0; + hist_rst = 1'b0; + input_pixel_type = 1'b0; + hist_wr_en_ch0 = 1'b0; + hist_wr_addr_ch0 = 8'd0; + hist_wr_en_ch1 = 1'b0; + hist_wr_addr_ch1 = 8'd0; + hist_wr_en_ch2 = 1'b0; + hist_wr_addr_ch2 = 8'd0; + histogram_low_num = 16'd2; // 找第2个有效像素作为min（跳过1个噪声点） + histogram_high_num = 16'd2; // 找第2个有效像素作为max（跳过1个噪声点） + calc_en = 1'b0; + + #(CLK_PERIOD * 5); // 复位保持5个时钟周期 + rst_n = 1'b1; // 释放全局复位 + #(CLK_PERIOD * 2); // 等待稳定 + + // --------------- 步骤2：测试直方图复位（替代原状态判断） --------------- + $display("[%0t] Test 1: Histogram Reset", $time); + hist_rst = 1'b1; // 触发直方图复位 + #(CLK_PERIOD); // 保持1个时钟周期确保状态切换 + hist_rst = 1'b0; // 释放复位 + #(CLK_PERIOD * RAM_CLEAR_CYCLES); // 等待复位完成（遍历256个地址） + #(CLK_PERIOD * 2); // 额外等待2个周期稳定 + $display("[%0t] Test 1 Done: Histogram RAM Cleared", $time); + + // --------------- 步骤3：灰度模式（Gray）写入与min/max计算 --------------- + $display("[%0t] Test 2: Gray Mode (Write + Calc min/max)", $time); + input_pixel_type = 1'b0; // 切换为Gray模式（仅CH0有效） + + // 3.1 写入Gray数据（有效像素值：10、20、30、40、50） + hist_wr_en_ch0 = 1'b1;#(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd10; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd20; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd30; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd40; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd50; #(CLK_PERIOD); + hist_wr_en_ch0 = 1'b0; // 关闭写使能 + #(CLK_PERIOD * 2); + + // 3.2 触发min/max计算（找第2个min=20，第2个max=40） + calc_en = 1'b1; + #(CLK_PERIOD); + calc_en = 1'b0; // 释放计算使能 + wait(calc_done == 1'b1); // 用输出信号判断计算完成（无需内部状态） + #(CLK_PERIOD); + + // 打印结果（预期：min_ch0=20，max_ch0=40） + $display("[%0t] Gray Mode Result: min_ch0=%0d, max_ch0=%0d (Expected: 20, 40)", + $time, dwidth_conv_min_ch0, dwidth_conv_max_ch0); + #(CLK_PERIOD * 2); + + // --------------- 步骤4：RGB模式写入与min/max计算 --------------- + $display("[%0t] Test 3: RGB Mode (Write + Calc min/max)", $time); + // 直方图复位（用时间等待替代状态判断） + hist_rst = 1'b1; + #(CLK_PERIOD); + hist_rst = 1'b0; + #(CLK_PERIOD * RAM_CLEAR_CYCLES); // 等待复位完成 + input_pixel_type = 1'b1; // 切换为RGB模式（CH0=R，CH1=G，CH2=B） + #(CLK_PERIOD * 2); + + // 4.1 写入RGB数据（R:15、25、35；G:45、55、65；B:75、85、95） + // 写R通道（CH0） + hist_wr_en_ch0 = 1'b1;#(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd15; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd25; #(CLK_PERIOD); + hist_wr_addr_ch0 = 8'd35; #(CLK_PERIOD); + hist_wr_en_ch0 = 1'b0; + + // 写G通道（CH1） + hist_wr_en_ch1 = 1'b1;#(CLK_PERIOD); + hist_wr_addr_ch1 = 8'd45; #(CLK_PERIOD); + hist_wr_addr_ch1 = 8'd55; #(CLK_PERIOD); + hist_wr_addr_ch1 = 8'd65; #(CLK_PERIOD); + hist_wr_en_ch1 = 1'b0; + + // 写B通道（CH2） + hist_wr_en_ch2 = 1'b1;#(CLK_PERIOD); + hist_wr_addr_ch2 = 8'd75; #(CLK_PERIOD); + hist_wr_addr_ch2 = 8'd85; #(CLK_PERIOD); + hist_wr_addr_ch2 = 8'd95; #(CLK_PERIOD); + hist_wr_en_ch2 = 1'b0; + #(CLK_PERIOD * 2); + + // 4.2 触发RGB模式计算（预期：R=25/25，G=55/55，B=85/85） + calc_en = 1'b1; + #(CLK_PERIOD); + calc_en = 1'b0; + wait(calc_done == 1'b1); // 用输出信号判断完成 + #(CLK_PERIOD); + + // 打印RGB结果 + $display("[%0t] RGB Mode Result: R(min=%0d, max=%0d), G(min=%0d, max=%0d), B(min=%0d, max=%0d) (Expected: R=25/25, G=55/55, B=85/85)", + $time, dwidth_conv_min_ch0, dwidth_conv_max_ch0, + dwidth_conv_min_ch1, dwidth_conv_max_ch1, + dwidth_conv_min_ch2, dwidth_conv_max_ch2); + #(CLK_PERIOD * 2); + + // --------------- 步骤5：测试“写+计算”并行触发 --------------- + $display("[%0t] Test 4: Trigger Write and Calc Simultaneously", $time); + // 直方图复位 + hist_rst = 1'b1; + #(CLK_PERIOD); + hist_rst = 1'b0; + #(CLK_PERIOD * RAM_CLEAR_CYCLES); + input_pixel_type = 1'b0; // 回到Gray模式 + #(CLK_PERIOD * 2); + + // 先写1个数据，再并行触发“写+计算” + hist_wr_en_ch0 = 1'b1; + hist_wr_addr_ch0 = 8'd5; #(CLK_PERIOD); + calc_en = 1'b1; // 同时触发计算 + hist_wr_addr_ch0 = 8'd15; #(CLK_PERIOD); + hist_wr_en_ch0 = 1'b0; + calc_en = 1'b0; + wait(calc_done == 1'b1); // 用输出信号判断完成 + #(CLK_PERIOD); + $display("[%0t] Test 4 Done: Simultaneous Trigger OK", $time); + + // --------------- 步骤6：测试完成，结束仿真 --------------- + #(CLK_PERIOD * 5); + $display("[%0t] All Tests Completed!", $time); + $finish; // 结束仿真 +end + +endmodule \ No newline at end of file diff --git a/tb/data_cache/tb_sync_fifo.v b/tb/data_cache/tb_sync_fifo.v new file mode 100644 index 0000000..92b4c92 --- /dev/null +++ b/tb/data_cache/tb_sync_fifo.v @@ -0,0 +1,156 @@ +`timescale 1ns/1ps + +module tb_sync_fifo(); + +// 参数定义，与被测试模块保持一致 +parameter DATA_WIDTH = 256; +parameter FIFO_DEPTH = 8; + +// 信号定义 +reg clk; +reg rst_n; +reg wr_en; +reg [DATA_WIDTH-1:0] wr_data; +wire full; +reg rd_en; +wire [DATA_WIDTH-1:0] rd_data; +wire empty; + +// 生成时钟，周期为10ns（100MHz） +initial begin + clk = 1'b0; + forever #5 clk = ~clk; +end + +// 实例化被测试的FIFO模块 +sync_fifo #( + .DATA_WIDTH(DATA_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH) +) u_sync_fifo ( + .clk(clk), + .rst_n(rst_n), + .wr_en(wr_en), + .wr_data(wr_data), + .full(full), + .rd_en(rd_en), + .rd_data(rd_data), + .empty(empty) +); + +// 生成FSDB波形文件 +initial begin + $fsdbDumpfile("tb.fsdb"); // 指定波形文件名称 + $fsdbDumpvars(0, tb_sync_fifo); // 记录所有层次的信号 +end + +// 测试过程 +initial begin + // 初始化所有输入信号 + rst_n = 1'b0; + wr_en = 1'b0; + wr_data = {DATA_WIDTH{1'b0}}; + rd_en = 1'b0; + + // 复位操作 + #20; + rst_n = 1'b1; + #20; + + // 测试1: 连续写入数据直到FIFO满 + $display("Test 1: Writing until FIFO is full"); + + rd_en = 1'b0; + repeat (FIFO_DEPTH + 2) begin // 多写2个验证满状态保护 + + wr_data = $urandom_range(1, 255); // 生成1-255的随机数 + wr_en = 1'b1; + @(posedge clk); + end + wr_en = 1'b0; + #20; + + // 测试2: 连续读出数据直到FIFO空 + $display("Test 2: Reading until FIFO is empty"); + wr_en = 1'b0; + @(negedge clk); + rd_en = 1'b1; + repeat (FIFO_DEPTH + 2) begin // 多读2个验证空状态保护 + + @(posedge clk); + end + rd_en = 1'b0; + #20; + + // 测试3: 同时读写操作 + $display("Test 3: Simultaneous read and write"); + + repeat (30) begin // 同时进行30次读写 + wr_en = 1'b1; + rd_en = 1'b1; + wr_data = $urandom_range(1, 255); + @(posedge clk); + end + wr_en = 1'b0; + rd_en = 1'b0; + #20; + + // 测试4: 交替读写（写入一个，读出一个） + $display("Test 4: Alternate read and write"); + repeat (10) begin + // 写入一个数据 + wr_en = 1'b1; + rd_en = 1'b0; + wr_data = $urandom_range(1, 255); + @(posedge clk); + + // 读出一个数据 + wr_en = 1'b0; + rd_en = 1'b1; + @(posedge clk); + end + wr_en = 1'b0; + rd_en = 1'b0; + #20; + + // 测试5: 部分填充后连续读写 + $display("Test 5: Partial fill then continuous read/write"); + // 先填充一半 + wr_en = 1'b1; + rd_en = 1'b0; + repeat (FIFO_DEPTH/2) begin + wr_data = $urandom_range(1, 255); + @(posedge clk); + end + + // 然后同时读写 + wr_en = 1'b1; + rd_en = 1'b1; + repeat (20) begin + wr_data = $urandom_range(1, 255); + @(posedge clk); + end + + // 最后清空FIFO + wr_en = 1'b0; + rd_en = 1'b1; + repeat (FIFO_DEPTH/2) begin + @(posedge clk); + end + rd_en = 1'b0; + #50; + + $display("All tests completed!"); + $finish; +end + +// 监控异常操作并打印信息 +always @(posedge clk) begin + if (wr_en && full) begin + $display("%t: Error: Trying to write to a full FIFO!", $time); + end + if (rd_en && empty) begin + $display("%t: Error: Trying to read from an empty FIFO!", $time); + end +end + +endmodule