cache module

sim/Makefile

@@ -0,0 +1,20 @@
+find  :
+	find ../rtl -name "*.v" >>rtl.f
+	find ../tb -name "*.v" >>tb.f
+#-------------------------------------------------------------------------------------------------------
+comp  : clean vcs
+#-------------------------------------------------------------------------------------------------------
+vcs   :
+	vcs  \
+		-f rtl.f  \
+		-f tb.f  \
+		-timescale=1ns/1ps \
+		-full64  -R  +vc  +v2k  -sverilog -debug_access+all\
+		|  tee  vcs.log 
+#-------------------------------------------------------------------------------------------------------
+verdi  :
+	verdi -f rtl.f tb.f -ssf tb.fsdb &
+#-------------------------------------------------------------------------------------------------------
+clean  :
+	 rm  -rf  *~  *.f core  csrc  simv*  vc_hdrs.h  ucli.key  urg* *.log  novas.* *.fsdb* verdiLog  64* DVEfiles *.vpd
+#-------------------------------------------------------------------------------------------------------