cache module
This commit is contained in:
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.daidir_complete
Normal file
0
sim/simv.daidir/.normal_done
Normal file
0
sim/simv.daidir/.normal_done
Normal file
129
sim/simv.daidir/.vcs.timestamp
Normal file
129
sim/simv.daidir/.vcs.timestamp
Normal file
@@ -0,0 +1,129 @@
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0
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34
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+itf+/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
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+v2k
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+vc
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+vcsd1
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+vpi
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-Mamsrun=
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-Masflags=
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-Mcc=gcc
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-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs-mx/O-2018.09-1/include
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-Mcplusplus=g++
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-Mcrt0=
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-Mcrtn=
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-Mcsrc=
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-Mexternalobj=
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-Mldflags= -rdynamic
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-Mobjects= /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
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-Mout=simv
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-Msaverestoreobj=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o
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-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
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-Mvcsaceobjs=
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-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs-mx/O-2018.09-1/include
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-P
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-Xvcs_run_simv=1
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-debug_access+all
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-f rtl.f
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-f tb.f
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-fsdb
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-full64
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-gen_obj
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-picarchive
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-sverilog
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-timescale=1ns/1ps
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/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcs1
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/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
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71
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sysc_uni_pwd=/home/ICer/ic_prjs/IPA/sim
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XILINX_VIVADO=/home/Xilinx/Vivado/2019.1
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XDG_SESSION_ID=2
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XDG_RUNTIME_DIR=/run/user/1000
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XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
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VSCODE_IPC_HOOK_CLI=/run/user/1000/vscode-ipc-1591ffa4-a3ad-479f-90eb-871a7ef0f2ac.sock
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VSCODE_GIT_IPC_HANDLE=/run/user/1000/vscode-git-07cba0c96a.sock
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VSCODE_GIT_ASKPASS_NODE=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/node
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VSCODE_GIT_ASKPASS_MAIN=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass-main.js
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VSCODE_GIT_ASKPASS_EXTRA_ARGS=
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VMR_MODE_FLAG=64
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VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
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VCS_MX_HOME_INTERNAL=1
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VCS_MODE_FLAG=64
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VCS_HOME=/home/synopsys/vcs-mx/O-2018.09-1
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VCS_DEPTH=0
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VCS_ARG_ADDED_FOR_TMP=1
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VCS_ARCH_OVERRIDE=linux
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VCS_ARCH=linux64
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UNAME=/bin/uname
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TOOL_HOME=/home/synopsys/vcs-mx/O-2018.09-1/linux64
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TERM_PROGRAM_VERSION=1.85.2
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TERM_PROGRAM=vscode
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SYNPLIFY_HOME=/home/synopsys/fpga/N-2018.03-SP1
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SSH_CONNECTION=192.168.223.1 58217 192.168.223.129 22
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SSH_CLIENT=192.168.223.1 58217 22
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SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
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SPECMAN_HOME=/home/cadence/INCISIVE152/components/sn
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SPECMAN_DIR=/home/cadence/INCISIVE152/components/sn/
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SELINUX_USE_CURRENT_RANGE=
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SELINUX_ROLE_REQUESTED=
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SELINUX_LEVEL_REQUESTED=
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SCRNAME=vcs
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SCRIPT_NAME=vcs
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SCL_HOME=/home/synopsys/scl/2018.06
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RISCV=/home/Riscv_Tools
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QUESTASIM_HOME=/home/mentor/questasim
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QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
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QT_GRAPHICSSYSTEM_CHECKED=1
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QTLIB=/usr/lib/qt-3.3/lib
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QTINC=/usr/lib/qt-3.3/include
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QTDIR=/usr/lib/qt-3.3
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QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
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PT_HOME=/home/synopsys/pts/O-2018.06-SP1
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OVA_UUM=0
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MMSIMHOME=/home/cadence/MMSIM151
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MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
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MGC_LICENSE_FILE=/home/mentor//license/license.dat
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MGC_HOME=/home/mentor/
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MGC_CALIBRE_SCHEMATIC_SERVER=IC_EDA:9199
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MGC_CALIBRE_LAYOUT_SERVER=IC_EDA:9189
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MFLAGS=
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MAKE_TERMOUT=/dev/pts/1
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MAKE_TERMERR=/dev/pts/1
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MAKELEVEL=1
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MAKEFLAGS=
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LESSOPEN=||/usr/bin/lesspipe.sh %s
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LC_HOME=/home/synopsys/lc/O-2018.06-SP1
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LC_ALL=C
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KDEDIRS=/usr
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INCISIVE_HOME=/home/cadence/INCISIVE152
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ICC2_HOME=/home/synopsys/icc2/O-2018.06-SP1
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HISTCONTROL=ignoredups
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GIT_ASKPASS=/home/ICer/.vscode-server/bin/8b3775030ed1a69b13e4f4c628c612102e30a681/extensions/git/dist/askpass.sh
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DVE_HOME=/home/synopsys/vcs-mx/O-2018.09-1
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DC_HOME=/home/synopsys/syn/O-2018.06-SP1
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COLORTERM=truecolor
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CDS_LIC_FILE=/home/cadence/license/cadence.dat
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CDSHOME=/home/cadence/IC617
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CALIBRE_HOME=/home/mentor//Calibre2015/aoi_cal_2015.2_36.27
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CADHOME=/home/cadence
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0
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12
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1756197905 ../tb/data_cache/tb_data_cache.v
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1756194528 ../rtl/data_cache/data_cache.v
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1756115099 ../rtl/data_cache/rst_sync.v
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1756112329 ../rtl/data_cache/axi_write_ctrl.v
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1756197232 ../rtl/data_cache/data_assemble.v
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1756109175 ../rtl/data_cache/histogram_ctrl.v
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1756107950 ../rtl/data_cache/async_fifo.v
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1756106550 ../rtl/data_cache/sync_fifo.v
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1756197951 tb.f
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1756197943 rtl.f
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1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
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1539400757 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcsdp_lite.tab
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4
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1539402341 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvirsim.so
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1539401183 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/liberrorinf.so
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1539401125 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libsnpsmalloc.so
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1539401175 /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/libvfs.so
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1756197957 simv.daidir
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-1 partitionlib
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BIN
sim/simv.daidir/_16331_archive_1.so
Executable file
BIN
sim/simv.daidir/_16331_archive_1.so
Executable file
Binary file not shown.
BIN
sim/simv.daidir/binmap.sdb
Normal file
BIN
sim/simv.daidir/binmap.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/build_db
Executable file
4
sim/simv.daidir/build_db
Executable file
@@ -0,0 +1,4 @@
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#!/bin/sh -e
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# This file is automatically generated by VCS. Any changes you make
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# to it will be overwritten the next time VCS is run.
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vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' -static_dbgen_only -daidir=$1 2>&1
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7
sim/simv.daidir/cc/cc_bcode.db
Normal file
7
sim/simv.daidir/cc/cc_bcode.db
Normal file
@@ -0,0 +1,7 @@
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sid tb_data_cache
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bcid 0 0 WIDTH,4 OPT_CONST,0 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU CALL_ARG_VAL,4,0 NOT OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,1 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,26 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,2 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU WIDTH,16 CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU WIDTH,16 CALL_ARG_VAL,8,0 CALL_ARG_VAL,9,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,3 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,3 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,4 WIDTH,1 CALL_ARG_VAL,10,0 CALL_ARG_VAL,11,0 NOT AND OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,4 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,5 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 WIDTH,4 OPT_CONST,5 WIDTH,3 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 EQU CALL_ARG_VAL,13,0 OPT_CONST,1 EQU WIDTH,3 OPT_CONST,1 OPT_CONST,5 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
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bcid 1 1 WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OR OR OPT_CONST,1 EQU WIDTH,2 OPT_CONST,2 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU CALL_ARG_VAL,3,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,7,0 OPT_CONST,1 EQU WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,8 CALL_ARG_VAL,8,0 OPT_CONST,255 WIDTH,1 M_EQU OPT_CONST,1 EQU WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
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||||
bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,3 CALL_ARG_VAL,3,0 WIDTH,4 PAD OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 NOT AND AND RET
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||||
bcid 3 3 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,11 SHIFT_R XOR RET
|
||||
bcid 4 4 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,11 SLICE,1 WIDTH,1 M_EQU AND RET
|
||||
bcid 5 5 WIDTH,12 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET
|
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
2
sim/simv.daidir/cc/cc_dummy_file
Normal file
@@ -0,0 +1,2 @@
|
||||
Dummy_file
|
||||
Missing line/file info
|
20
sim/simv.daidir/cgname.json
Normal file
20
sim/simv.daidir/cgname.json
Normal file
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
3
|
||||
],
|
||||
"tb_data_cache": [
|
||||
"tb_data_cache",
|
||||
"EULYA",
|
||||
"module",
|
||||
2
|
||||
]
|
||||
}
|
0
sim/simv.daidir/covg_defs
Normal file
0
sim/simv.daidir/covg_defs
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
4
sim/simv.daidir/debug_dump/.version
Normal file
@@ -0,0 +1,4 @@
|
||||
O-2018.09-1_Full64
|
||||
Build Date = Oct 12 2018 20:38:10
|
||||
RedHat
|
||||
Compile Location: /home/ICer/ic_prjs/IPA/sim
|
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/HsimSigOptDb.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
0
sim/simv.daidir/debug_dump/dumpcheck.db
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
BIN
sim/simv.daidir/debug_dump/dve_debug.db.gz
Normal file
Binary file not shown.
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
9
sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db
Executable file
@@ -0,0 +1,9 @@
|
||||
#!/bin/sh -h
|
||||
PYTHONHOME=/home/synopsys/vcs-mx/O-2018.09-1/etc/search/pyh
|
||||
export PYTHONHOME
|
||||
PYTHONPATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib:/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs-mx/O-2018.09-1/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_s87tOh.xml.gz" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
57
sim/simv.daidir/debug_dump/fsearch/check_fsearch_db
Executable file
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh -h
|
||||
|
||||
FILE_PATH="/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch"
|
||||
lockfile="${FILE_PATH}"/lock
|
||||
|
||||
FSearch_lock_release() {
|
||||
echo "" > /dev/null
|
||||
}
|
||||
create_fsearch_db_ctrl() {
|
||||
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
|
||||
if [ -s "${FILE_PATH}"/fsearch.log ]; then
|
||||
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
|
||||
else
|
||||
cat "${FILE_PATH}"/fsearch.stat
|
||||
fi
|
||||
return
|
||||
fi
|
||||
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
|
||||
MY_PID=`echo $!`
|
||||
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
|
||||
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
|
||||
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
|
||||
return
|
||||
}
|
||||
|
||||
dir_name=`/bin/dirname "$0"`
|
||||
if [ "${dir_name}" = "." ]; then
|
||||
cd $dir_name
|
||||
dir_name=`/bin/pwd`
|
||||
fi
|
||||
if [ -d "$dir_name"/../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../..
|
||||
fi
|
||||
|
||||
if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
||||
trap FSearch_lock_release EXIT
|
||||
(
|
||||
flock 193
|
||||
create_fsearch_db_ctrl "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
exit 193
|
||||
) 193> "$lockfile"
|
||||
rstat=$?
|
||||
if [ "${rstat}"x != "193x" ]; then
|
||||
exit $rstat
|
||||
fi
|
||||
else
|
||||
"/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
elif [ -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/ic_prjs/IPA/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
0
sim/simv.daidir/debug_dump/fsearch/fsearch.stat
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_s87tOh.xml.gz
Normal file
Binary file not shown.
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
BIN
sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz
Normal file
Binary file not shown.
8
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
8
sim/simv.daidir/debug_dump/src_files_verilog
Normal file
@@ -0,0 +1,8 @@
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/async_fifo.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/axi_write_ctrl.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/data_assemble.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/data_cache.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/histogram_ctrl.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/rst_sync.v
|
||||
/home/ICer/ic_prjs/IPA/rtl/data_cache/sync_fifo.v
|
||||
/home/ICer/ic_prjs/IPA/tb/data_cache/tb_data_cache.v
|
1
sim/simv.daidir/debug_dump/topmodules
Normal file
1
sim/simv.daidir/debug_dump/topmodules
Normal file
@@ -0,0 +1 @@
|
||||
<02>E<EFBFBD>d
|
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
BIN
sim/simv.daidir/debug_dump/vir.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/eblklvl.db
Normal file
BIN
sim/simv.daidir/eblklvl.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
BIN
sim/simv.daidir/elabmoddb.sdb
Normal file
Binary file not shown.
78
sim/simv.daidir/external_functions
Normal file
78
sim/simv.daidir/external_functions
Normal file
@@ -0,0 +1,78 @@
|
||||
pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC
|
||||
pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC
|
||||
pli $dumpportson DumpPortsOnCALL - DumpPortsMISC
|
||||
pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC
|
||||
pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC
|
||||
pli $simlearn simLearnCall simLearnCheck simLearnMisc
|
||||
pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC
|
||||
pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC
|
||||
pli $countdrivers CountDriversCALL - -
|
||||
pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC
|
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
BIN
sim/simv.daidir/hslevel_callgraph.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_level.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
BIN
sim/simv.daidir/hslevel_rtime_level.sdb
Normal file
Binary file not shown.
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
0
sim/simv.daidir/hsscan_cfg.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
BIN
sim/simv.daidir/nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcc.sdb
Normal file
BIN
sim/simv.daidir/pcc.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
BIN
sim/simv.daidir/pcxpxmr.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/prof.sdb
Normal file
BIN
sim/simv.daidir/prof.sdb
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.dat
Normal file
BIN
sim/simv.daidir/rmapats.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/rmapats.so
Executable file
BIN
sim/simv.daidir/rmapats.so
Executable file
Binary file not shown.
1
sim/simv.daidir/saifNetInfo.db
Normal file
1
sim/simv.daidir/saifNetInfo.db
Normal file
@@ -0,0 +1 @@
|
||||
0
|
16
sim/simv.daidir/simv.kdb
Normal file
16
sim/simv.daidir/simv.kdb
Normal file
@@ -0,0 +1,16 @@
|
||||
rc file Version 1.0
|
||||
|
||||
[Design]
|
||||
COMPILE_PATH=/home/ICer/ic_prjs/IPA/sim
|
||||
SystemC=FALSE
|
||||
UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=tb_data_cache
|
||||
OPTION=-ssv -ssy
|
||||
ELAB_OPTION=-ssv -ssy
|
||||
|
||||
[Value]
|
||||
WREALX=ffff534e50535f58
|
||||
WREALZ=ffff534e50535f5a
|
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
BIN
sim/simv.daidir/stitch_nsparam.dat
Normal file
Binary file not shown.
BIN
sim/simv.daidir/tt.sdb
Normal file
BIN
sim/simv.daidir/tt.sdb
Normal file
Binary file not shown.
4
sim/simv.daidir/vcs_rebuild
Executable file
4
sim/simv.daidir/vcs_rebuild
Executable file
@@ -0,0 +1,4 @@
|
||||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-f' 'rtl.f' '-f' 'tb.f' '-timescale=1ns/1ps' '-full64' '-R' '+vc' '+v2k' '-sverilog' '-debug_access+all' 2>&1
|
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
673
sim/simv.daidir/vcselab_master_hsim_elabout.db
Normal file
@@ -0,0 +1,673 @@
|
||||
hsDirType 1
|
||||
fHsimDesignHasDebugNodes 61
|
||||
fNSParam 1024
|
||||
fLargeSizeSdfTest 0
|
||||
fHsimDelayGateMbme 0
|
||||
fNoMergeDelays 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimCertRaptMode 0
|
||||
fSharedMasterElab 0
|
||||
hsimLevelizeDone 1
|
||||
fHsimCompressDiag 1
|
||||
fHsimPowerOpt 0
|
||||
fLoopReportElab 0
|
||||
fHsimRtl 0
|
||||
fHsimCbkOptVec 1
|
||||
fHsimDynamicCcnHeur 1
|
||||
fHsimPvcs 0
|
||||
fHsimPvcsCcn 0
|
||||
fHsimOldLdr 0
|
||||
fHsimSingleDB 1
|
||||
uVfsGcLimit 50
|
||||
fHsimCompatSched 0
|
||||
fHsimCompatOrder 0
|
||||
fHsimTransUsingdoMpd32 0
|
||||
fHsimDynamicElabForGates 1
|
||||
fHsimDynamicElabForVectors 0
|
||||
fHsimDynamicElabForVectorsAlways 0
|
||||
fHsimDynamicElabForVectorsMinputs 0
|
||||
fHsimDeferForceSelTillReElab 0
|
||||
fHsimModByModElab 1
|
||||
fSvNettRealResType 0
|
||||
fHsimExprID 1
|
||||
fHsimSequdpon 0
|
||||
fHsimDatapinOpt 0
|
||||
fHsimExprPrune 0
|
||||
fHsimMimoGate 0
|
||||
fHsimNewChangeCheckFrankch 1
|
||||
fHsimNoSched0Front 0
|
||||
fHsimNoSched0FrontForMd 1
|
||||
fHsimScalReg 0
|
||||
fHsimNtbVl 0
|
||||
fHsimICTimeStamp 0
|
||||
fHsimICDiag 0
|
||||
fHsimNewCSDF 1
|
||||
vcselabIncrMode 2
|
||||
fHsimMPPackDelay 0
|
||||
fHsimMultDriver 0
|
||||
fHsimPart 0
|
||||
fHsimPrlComp 0
|
||||
fHsimPartTest 0
|
||||
fHsimTestChangeCheck 0
|
||||
fHsimTestFlatNodeOrder 0
|
||||
fHsimTestNState 0
|
||||
fHsimPartDebug 0
|
||||
fHsimPartFlags 0
|
||||
fHsimOdeSched0 0
|
||||
fHsimNewRootSig 1
|
||||
fHsimDisableRootSigModeOpt 0
|
||||
fHsimTestRootSigModeOpt 0
|
||||
fHsimIncrWriteOnce 0
|
||||
fHsimUnifInterfaceFlow 1
|
||||
fHsimUnifInterfaceFlowDiag 0
|
||||
fHsimUnifInterfaceFlowXmrDiag 0
|
||||
fHsimUnifInterfaceMultiDrvChk 1
|
||||
fHsimXVirForGenerateScope 0
|
||||
fHsimCongruencyIntTestI 0
|
||||
fHsimCongruencySVA 0
|
||||
fHsimCongruencySVADbg 0
|
||||
fHsimCongruencyLatchEdgeFix 0
|
||||
fHsimCongruencyFlopEdgeFix 0
|
||||
fHsimCongruencyXprop 0
|
||||
fHsimCongruencyXpropFix 0
|
||||
fHsimCongruencyXpropDbsEdge 0
|
||||
fHsimCongruencyResetRecoveryDbs 0
|
||||
fHsimCongruencyClockControlDiag 0
|
||||
fHsimCongruencySampleUpdate 0
|
||||
fHsimCongruencyFFDbsFix 0
|
||||
fHsimCongruency 0
|
||||
fHsimCongruencySlave 0
|
||||
fHsimCongruencyCombinedLoads 0
|
||||
fHsimCongruencyFGP 0
|
||||
fHsimDeraceClockDataUdp 0
|
||||
fHsimDeraceClockDataLERUpdate 0
|
||||
fHsimCongruencyPC 0
|
||||
fHsimCongruencyPCInl 0
|
||||
fHsimCongruencyPCDbg 0
|
||||
fHsimCongruencyPCNoReuse 0
|
||||
fHsimCongruencyDumpHier 0
|
||||
fHsimCongruencyResolution 0
|
||||
fHsimCongruencyEveBus 0
|
||||
fHsimHcExpr 0
|
||||
fHsCgOptModOpt 0
|
||||
fHsCgOptSlowProp 0
|
||||
fHsimCcnOpt 1
|
||||
fHsimCcnOpt2 1
|
||||
fHsimCcnOpt3 0
|
||||
fHsimSmdMap 0
|
||||
fHsimSmdDiag 0
|
||||
fHsimSmdSimProf 0
|
||||
fHsimSgdDiag 0
|
||||
fHsimRtDiagLite 0
|
||||
fHsimRtDiagLiteCevent 100
|
||||
fHsimRtDiag 0
|
||||
fHsimSkRtDiag 0
|
||||
fHsimDDBSRtdiag 0
|
||||
fHsimDbg 0
|
||||
fHsimCompWithGates 0
|
||||
fHsimMdbDebugOpt 0
|
||||
fHsimMdbDebugOptP1 0
|
||||
fHsimMdbDebugOptP2 0
|
||||
fHsimMdbPruneOpt 1
|
||||
fHsimMdbMemOpt 0
|
||||
hsimRandValue 0
|
||||
fHsimSimMemProfile 0
|
||||
fHsimSimTimeProfile 0
|
||||
fHsimElabMemProfile 0
|
||||
fHsimElabTimeProfile 0
|
||||
fHsimElabMemNodesProfile 0
|
||||
fHsimElabMemAllNodesProfile 0
|
||||
fHsimDisableVpdGatesProfile 0
|
||||
fHsimFileProfile 0
|
||||
fHsimCountProfile 0
|
||||
fHsimXmrDefault 1
|
||||
fHsimFuseWireAndReg 0
|
||||
fHsimFuseSelfDrvLogic 0
|
||||
fHsimFuseProcess 0
|
||||
fHsimAllXmrs 1
|
||||
fHsimMvsimDb 0
|
||||
fHsimTaskFuncXmrs 0
|
||||
fHsimTaskFuncXmrsDbg 0
|
||||
fHsimAllTaskFuncXmrs 0
|
||||
fHsimPageArray 16383
|
||||
fHsimPageControls 16383
|
||||
hsDfsNodePageElems 0
|
||||
hsNodePageElems 0
|
||||
hsFlatNodePageElems 0
|
||||
hsGateMapPageElems 0
|
||||
hsGateOffsetPageElems 0
|
||||
hsGateInputOffsetPageElems 0
|
||||
hsDbsOffsetPageElems 0
|
||||
hsMinPulseWidthPageElems 0
|
||||
hsNodeUpPatternPageElems 0
|
||||
hsNodeDownPatternPageElems 0
|
||||
hsNodeUpOffsetPageElems 0
|
||||
hsNodeEblkOffsetPageElems 0
|
||||
hsNodeDownOffsetPageElems 0
|
||||
hsNodeUpdateOffsetPageElems 0
|
||||
hsSdfOffsetPageElems 0
|
||||
fHsimPageAllLevelData 0
|
||||
fHsimAggrCg 0
|
||||
fHsimViWire 1
|
||||
fHsimPcCbOpt 1
|
||||
fHsimAmsTunneling 0
|
||||
fHsimAmsTunnelingDiag 0
|
||||
fHsimScUpwardXmrNoSplit 1
|
||||
fHsimOrigNdbViewOnly 0
|
||||
fHsimVcsInterface 1
|
||||
fHsimVcsInterfaceAlias 1
|
||||
fHsimSVTypesIntf 1
|
||||
fUnifiedAssertCtrlDiag 0
|
||||
fHsimEnable2StateScal 0
|
||||
fHsimDisable2StateScalIbn 0
|
||||
fHsimVcsInterfaceAliasDbg 0
|
||||
fHsimVcsInterfaceDbg 0
|
||||
fHsimVcsVirtIntfDbg 0
|
||||
fHsimVcsAllIntfVarMem 0
|
||||
fHsimCheckVIDynLoadOffsets 0
|
||||
fHsimModInline 1
|
||||
fHsimModInlineDbg 0
|
||||
fHsimPCDrvLoadDbg 0
|
||||
fHsimDrvChk 1
|
||||
fHsimRtlProcessingNeeded 0
|
||||
fHsimGrpByGrpElab 0
|
||||
fHsimGrpByGrpElabMaster 0
|
||||
fHsimNoParentSplitPC 0
|
||||
fHsimNusymMode 0
|
||||
fHsimOneIntfPart 0
|
||||
fHsimCompressInSingleDb 2
|
||||
fHsimCompressFlatDb 0
|
||||
fHsimNoTime0Sched 1
|
||||
fHsimMdbVectorizeInstances 0
|
||||
fHsimMdbSplitGates 0
|
||||
fHsimDeleteInstances 0
|
||||
fHsimUserDeleteInstances 0
|
||||
fHsimDeleteGdb 0
|
||||
fHsimDeleteInstancesMdb 0
|
||||
fHsimShortInstMap 0
|
||||
fHsimMdbVectorizationDump 0
|
||||
fHsimScanVectorize 0
|
||||
fHsimParallelScanVectorize 0
|
||||
noInstsInVectorization 0
|
||||
cHsimNonReplicatedInstances 0
|
||||
fHsimScanRaptor 0
|
||||
fHsimConfigFileCount 0
|
||||
fHsimVectorConstProp 0
|
||||
fHsimPromoteParam 0
|
||||
fHsimNoVecInRaptor 0
|
||||
fRaptorDumpVal 0
|
||||
fRaptorVecNodes 0
|
||||
fRaptorVecNodes2 0
|
||||
fRaptorNonVecNodes 0
|
||||
fRaptorBdrNodes 0
|
||||
fRaptorVecGates 0
|
||||
fRaptorNonVecGates 0
|
||||
fRaptorTotalNodesBeforeVect 0
|
||||
fRaptorTotalGatesBeforeVect 0
|
||||
fHsimCountRaptorBits 0
|
||||
fHsimNewEvcd 1
|
||||
fHsimNewEvcdMX 0
|
||||
fHsimNewEvcdVecRoot 1
|
||||
fHsimNewEvcdForce 1
|
||||
fHsimNewEvcdTest 0
|
||||
fHsimNewEvcdObnDrv 1
|
||||
fHsimNewEvcdW 1
|
||||
fHsimNewEvcdWTest 0
|
||||
fHsimEvcdDbgFlags 0
|
||||
fHsimDumpOffsetData 1
|
||||
fFlopGlitchDetect 0
|
||||
fHsimClkGlitch 0
|
||||
fHsimGlitchDumpOnce 0
|
||||
fHsimDynamicElab 1
|
||||
fHsimCgVectors2Debug 0
|
||||
fHsimOdeDynElab 0
|
||||
fHsimOdeDynElabDiag 0
|
||||
fHsimOdeSeqUdp 0
|
||||
fHsimOdeSeqUdpXEdge 0
|
||||
fHsimOdeSeqUdpDbg 0
|
||||
fHsimOdeRmvSched0 0
|
||||
fHsimAllLevelSame 0
|
||||
fHsimRtlDbsList 0
|
||||
fHsimPePort 0
|
||||
fHsimPeXmr 0
|
||||
fHsimPePortDiag 0
|
||||
fHsimUdpDbs 0
|
||||
fHsimRemoveDbgCaps 0
|
||||
fFsdbGateOnepassTraverse 0
|
||||
fHsimAllowVecGateInVpd 1
|
||||
fHsimAllowAllVecGateInVpd 0
|
||||
fHsimAllowUdpInVpd 1
|
||||
fHsimAllowAlwaysCombInVpd 1
|
||||
fHsimAllowAlwaysCombCmpDvcSimv 0
|
||||
fHsimAllowAlwaysCombDbg 0
|
||||
fHsimMakeAllP2SPrimary 0
|
||||
fHsimMakeAllSeqPrimary 0
|
||||
fHsimNoCcnDump 0
|
||||
fHsimFsdbProfDiag 0
|
||||
fVpdSeqGate 0
|
||||
fVpdHsIntVecGate 0
|
||||
fVpdHsCmplxVecGate 0
|
||||
fVpdHsVecGateDiags 0
|
||||
fSeqGateCodePatch 0
|
||||
fVpdLongFaninOpt 0
|
||||
fVpdSeqLongFaninOpt 0
|
||||
fVpdNoLoopDetect 0
|
||||
fVpdNoSeqLoopDetect 0
|
||||
fVpdOptAllowConstDriver 0
|
||||
fVpdAllowCellReconstruction 0
|
||||
fVpdRtlForSharedLib 0
|
||||
fHsimVpdOptGate 1
|
||||
fHsimVpdOptDelay 0
|
||||
fHsimVpdOptMPDelay 0
|
||||
fHsimCbkOptDiag 0
|
||||
fHsimSK 0
|
||||
fHsimSharedKernel 1
|
||||
fHsimOnepass 0
|
||||
fHsimStitchNew 0
|
||||
fHsimParallelLevelize 0
|
||||
fHsimParallelLevelizeDbg 0
|
||||
fHsimSeqUdpDbsByteArray 0
|
||||
fHsimCoLocate 0
|
||||
fHsimSeqUdpEblkOpt 0
|
||||
fHsimSeqUdpEblkOptDiag 0
|
||||
fHsimGateInputAndDbsOffsetsOpt 1
|
||||
fHsimUdpDynElab 0
|
||||
fHsimCompressData 4
|
||||
fHsimIgnoreZForDfuse 1
|
||||
fHsimIgnoreDifferentCaps 0
|
||||
fHandleGlitchQC 1
|
||||
fGlitchDetectForAllRtlLoads 0
|
||||
fHsimFuseConstDriversOpt 1
|
||||
fHsimIgnoreReElab 0
|
||||
fHsimFuseMultiDrivers 0
|
||||
fHsimNoSched0Reg 0
|
||||
fHsimAmsFusionEnabled 0
|
||||
fHsimRtlDbs 0
|
||||
fHsimWakeupId 0
|
||||
fHsimPassiveIbn 0
|
||||
fHsimBcOpt 1
|
||||
fHsimCertitude 0
|
||||
fHsimCertRapAutoTest 0
|
||||
fHsimRaceDetect 0
|
||||
fCheckTcCond 0
|
||||
fHsimScanOptRelaxDbg 0
|
||||
fHsimScanOptRelaxDbgDynamic 0
|
||||
fHsimScanOptRelaxDbgDynamicPli 0
|
||||
fHsimScanOptRelaxDbgDiag 0
|
||||
fHsimScanOptRelaxDbgDiagHi 0
|
||||
fHsimScanOptNoErrorOnPliAccess 0
|
||||
fHsimScanOptTiming 0
|
||||
fRelaxIbnSchedCheck 0
|
||||
fHsimScanOptNoDumpCombo 0
|
||||
fHsimScanOptPrintSwitchState 0
|
||||
fHsimScanOptSelectiveSwitchOn 0
|
||||
fHsimScanOptSingleSEPliOpt 1
|
||||
fHsimScanOptDesignHasDebugAccessOnly 0
|
||||
fHsimScanOptPrintPcode 0
|
||||
fHsimScanDbgPerf 0
|
||||
fHsimNoStitchMap 0
|
||||
fHsimUnifiedModName 0
|
||||
fHsimCbkMemOptDebug 0
|
||||
fHsimMasterModuleOnly 0
|
||||
fHsimMdbOptimizeSelects 0
|
||||
fHsimMdbScalarizePorts 0
|
||||
fHsimMdbOptimizeSelectsHeuristic 1
|
||||
fHsimMdb1006Partition 0
|
||||
fHsimVectorPgate 0
|
||||
fHsimNoHs 0
|
||||
fHsimXmrPartition 0
|
||||
fHsimNewPartition 0
|
||||
fHsimElabPart 0
|
||||
fHsimNewPartTHold 0
|
||||
fHsimParitionCellInstNum 1000
|
||||
fHsimParitionCellNodeNum 1000
|
||||
fHsimParitionCellXMRNum 1000
|
||||
fHsimNewPartCutSingleInstLimit 268435455
|
||||
fHsimElabModDistNum 0
|
||||
fHsimNewPartAutoUpperLimit 0
|
||||
fHsimPCPortPartition 0
|
||||
fHsimPortPartition 0
|
||||
fHsimDumpMdb 0
|
||||
fHsimElabDiag 0
|
||||
fHsimSimpCollect 0
|
||||
fHsimPcodeDiag 0
|
||||
fHsimFastelab 0
|
||||
fHsimMacroOpt 0
|
||||
fHsimSkipOpt 0
|
||||
fHsimSkipOptFanoutlimit 0
|
||||
fHsimSkipOptRootlimit 0
|
||||
fHsimFuseDelayChains 0
|
||||
fFusempchainsFanoutlimit 0
|
||||
fFusempchainsDiagCount 0
|
||||
fHsimCgVectorGates 0
|
||||
fHsimCgVectorGates1 0
|
||||
fHsimCgVectorGates2 0
|
||||
fHsimCgVectorGatesNoReElab 0
|
||||
fHsimCgScalarGates 0
|
||||
fHsimCgScalarGatesExpr 0
|
||||
fHsimCgScalarGatesLut 0
|
||||
fHsimCgRtl 1
|
||||
fHsimCgRtlFilter 0
|
||||
fHsimCgRtlDebug 0
|
||||
fHsimCgRtlSize 15
|
||||
fHsimNewCgRt 0
|
||||
fHsimNewCgMPRt 0
|
||||
fHsimNewCgMPRetain 0
|
||||
fHsimCgRtlInfra 1
|
||||
fHsimGlueOpt 0
|
||||
fHsimPGatePatchOpt 0
|
||||
fHsimCgNoPic 0
|
||||
fHsimElabModCg 0
|
||||
fPossibleNullChecks 0
|
||||
fHsimProcessNoSplit 1
|
||||
fHsimMdbOptInSchedDelta 0
|
||||
fScaleTimeValue 0
|
||||
fDebugTimeScale 0
|
||||
fPartCompSDF 0
|
||||
fHsimNbaGate 1
|
||||
fDumpSDFBasedMod 1
|
||||
fOptimisticNtcSolver 0
|
||||
fHsimAllMtm 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimSdgOptEnable 0
|
||||
fHsimSVTypesRefPorts 0
|
||||
fHsimGrpByGrpElabIncr 0
|
||||
fHsimMarkRefereeInVcsElab 0
|
||||
fHsimStreamOpFix 1
|
||||
fHsimInterface 0
|
||||
fHsimMxWrapOpt 0
|
||||
fHsimMxTopBdryOpt 0
|
||||
fHsimClasses 0
|
||||
fHsimAggressiveDce 0
|
||||
fHsimDceDebug 1
|
||||
fHsimDceDebugUseHeuristics 1
|
||||
fHsimMdbNewDebugOpt 0
|
||||
fHsimMdbNewDebugOptExitOnError 1
|
||||
fHsimNewDebugOptMemDiag 0
|
||||
hsGlobalVerboseLevel 0
|
||||
fHsimMdbVectorConstProp 1
|
||||
fHsimEnableSeqUdpWrite 1
|
||||
fHsimDumpMDBOnlyForSeqUdp 0
|
||||
fHsimInitRegRandom 0
|
||||
fHsimInitRegRandomVcs 1
|
||||
fEnableNewFinalStrHash 0
|
||||
fEnableNewAssert 1
|
||||
fRunDbgDmma 0
|
||||
fAssrtCtrlSigChk 1
|
||||
fCheckSigValidity 0
|
||||
fUniqPriToAstRewrite 0
|
||||
fUniqPriToAstCtrl 0
|
||||
fAssertcontrolUniqPriNewImpl 0
|
||||
fRTLoopDectEna 0
|
||||
fCmplLoopDectEna 0
|
||||
fHsimMopFlow 1
|
||||
fUCaseLabelCtrl 0
|
||||
fUniSolRtSvaEna 1
|
||||
fUniSolSvaEna 1
|
||||
fXpropRtCtrlCallerOnly 0
|
||||
fHsimRaptorPart 0
|
||||
fHsimEnableDbsMemOpt 1
|
||||
fHsimDebugDbsMemOpt 0
|
||||
fHsimRenPart 0
|
||||
fHsimShortElabInsts 0
|
||||
fHsimXmrAllWires 0
|
||||
fHsimXmrDiag 0
|
||||
fHsimXmrPort 0
|
||||
fHsimFalcon 1
|
||||
fHsimGenForProfile 0
|
||||
fCompressSDF 0
|
||||
fDlpSvtbExclElab 0
|
||||
fHsimGates1209 0
|
||||
fHsimCgRtlNoShareSmd 0
|
||||
fHsimGenForErSum 0
|
||||
fVpdOpt 1
|
||||
fHsimMdbCell 0
|
||||
fHsimCellDebug 0
|
||||
fHsimNoPeekInMdbCell 0
|
||||
igetOpcodeSmdPtrLayoutId -1
|
||||
igetFieldSmdPtr -1
|
||||
fDebugDump 1
|
||||
fHsimOrigNodeNames 0
|
||||
fHsimCgVectors2VOnly 0
|
||||
fHsimMdbDeltaGate 0
|
||||
fHsimMdbVecDeltaGate 1
|
||||
fHsimVpdOptVfsDB 1
|
||||
fHsimMdbPruneVpdGates 1
|
||||
fHsimPcPe 0
|
||||
fHsimVpdGateOnlyFlag 1
|
||||
fHsimMxConnFrc 0
|
||||
fHsimNewForceCbkVec 0
|
||||
fHsimNewForceCbkVecDiag 0
|
||||
fHsimMdbReplaceVpdHighConn 1
|
||||
fHsimVpdOptSVTypes 1
|
||||
fHsHasPeUpXmr 0
|
||||
fHsimCompactVpdFn 1
|
||||
fHsimPIP 0
|
||||
fHsimRTLoopDectOrgName 0
|
||||
fHsimVpdOptPC 0
|
||||
fHsimFusePeXmrFo 0
|
||||
fHsimXmrSched 0
|
||||
fHsimNoMdg 0
|
||||
fHsimVectorGates 0
|
||||
fHsimRtlLite 0
|
||||
fHsimMdbcgLut 0
|
||||
fHsimMdbcgSelective 0
|
||||
fHsimVcselabGates 0
|
||||
fHsimMdbcgLevelize 0
|
||||
fHsimParGateEvalMode 0
|
||||
fHsimDFuseVectors 0
|
||||
fHsimDFuseZero 0
|
||||
fHsimDFuseOpt 1
|
||||
fHsimPruneOpt 0
|
||||
fHsimSeqUdpPruneWithConstInputs 0
|
||||
fHsimSafeDFuse 0
|
||||
fHsimVpdOptExpVec 0
|
||||
fHsimVpdOptSelGate 1
|
||||
fHsimVpdOptSkipFuncPorts 0
|
||||
fHsimVpdOptAlways 1
|
||||
fHsimVpdOptMdbCell 0
|
||||
fHsimVpdOptPartialMdb 1
|
||||
fHsimVpdOptPartitionGate 1
|
||||
fHsimVpdOptXmr 1
|
||||
fHsimVpdHilRtl 0
|
||||
fHsimSWave 0
|
||||
fHsimNoSched0InCell 1
|
||||
fHsimPartialMdb 0
|
||||
hsimPdbLargeOffsetThreshold 1048576
|
||||
fHsimFlatCell 0
|
||||
fHsimFlatCellLimit 0
|
||||
fHsimRegBank 0
|
||||
fHsimHmetisMaxPartSize 0
|
||||
fHsimHmetisGateWt 0
|
||||
fHsimHmetisUbFactor 0
|
||||
fHsimHmetis 0
|
||||
fHsimHmetisDiag 0
|
||||
fHsimRenumGatesForMdbCell 0
|
||||
fHsimHmetisMinPart 0
|
||||
fHsim2stCell 0
|
||||
fHsim2stCellMinSize 0
|
||||
fHsimMdbcgDebug 0
|
||||
fHsimMdbcgDebugLite 0
|
||||
fHsimMdbcgDistrib 0
|
||||
fHsimMdbcgSepmem 1
|
||||
fHsimMdbcgObjDiag 0
|
||||
fHsimMdbcg2stDiag 0
|
||||
fHsimMdbcgRttrace 0
|
||||
fHsimMdbVectorGateGroup 1
|
||||
fHsimMdbProcDfuse 1
|
||||
fHsimMdbHilPrune 0
|
||||
fHsCgOpt 1
|
||||
fHsCgOptUdp 1
|
||||
fHsCgOptRtl 1
|
||||
fHsCgOptDiag 0
|
||||
fHsCgOptAggr 0
|
||||
fHsCgOptNoZCheck 0
|
||||
fHsCgOptEnableZSupport 0
|
||||
fHsCgOpt4StateInfra 0
|
||||
fHsCgOptUdpChkDataForWakeup 1
|
||||
fHsCgOptXprop 0
|
||||
fHsimMdbcgDiag 0
|
||||
fHsCgMaxInputs 6
|
||||
fHsCgOptFwdPass 1
|
||||
fHsimHpnodes 0
|
||||
fLightDump 0
|
||||
fHDLCosim 0
|
||||
fHDLCosimDebug 0
|
||||
fHDLCosimTimeCoupled 0
|
||||
fHDLCosimTimeCoupledPorts 0
|
||||
HDLCosimMaxDataPerDpi 1
|
||||
HDLCosimMaxCallsPerDpi 2147483647
|
||||
fHDLCosimCompileDUT 0
|
||||
fHDLCosimCustomCompile 0
|
||||
fHDLCosimBoundaryAnalysis 0
|
||||
fVpdBeforeScan 1
|
||||
fHsCgOptMiSched0 0
|
||||
fgcAddSched0 0
|
||||
fParamClassOptRtDiag 0
|
||||
fHsRegress 0
|
||||
fHsBenchmark 0
|
||||
fHsimCgScalarVerilogForce 1
|
||||
fVcsElabToRoot 1
|
||||
fHilIbnObnCallByName 0
|
||||
fHsimMdbcgCellPartition 0
|
||||
fHsimCompressVpdSig 0
|
||||
fHsimLowPowerOpt 0
|
||||
fHsimUdpOpt 1
|
||||
fHsVecOneld 0
|
||||
fNativeVpdDebug 0
|
||||
fHsimVcsGenTLS 1
|
||||
fAssertSuccDebugLevelDump 0
|
||||
fHsimMinputsChangeCheck 0
|
||||
fHsimClkLayout 0
|
||||
fHsimIslandLayout 0
|
||||
fHsimConfigSched0 0
|
||||
fHsimSelectFuseAfterDfuse 0
|
||||
fHsimFoldedCell 0
|
||||
fHsimSWaveEmul 0
|
||||
fHsimSWaveDumpMDB 0
|
||||
fHsimSWaveDumpFlatData 0
|
||||
fHsimRenumberAlias 0
|
||||
fHsimAliasRenumbered 0
|
||||
fHilCgMode 115
|
||||
fHsimUnionOpt 0
|
||||
fHsimFuseSGDBoundaryNodes 0
|
||||
fHsimRemoveCapsVec 0
|
||||
fHsimCertRaptScal 0
|
||||
fHsimCertRaptMdbClock 0
|
||||
fHsCgOptMux 0
|
||||
fHsCgOptFrc 0
|
||||
fHsCgOpt30 0
|
||||
fHsLpNoCapsOpt 0
|
||||
fHsCgOpt4State 1
|
||||
fSkipStrChangeOnDelay 1
|
||||
fHsimTcheckOpt 0
|
||||
fHsCgOptMuxMClk 0
|
||||
fHsCgOptMuxFrc 0
|
||||
fHsCgOptNoPcb 0
|
||||
fHsCgOptMin1 0
|
||||
fHsCgOptUdpChk 0
|
||||
fHsChkXForSlowSigProp 1
|
||||
fHsimVcsParallelDbg 0
|
||||
fHsimVcsParallelStrategy 0
|
||||
fHsimVcsParallelOpt 0
|
||||
fHsimVcsParallelSubLevel 4
|
||||
fHsimParallelEblk 0
|
||||
fHsimByteCodeParts 1
|
||||
fFgpNovlInComp 0
|
||||
fFutEventPRL 0
|
||||
fFgpNbaDelay 0
|
||||
fHsimDbsFlagsByteArray 0
|
||||
fHsimDbsFlagsByteArrayTC 0
|
||||
fHsimDbsFlagsThreadArray 0
|
||||
fHsimGateEdgeEventSched 0
|
||||
fHsimEgschedDynelab 0
|
||||
fHsimUdpClkDynelab 0
|
||||
fUdpLayoutOnClk 0
|
||||
fDbsPreCheck 0
|
||||
fHsimSched0Analysis 0
|
||||
fHsimMultiDriverSched0 0
|
||||
fHsimLargeIbnSched 0
|
||||
fFgpHierarchical 0
|
||||
fFgpHierAllElabModAsRoot 0
|
||||
fFgpHierPCElabModAsRoot 0
|
||||
fFgpAdjustDataLevelOfLatch 1
|
||||
fHsimUdpXedgeEval 0
|
||||
fFgpRaceCheck 0
|
||||
fFgpUnifyClk 0
|
||||
fFgpSmallClkTree 0
|
||||
fFgpSmallRtlClkTree 4
|
||||
fFgpNoRtlUnlink 0
|
||||
fFgpNoRtlAuxLevel 0
|
||||
fFgpNumPartitions 8
|
||||
fFgpMultiSocketCompile 0
|
||||
fFgpDataDepOn 0
|
||||
fFgpDDIgnore 0
|
||||
fFgpTbCbOn 0
|
||||
fFgpTbEvOn 1
|
||||
fFgpTbNoVSA 0
|
||||
fFgpTbEvXmr 0
|
||||
fFgpDisabledLevel 512
|
||||
fFgpSched0User 0
|
||||
fFgpNoSdDelayedNbas 1
|
||||
fFgpTimingFlags 0
|
||||
fFgpSched0Level 0
|
||||
fHsimFgpMultiClock 0
|
||||
fFgpScanOptFix 0
|
||||
fFgpSched0UdpData 0
|
||||
fFgpDepositDiag 0
|
||||
fFgpEvtDiag.diagOn 0
|
||||
fFgpEvtDiag.printAllNodes 0
|
||||
fFgpMangleDiagLog 0
|
||||
fFgpMultiExclDiag 0
|
||||
fFgpSingleExclReason 0
|
||||
fHsDoFaninFanoutSanity 0
|
||||
fHsFgpNonDbsOva 1
|
||||
fFgpParallelTask 1
|
||||
fFgpIbnSched 0
|
||||
fFgpIbnSchedOpt 0
|
||||
fFgpIbnSchedThreshold 0
|
||||
fFgpIbnSchedDyn 0
|
||||
fFgpMpStateByte 0
|
||||
fFgpTcStateByte 0
|
||||
fHsimVirtIntfDynLoadSched 0
|
||||
fFgpNoRtimeFgp 0
|
||||
fHsFgpGlSched0 0
|
||||
fFgpExclReason 0
|
||||
fHsimIslandByIslandElab 0
|
||||
fHsimIslandByIslandFlat 151652416
|
||||
fHsimIslandByIslandFlat1 4
|
||||
fHsimVpdIBIF 0
|
||||
fHsimXmrIBIF 0
|
||||
fHsimReportTime 0
|
||||
fHsimElabJ 0
|
||||
hf_fHsimElabJ 0
|
||||
fHsimElabJOpt 0
|
||||
fHsimSchedMinput 0
|
||||
fHsimSchedSeqPrim 0
|
||||
fHsimSchedSelectFanout 0
|
||||
fHsimSchedSelectFanoutDebug 0
|
||||
fSpecifyInDesign 0
|
||||
fFgpDynamicReadOn 0
|
||||
fHsCgOptAllUc 0
|
||||
fHsimXmrRepl 0
|
||||
fZoix 0
|
||||
fHsimDfuseNewOpt 0
|
||||
fHsimBfuseNewOpt 0
|
||||
fFgpXmrSched 0
|
||||
fHsimClearClkCaps 0
|
||||
fHsimDiagClkConfig 0
|
||||
fHsimDiagClkConfigDebug 0
|
||||
fHsimDiagClkConfigDumpAll 0
|
||||
fHsDiagClkConfigPara 0
|
||||
fHsimDiagClkConfigAn 0
|
||||
fHsimCanDumpClkConfig 0
|
||||
fFgpInitRout 0
|
||||
fFgpIgnoreExclSD 0
|
||||
fHsCgOptNoClockFusing 0
|
||||
fHsClkWheelLimit 50000
|
||||
fHsimPCSharedLibSpecified 0
|
||||
fHsFgpSchedCgUcLoads 1
|
||||
fHsCgOptNewSelCheck 1
|
||||
fFgpReportUnsafeFuncs 0
|
||||
fHsCgOptUncPrlThreshold 4
|
||||
fHsimLowPowerRetAnalysisInChild 0
|
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsdef.db
Normal file
Binary file not shown.
1190
sim/simv.daidir/vcselab_misc_hsim_elab.db
Normal file
1190
sim/simv.daidir/vcselab_misc_hsim_elab.db
Normal file
File diff suppressed because it is too large
Load Diff
BIN
sim/simv.daidir/vcselab_misc_hsim_fegate.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_fegate.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_hsim_lvl.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_lvl.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_hsim_name.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_hsim_name.db
Normal file
Binary file not shown.
3
sim/simv.daidir/vcselab_misc_hsim_uds.db
Normal file
3
sim/simv.daidir/vcselab_misc_hsim_uds.db
Normal file
@@ -0,0 +1,3 @@
|
||||
vcselab_misc_midd.db 749
|
||||
vcselab_misc_mnmn.db 26
|
||||
vcselab_misc_hsim_name.db 217
|
BIN
sim/simv.daidir/vcselab_misc_midd.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_midd.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_mnmn.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_mnmn.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_partition.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_partition.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_vcselabref.db
Normal file
BIN
sim/simv.daidir/vcselab_misc_vcselabref.db
Normal file
Binary file not shown.
BIN
sim/simv.daidir/vcselab_misc_vpdnodenums
Normal file
BIN
sim/simv.daidir/vcselab_misc_vpdnodenums
Normal file
Binary file not shown.
Reference in New Issue
Block a user