Chronologic VCS (TM) Version O-2018.09-1_Full64 -- Tue Aug 26 16:45:55 2025 Copyright (c) 1991-2018 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file '../rtl/data_cache/sync_fifo.v' Parsing design file '../rtl/data_cache/async_fifo.v' Parsing design file '../rtl/data_cache/histogram_ctrl.v' Parsing design file '../rtl/data_cache/data_assemble.v' Parsing design file '../rtl/data_cache/axi_write_ctrl.v' Parsing design file '../rtl/data_cache/rst_sync.v' Parsing design file '../rtl/data_cache/data_cache.v' Parsing design file '../tb/data_cache/tb_data_cache.v' Top Level Modules: tb_data_cache TimeScale is 1 ns / 1 ps Warning-[PCWM-W] Port connection width mismatch ../rtl/data_cache/data_cache.v, 245 "axi_write_ctrl #(AXI_ID_W, AXI_ADDR_W, AXI_DATA_W, AXI_STRB_W, , , , ) u_axi_write_ctrl( .clk (clk), .rst_n (rst_n_sys), .start_en (((!sync_fifo_empty) && (!axi_write_busy))), .sram_base_addr (32'b0), .fifo_rd_data (sync_fifo_rd_data), .fifo_empty (sync_fifo_empty), .fifo_rd_en (sync_fifo_rd_en), .axi_m_awid (axi_m_awid), .axi_m_awaddr (axi_m_awaddr), .axi_m_awlen (axi_m_awlen), .axi_m_awsize (axi_m_awsize), .axi_m_awburst (axi_m_awburst), .axi_m_awlock (axi_m_awlock), .axi_m_awcache (axi_m_awcache), .axi_m_awprot (axi_m_awprot), .axi_m_awqos (axi_m_awqos), .axi_m_awvalid (axi_m_awvalid), .axi_m_awready (axi_m_awready), .axi_m_wid (axi_m_wid), .axi_m_wdata (axi_m_wdata), .axi_m_wstrb (axi_m_wstrb), .axi_m_wlast (axi_m_wlast), .axi_ ... " The following 4-bit expression is connected to 5-bit port "axi_m_awcache" of module "axi_write_ctrl", instance "u_axi_write_ctrl". Expression: axi_m_awcache use +lint=PCWM for more details Warning-[PCWM-W] Port connection width mismatch ../rtl/data_cache/data_cache.v, 245 "axi_write_ctrl #(AXI_ID_W, AXI_ADDR_W, AXI_DATA_W, AXI_STRB_W, , , , ) u_axi_write_ctrl( .clk (clk), .rst_n (rst_n_sys), .start_en (((!sync_fifo_empty) && (!axi_write_busy))), .sram_base_addr (32'b0), .fifo_rd_data (sync_fifo_rd_data), .fifo_empty (sync_fifo_empty), .fifo_rd_en (sync_fifo_rd_en), .axi_m_awid (axi_m_awid), .axi_m_awaddr (axi_m_awaddr), .axi_m_awlen (axi_m_awlen), .axi_m_awsize (axi_m_awsize), .axi_m_awburst (axi_m_awburst), .axi_m_awlock (axi_m_awlock), .axi_m_awcache (axi_m_awcache), .axi_m_awprot (axi_m_awprot), .axi_m_awqos (axi_m_awqos), .axi_m_awvalid (axi_m_awvalid), .axi_m_awready (axi_m_awready), .axi_m_wid (axi_m_wid), .axi_m_wdata (axi_m_wdata), .axi_m_wstrb (axi_m_wstrb), .axi_m_wlast (axi_m_wlast), .axi_ ... " The following 4-bit expression is connected to 5-bit port "axi_m_awqos" of module "axi_write_ctrl", instance "u_axi_write_ctrl". Expression: axi_m_awqos use +lint=PCWM for more details Starting vcs inline pass... 1 module and 0 UDP read. recompiling module tb_data_cache make[1]: Entering directory '/home/ICer/ic_prjs/IPA/sim/csrc' make[1]: Leaving directory '/home/ICer/ic_prjs/IPA/sim/csrc' make[1]: Entering directory '/home/ICer/ic_prjs/IPA/sim/csrc' rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-rpath=/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib -L/home/synopsys/vcs-mx/O-2018.09-1/linux64/lib objs/amcQw_d.o _16331_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/synopsys/vcs-mx/O-2018.09-1/linux64/lib/vcs_save_restore_new.o /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl ../simv up to date make[1]: Leaving directory '/home/ICer/ic_prjs/IPA/sim/csrc' Chronologic VCS simulator copyright 1991-2018 Contains Synopsys proprietary information. Compiler version O-2018.09-1_Full64; Runtime version O-2018.09-1_Full64; Aug 26 16:45 2025 *Verdi* Loading libsscore_vcs201809.so FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 (C) 1996 - 2019 by Synopsys, Inc. *Verdi* : Create FSDB file 'tb.fsdb' *Verdi* : Begin traversing the scope (tb_data_cache), layer (0). *Verdi* : End of traversing. *Verdi* : Begin traversing the MDAs under scope (tb_data_cache), layer (0). *Verdi* : Enable +mda and +packedmda dumping. *Verdi* : End of traversing the MDAs. [150000] Test 1: Gray scale single frame test [165000] Data Cache State: WAIT_VS [185000] Data Cache State: RECEIVE_DATA [595000] AXI Write Transaction: Address=0x00000000, Length= 0 [605000] AXI Write Transaction: Address=0x00000000, Length= 0 [615000] AXI Write Data: ID= 0, Data[31:0]=0x3c3d3e3f, Last=1 [935000] AXI Write Transaction: Address=0x00000020, Length= 0 [955000] AXI Write Data: ID= 0, Data[31:0]=0x5c5d5e5f, Last=1 [1285000] AXI Write Transaction: Address=0x00000040, Length= 0 [1295000] AXI Write Transaction: Address=0x00000040, Length= 0 [1305000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 [1635000] AXI Write Transaction: Address=0x00000060, Length= 0 [1655000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 [1985000] AXI Write Transaction: Address=0x00000080, Length= 0 [2015000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 [2335000] AXI Write Transaction: Address=0x000000a0, Length= 0 [2345000] AXI Write Transaction: Address=0x000000a0, Length= 0 [2355000] AXI Write Data: ID= 0, Data[31:0]=0x3b3c3d3e, Last=1 [2715000] AXI Write Transaction: Address=0x000000c0, Length= 0 [2735000] AXI Write Data: ID= 0, Data[31:0]=0x5b5c5d5e, Last=1 [3035000] AXI Write Transaction: Address=0x000000e0, Length= 0 [3045000] AXI Write Transaction: Address=0x000000e0, Length= 0 [3065000] AXI Write Data: ID= 0, Data[31:0]=0x7b7c7d7e, Last=1 [3385000] AXI Write Transaction: Address=0x00000100, Length= 0 [3435000] AXI Write Data: ID= 0, Data[31:0]=0x9b9c9d9e, Last=1 [3745000] AXI Write Transaction: Address=0x00000120, Length= 0 [3755000] AXI Write Transaction: Address=0x00000120, Length= 0 [3805000] AXI Write Data: ID= 0, Data[31:0]=0xbbbcbdbe, Last=1 [4085000] AXI Write Transaction: Address=0x00000140, Length= 0 [4095000] AXI Write Transaction: Address=0x00000140, Length= 0 [4125000] AXI Write Data: ID= 0, Data[31:0]=0x3a3b3c3d, Last=1 [4435000] AXI Write Transaction: Address=0x00000160, Length= 0 [4455000] AXI Write Data: ID= 0, Data[31:0]=0x5a5b5c5d, Last=1 [4795000] AXI Write Transaction: Address=0x00000180, Length= 0 [4805000] AXI Write Transaction: Address=0x00000180, Length= 0 [4815000] AXI Write Data: ID= 0, Data[31:0]=0x7a7b7c7d, Last=1 [5135000] AXI Write Transaction: Address=0x000001a0, Length= 0 [5155000] AXI Write Data: ID= 0, Data[31:0]=0x9a9b9c9d, Last=1 [5515000] AXI Write Transaction: Address=0x000001c0, Length= 0 [5525000] AXI Write Transaction: Address=0x000001c0, Length= 0 [5545000] AXI Write Data: ID= 0, Data[31:0]=0xbabbbcbd, Last=1 [5785000] Data Cache State: WRITE_FIFO [5795000] Data Cache State: FRAME_DONE [5835000] AXI Write Transaction: Address=0x000001e0, Length= 0 [5845000] AXI Write Transaction: Address=0x000001e0, Length= 0 [5865000] AXI Write Data: ID= 0, Data[31:0]=0x393a3b3c, Last=1 [8375000] Data Cache State: WAIT_VS [8455000] Test 1 Histogram Check: CH0 min=20 (exp=20), max=c0 (exp=c0) [8455000] Test 1 Histogram Check PASSED! [8505000] Test 2: RGB single frame test [8515000] Data Cache State: IDLE [8535000] Data Cache State: WAIT_VS [8565000] Data Cache State: RECEIVE_DATA [14165000] Data Cache State: WRITE_FIFO [14175000] Data Cache State: FRAME_DONE [16755000] Data Cache State: WAIT_VS [16835000] Test 2 Histogram Check: CH0 min=37 (exp=30), max=3f (exp=70) [16835000] Test 2 Histogram Check: CH1 min=50 (exp=50), max=6f (exp=90) [16835000] Test 2 Histogram Check: CH2 min=78 (exp=70), max=9e (exp=b0) [16835000] Test 2 Histogram Check FAILED! [16885000] Test 3: Continuous frame test [16895000] Data Cache State: IDLE [16915000] Data Cache State: WAIT_VS [16945000] Data Cache State: RECEIVE_DATA [17345000] AXI Write Transaction: Address=0x00000200, Length= 0 [17415000] AXI Write Data: ID= 0, Data[31:0]=0x5c5d5e5f, Last=1 [17695000] AXI Write Transaction: Address=0x00000220, Length= 0 [17705000] AXI Write Transaction: Address=0x00000220, Length= 0 [17725000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 [18065000] AXI Write Transaction: Address=0x00000240, Length= 0 [18075000] AXI Write Transaction: Address=0x00000240, Length= 0 [18085000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 [18395000] AXI Write Transaction: Address=0x00000260, Length= 0 [18405000] AXI Write Transaction: Address=0x00000260, Length= 0 [18435000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 [18765000] AXI Write Transaction: Address=0x00000280, Length= 0 [18775000] AXI Write Transaction: Address=0x00000280, Length= 0 [18795000] AXI Write Data: ID= 0, Data[31:0]=0xdcdddedf, Last=1 [19115000] AXI Write Transaction: Address=0x000002a0, Length= 0 [19135000] AXI Write Data: ID= 0, Data[31:0]=0x5b5c5d5e, Last=1 [19445000] AXI Write Transaction: Address=0x000002c0, Length= 0 [19455000] AXI Write Transaction: Address=0x000002c0, Length= 0 [19465000] AXI Write Data: ID= 0, Data[31:0]=0x7b7c7d7e, Last=1 [19825000] AXI Write Transaction: Address=0x000002e0, Length= 0 [19845000] AXI Write Data: ID= 0, Data[31:0]=0x9b9c9d9e, Last=1 [20175000] AXI Write Transaction: Address=0x00000300, Length= 0 [20185000] AXI Write Transaction: Address=0x00000300, Length= 0 [20215000] AXI Write Data: ID= 0, Data[31:0]=0xbbbcbdbe, Last=1 [20525000] AXI Write Transaction: Address=0x00000320, Length= 0 [20545000] AXI Write Data: ID= 0, Data[31:0]=0xdbdcddde, Last=1 [20865000] AXI Write Transaction: Address=0x00000340, Length= 0 [20885000] AXI Write Data: ID= 0, Data[31:0]=0x5a5b5c5d, Last=1 [21225000] AXI Write Transaction: Address=0x00000360, Length= 0 [21265000] AXI Write Data: ID= 0, Data[31:0]=0x7a7b7c7d, Last=1 [21545000] AXI Write Transaction: Address=0x00000380, Length= 0 [21565000] AXI Write Data: ID= 0, Data[31:0]=0x9a9b9c9d, Last=1 [21915000] AXI Write Transaction: Address=0x000003a0, Length= 0 [21925000] AXI Write Transaction: Address=0x000003a0, Length= 0 [21935000] AXI Write Data: ID= 0, Data[31:0]=0xbabbbcbd, Last=1 [22255000] AXI Write Transaction: Address=0x000003c0, Length= 0 [22265000] AXI Write Transaction: Address=0x000003c0, Length= 0 [22305000] AXI Write Data: ID= 0, Data[31:0]=0xdadbdcdd, Last=1 [22545000] Data Cache State: WRITE_FIFO [22555000] Data Cache State: FRAME_DONE [22615000] AXI Write Transaction: Address=0x000003e0, Length= 0 [22635000] AXI Write Data: ID= 0, Data[31:0]=0x595a5b5c, Last=1 [25135000] Data Cache State: WAIT_VS [25185000] Data Cache State: RECEIVE_DATA [30785000] Data Cache State: WRITE_FIFO [30795000] Data Cache State: FRAME_DONE [33375000] Data Cache State: WAIT_VS [33455000] Test 4: Update trigger test [33475000] Data Cache State: RECEIVE_DATA [33885000] AXI Write Transaction: Address=0x00000400, Length= 0 [33905000] AXI Write Data: ID= 0, Data[31:0]=0x7c7d7e7f, Last=1 [34225000] AXI Write Transaction: Address=0x00000420, Length= 0 [34255000] AXI Write Data: ID= 0, Data[31:0]=0x9c9d9e9f, Last=1 [34585000] AXI Write Transaction: Address=0x00000440, Length= 0 [34625000] AXI Write Data: ID= 0, Data[31:0]=0xbcbdbebf, Last=1 [34945000] AXI Write Transaction: Address=0x00000460, Length= 0 [34955000] AXI Write Transaction: Address=0x00000460, Length= 0 [34965000] AXI Write Data: ID= 0, Data[31:0]=0xdcdddedf, Last=1 [35275000] AXI Write Transaction: Address=0x00000480, Length= 0 [35285000] AXI Write Transaction: Address=0x00000480, Length= 0 [35295000] AXI Write Data: ID= 0, Data[31:0]=0xfcfdfeff, Last=1 [35625000] AXI Write Transaction: Address=0x000004a0, Length= 0 [35645000] AXI Write Data: ID= 0, Data[31:0]=0x1c1d1e1f, Last=1 [35945000] Data Cache State: IDLE [35985000] AXI Write Transaction: Address=0x000004c0, Length= 0 [35995000] AXI Write Transaction: Address=0x000004c0, Length= 0 [35995000] Data Cache State: WAIT_VS [36015000] AXI Write Data: ID= 0, Data[31:0]=0x3c3d3e3f, Last=1 [36076000] All tests completed! $finish called from file "../tb/data_cache/tb_data_cache.v", line 418. $finish at simulation time 36076000 V C S S i m u l a t i o n R e p o r t Time: 36076000 ps CPU Time: 0.740 seconds; Data structure size: 0.0Mb Tue Aug 26 16:45:57 2025 CPU time: .528 seconds to compile + .347 seconds to elab + .349 seconds to link + .789 seconds in simulation