451 lines
15 KiB
Verilog
451 lines
15 KiB
Verilog
`timescale 1ns/1ps
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module tb_data_cache();
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// -------------------------- 参数定义 --------------------------
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parameter ASYNC_FIFO_DEPTH = 1024;
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parameter ASYNC_FIFO_DATA_W = 27;
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parameter SYNC_FIFO_DEPTH = 2048;
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parameter SYNC_FIFO_DATA_W = 256;
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parameter HIST_RAM_DEPTH = 256;
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parameter HIST_RAM_DATA_W = 1;
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parameter AXI_ID_W = 8;
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parameter AXI_ADDR_W = 32;
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parameter AXI_DATA_W = 256;
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parameter AXI_STRB_W = AXI_DATA_W / 8;
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// 测试用图像参数
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parameter IMAGE_WIDTH = 32; // 图像宽度（32像素，便于拼接256bit）
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parameter IMAGE_HEIGHT = 16; // 图像高度
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parameter HIST_LOW_NUM = 1; // 直方图低位数量
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parameter HIST_HIGH_NUM = 1; // 直方图高位数量
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// 时钟周期定义
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parameter SYS_CLK_PERIOD = 10; // 系统时钟周期(10ns=100MHz)
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parameter IR_CLK_PERIOD = 5; // IR时钟周期(8ns=125MHz)
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// -------------------------- 信号定义 --------------------------
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// 系统时钟与复位
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reg sys_clk;
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reg ir_clk;
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reg rst_n;
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// 配置信号
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reg ipa_en;
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reg update_src_trig;
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reg input_pixel_type;
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reg [15:0] src_pixel_height;
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reg [15:0] src_pixel_width;
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reg [15:0] histogram_low_num;
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reg [15:0] histogram_high_num;
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wire src_image_cache_done;
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// 与Windowed模块接口
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wire [7:0] dwidth_conv_min_ch0;
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wire [7:0] dwidth_conv_max_ch0;
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wire [7:0] dwidth_conv_min_ch1;
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wire [7:0] dwidth_conv_max_ch1;
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wire [7:0] dwidth_conv_min_ch2;
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wire [7:0] dwidth_conv_max_ch2;
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// IR图像输入
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reg ir_valid;
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reg ir_vs;
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reg ir_hs;
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reg [7:0] ir_ch0;
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reg [7:0] ir_ch1;
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reg [7:0] ir_ch2;
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// AXI写总线
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wire [AXI_ID_W-1:0] axi_m_awid;
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wire [AXI_ADDR_W-1:0] axi_m_awaddr;
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wire [3:0] axi_m_awlen;
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wire [2:0] axi_m_awsize;
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wire [1:0] axi_m_awburst;
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wire axi_m_awlock;
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wire [3:0] axi_m_awcache;
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wire [2:0] axi_m_awprot;
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wire [3:0] axi_m_awqos;
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wire axi_m_awvalid;
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reg axi_m_awready;
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wire [AXI_ID_W-1:0] axi_m_wid;
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wire [AXI_DATA_W-1:0] axi_m_wdata;
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wire [AXI_STRB_W-1:0] axi_m_wstrb;
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wire axi_m_wlast;
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wire axi_m_wvalid;
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reg axi_m_wready;
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reg [AXI_ID_W-1:0] axi_m_bid;
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reg [1:0] axi_m_bresp;
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reg axi_m_bvalid;
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wire axi_m_bready;
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// 内部测试信号
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reg [15:0] frame_cnt; // 帧计数器
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reg [15:0] ir_row_cnt; // IR行计数器
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reg [15:0] ir_col_cnt; // IR列计数器
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reg [7:0] golden_min_ch0; // 预期CH0最小值
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reg [7:0] golden_max_ch0; // 预期CH0最大值
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reg [7:0] golden_min_ch1; // 预期CH1最小值
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reg [7:0] golden_max_ch1; // 预期CH1最大值
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reg [7:0] golden_min_ch2; // 预期CH2最小值
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reg [7:0] golden_max_ch2; // 预期CH2最大值
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// -------------------------- 时钟生成 --------------------------
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initial begin
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sys_clk = 1'b0;
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forever #(SYS_CLK_PERIOD/2) sys_clk = ~sys_clk;
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end
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initial begin
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ir_clk = 1'b0;
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forever #(IR_CLK_PERIOD/2) ir_clk = ~ir_clk;
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end
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// -------------------------- 实例化DUT --------------------------
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data_cache #(
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.ASYNC_FIFO_DEPTH(ASYNC_FIFO_DEPTH),
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.ASYNC_FIFO_DATA_W(ASYNC_FIFO_DATA_W),
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.SYNC_FIFO_DEPTH(SYNC_FIFO_DEPTH),
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.SYNC_FIFO_DATA_W(SYNC_FIFO_DATA_W),
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.HIST_RAM_DEPTH(HIST_RAM_DEPTH),
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.HIST_RAM_DATA_W(HIST_RAM_DATA_W),
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.AXI_ID_W(AXI_ID_W),
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.AXI_ADDR_W(AXI_ADDR_W),
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.AXI_DATA_W(AXI_DATA_W),
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.AXI_STRB_W(AXI_STRB_W)
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) u_data_cache (
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.clk(sys_clk),
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.rst_n(rst_n),
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.ipa_en(ipa_en),
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.update_src_trig(update_src_trig),
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.input_pixel_type(input_pixel_type),
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.src_pixel_height(src_pixel_height),
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.src_pixel_width(src_pixel_width),
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.histogram_low_num(histogram_low_num),
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.histogram_high_num(histogram_high_num),
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.src_image_cache_done(src_image_cache_done),
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.dwidth_conv_min_ch0(dwidth_conv_min_ch0),
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.dwidth_conv_max_ch0(dwidth_conv_max_ch0),
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.dwidth_conv_min_ch1(dwidth_conv_min_ch1),
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.dwidth_conv_max_ch1(dwidth_conv_max_ch1),
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.dwidth_conv_min_ch2(dwidth_conv_min_ch2),
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.dwidth_conv_max_ch2(dwidth_conv_max_ch2),
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.ir_clk(ir_clk),
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.ir_valid(ir_valid),
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.ir_vs(ir_vs),
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.ir_hs(ir_hs),
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.ir_ch0(ir_ch0),
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.ir_ch1(ir_ch1),
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.ir_ch2(ir_ch2),
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.axi_m_awid(axi_m_awid),
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.axi_m_awaddr(axi_m_awaddr),
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.axi_m_awlen(axi_m_awlen),
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.axi_m_awsize(axi_m_awsize),
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.axi_m_awburst(axi_m_awburst),
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.axi_m_awlock(axi_m_awlock),
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.axi_m_awcache(axi_m_awcache),
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.axi_m_awprot(axi_m_awprot),
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.axi_m_awqos(axi_m_awqos),
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.axi_m_awvalid(axi_m_awvalid),
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.axi_m_awready(axi_m_awready),
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.axi_m_wid(axi_m_wid),
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.axi_m_wdata(axi_m_wdata),
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.axi_m_wstrb(axi_m_wstrb),
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.axi_m_wlast(axi_m_wlast),
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.axi_m_wvalid(axi_m_wvalid),
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.axi_m_wready(axi_m_wready),
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.axi_m_bid(axi_m_bid),
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.axi_m_bresp(axi_m_bresp),
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.axi_m_bvalid(axi_m_bvalid),
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.axi_m_bready(axi_m_bready)
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);
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// -------------------------- 生成FSDB波形 --------------------------
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initial begin
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0, tb_data_cache);
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$fsdbDumpMDA(0, tb_data_cache); // 记录内存和内部信号
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end
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// -------------------------- AXI从机模拟 --------------------------
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// AW通道响应
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always @(posedge sys_clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_awready <= 1'b0;
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end else if (axi_m_awvalid) begin
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// 随机延迟响应，模拟真实从机
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axi_m_awready <= ($random % 2) ? 1'b1 : 1'b0;
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if (!axi_m_awready) begin
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axi_m_awready <= #(SYS_CLK_PERIOD) 1'b1;
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end
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end else begin
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axi_m_awready <= 1'b0;
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end
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end
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// W通道响应
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always @(posedge sys_clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_wready <= 1'b0;
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end else if (axi_m_wvalid) begin
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axi_m_wready <= ($random % 2) ? 1'b1 : 1'b0;
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if (!axi_m_wready) begin
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axi_m_wready <= #(SYS_CLK_PERIOD) 1'b1;
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end
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end else begin
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axi_m_wready <= 1'b0;
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end
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end
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// B通道响应
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always @(posedge sys_clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_bvalid <= 1'b0;
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axi_m_bid <= 8'd0;
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axi_m_bresp <= 2'd0; // 0=OKAY
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end else if (axi_m_wvalid && axi_m_wready) begin
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// W通道传输完成后，延迟1周期发送响应
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axi_m_bvalid <= #(SYS_CLK_PERIOD) 1'b1;
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axi_m_bid <= axi_m_wid;
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end else if (axi_m_bvalid && axi_m_bready) begin
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axi_m_bvalid <= 1'b0;
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end
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end
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// -------------------------- 生成测试图像数据 --------------------------
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task generate_ir_data;
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input integer frame_num;
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input integer is_rgb;
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begin
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// 初始化计数器
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ir_row_cnt = 0;
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ir_col_cnt = 0;
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ir_vs = 1'b0;
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ir_hs = 1'b0;
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ir_valid = 1'b0;
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ir_ch0 = 8'd0;
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ir_ch1 = 8'd0;
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ir_ch2 = 8'd0;
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// 发送帧起始信号（ir_vs至少持续2个ir_clk周期，确保被FIFO捕获）
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@(posedge ir_clk);
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ir_vs = 1'b1;
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ir_valid = 1'b1; // 强制置1，配合DUT的async_fifo_wr_en逻辑
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@(posedge ir_clk);
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@(posedge ir_clk); // 持续2个周期，避免单周期漏采
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ir_vs = 1'b0;
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ir_valid = 1'b0;
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// 计算预期的min/max值
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if (is_rgb) begin
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golden_min_ch0 = 8'd32 + frame_num * 16;
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golden_max_ch0 = 8'd96 + frame_num * 16;
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golden_min_ch1 = 8'd64 + frame_num * 16;
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golden_max_ch1 = 8'd128 + frame_num * 16;
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golden_min_ch2 = 8'd96 + frame_num * 16;
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golden_max_ch2 = 8'd160 + frame_num * 16;
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end else begin
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golden_min_ch0 = 8'd32 + frame_num * 16;
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golden_max_ch0 = 8'd192 + frame_num * 16;
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golden_min_ch1 = 8'd0;
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golden_max_ch1 = 8'd0;
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golden_min_ch2 = 8'd0;
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golden_max_ch2 = 8'd0;
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end
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// 逐行发送数据
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while (ir_row_cnt < IMAGE_HEIGHT) begin
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// 行起始信号
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ir_hs = 1'b1;
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@(posedge ir_clk);
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ir_hs = 1'b0;
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// 逐像素发送数据
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ir_col_cnt = 0;
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while (ir_col_cnt < IMAGE_WIDTH) begin
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ir_valid = 1'b1;
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// 生成有规律的数据便于验证
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if (is_rgb) begin
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// RGB模式：三个通道不同范围
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ir_ch0 = golden_min_ch0 + (ir_row_cnt % (golden_max_ch0 - golden_min_ch0 + 1));
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ir_ch1 = golden_min_ch1 + (ir_col_cnt % (golden_max_ch1 - golden_min_ch1 + 1));
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ir_ch2 = golden_min_ch2 + ((ir_row_cnt + ir_col_cnt) % (golden_max_ch2 - golden_min_ch2 + 1));
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end else begin
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// 灰度模式：仅CH0有效
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ir_ch0 = golden_min_ch0 + ((ir_row_cnt * IMAGE_WIDTH + ir_col_cnt) %
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(golden_max_ch0 - golden_min_ch0 + 1));
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ir_ch1 = 8'd0;
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ir_ch2 = 8'd0;
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end
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@(posedge ir_clk);
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ir_col_cnt = ir_col_cnt + 1;
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end
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// 行结束
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ir_valid = 1'b0;
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ir_row_cnt = ir_row_cnt + 1;
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// 行间隙
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repeat(2) @(posedge ir_clk);
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end
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// 帧结束
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ir_valid = 1'b0;
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// 帧间隙
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repeat(5) @(posedge ir_clk);
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end
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endtask
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// -------------------------- 核心测试流程 --------------------------
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initial begin
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// 初始化
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rst_n = 1'b0;
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ipa_en = 1'b0;
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update_src_trig = 1'b0;
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input_pixel_type = 1'b0; // 默认灰度模式
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src_pixel_height = IMAGE_HEIGHT;
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src_pixel_width = IMAGE_WIDTH;
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histogram_low_num = HIST_LOW_NUM;
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histogram_high_num = HIST_HIGH_NUM;
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frame_cnt = 16'd0;
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axi_m_bid = 8'd0;
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axi_m_bresp = 2'd0;
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axi_m_bvalid = 1'b0;
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// 复位
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#(SYS_CLK_PERIOD * 10);
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rst_n = 1'b1;
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#(SYS_CLK_PERIOD * 5);
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// 测试1：灰度模式单帧测试
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$display("[%0t] Test 1: Gray scale single frame test", $time);
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input_pixel_type = 1'b0; // 灰度模式
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ipa_en = 1'b1;
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#(SYS_CLK_PERIOD * 2);
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// 发送一帧灰度图像
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generate_ir_data(frame_cnt, 0);
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frame_cnt = frame_cnt + 1;
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// 等待缓存完成
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wait(src_image_cache_done == 1'b1);
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#(SYS_CLK_PERIOD * 10);
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// 验证直方图结果
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$display("[%0t] Test 1 Histogram Check: CH0 min=%h (exp=%h), max=%h (exp=%h)",
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$time, dwidth_conv_min_ch0, golden_min_ch0,
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dwidth_conv_max_ch0, golden_max_ch0);
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if (dwidth_conv_min_ch0 != golden_min_ch0 || dwidth_conv_max_ch0 != golden_max_ch0) begin
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$display("[%0t] Test 1 Histogram Check FAILED!", $time);
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end else begin
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$display("[%0t] Test 1 Histogram Check PASSED!", $time);
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end
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#(SYS_CLK_PERIOD * 5);
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// 测试2：RGB模式单帧测试
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$display("[%0t] Test 2: RGB single frame test", $time);
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update_src_trig = 1'b1; // 触发更新
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#(SYS_CLK_PERIOD * 2);
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update_src_trig = 1'b0;
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input_pixel_type = 1'b1; // RGB模式
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#(SYS_CLK_PERIOD * 2);
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// 发送一帧RGB图像
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generate_ir_data(frame_cnt, 1);
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frame_cnt = frame_cnt + 1;
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// 等待缓存完成
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wait(src_image_cache_done == 1'b1);
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#(SYS_CLK_PERIOD * 10);
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// 验证直方图结果
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$display("[%0t] Test 2 Histogram Check: CH0 min=%h (exp=%h), max=%h (exp=%h)",
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$time, dwidth_conv_min_ch0, golden_min_ch0,
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dwidth_conv_max_ch0, golden_max_ch0);
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$display("[%0t] Test 2 Histogram Check: CH1 min=%h (exp=%h), max=%h (exp=%h)",
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$time, dwidth_conv_min_ch1, golden_min_ch1,
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dwidth_conv_max_ch1, golden_max_ch1);
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$display("[%0t] Test 2 Histogram Check: CH2 min=%h (exp=%h), max=%h (exp=%h)",
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$time, dwidth_conv_min_ch2, golden_min_ch2,
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dwidth_conv_max_ch2, golden_max_ch2);
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if (dwidth_conv_min_ch0 != golden_min_ch0 || dwidth_conv_max_ch0 != golden_max_ch0 ||
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dwidth_conv_min_ch1 != golden_min_ch1 || dwidth_conv_max_ch1 != golden_max_ch1 ||
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dwidth_conv_min_ch2 != golden_min_ch2 || dwidth_conv_max_ch2 != golden_max_ch2) begin
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$display("[%0t] Test 2 Histogram Check FAILED!", $time);
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end else begin
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$display("[%0t] Test 2 Histogram Check PASSED!", $time);
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end
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#(SYS_CLK_PERIOD * 5);
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// 测试3：连续两帧测试（验证FIFO和AXI写连续性）
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$display("[%0t] Test 3: Continuous frame test", $time);
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update_src_trig = 1'b1;
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#(SYS_CLK_PERIOD * 2);
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update_src_trig = 1'b0;
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#(SYS_CLK_PERIOD * 2);
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// 发送第3帧（灰度）
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input_pixel_type = 1'b0;
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generate_ir_data(frame_cnt, 0);
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frame_cnt = frame_cnt + 1;
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wait(src_image_cache_done == 1'b1);
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#(SYS_CLK_PERIOD * 5);
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// 发送第4帧（RGB）
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input_pixel_type = 1'b1;
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generate_ir_data(frame_cnt, 1);
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frame_cnt = frame_cnt + 1;
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wait(src_image_cache_done == 1'b1);
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#(SYS_CLK_PERIOD * 10);
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// 测试4：更新触发测试（验证中途更新配置）
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$display("[%0t] Test 4: Update trigger test", $time);
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input_pixel_type = 1'b0;
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generate_ir_data(frame_cnt, 0);
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frame_cnt = frame_cnt + 1;
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// 中途发送更新触发
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#(SYS_CLK_PERIOD * 20);
|
||
update_src_trig = 1'b1;
|
||
#(SYS_CLK_PERIOD * 5);
|
||
update_src_trig = 1'b0;
|
||
#(SYS_CLK_PERIOD * 10);
|
||
|
||
// 所有测试完成
|
||
$display("[%0t] All tests completed!", $time);
|
||
$finish;
|
||
end
|
||
|
||
// -------------------------- 监控AXI写事务 --------------------------
|
||
always @(posedge sys_clk) begin
|
||
if (axi_m_awvalid && axi_m_awready) begin
|
||
$display("[%0t] AXI Write Transaction: Address=0x%08h, Length=%d",
|
||
$time, axi_m_awaddr, axi_m_awlen);
|
||
end
|
||
|
||
if (axi_m_wvalid && axi_m_wready) begin
|
||
$display("[%0t] AXI Write Data: ID=%d, Data[31:0]=0x%08h, Last=%b",
|
||
$time, axi_m_wid, axi_m_wdata[31:0], axi_m_wlast);
|
||
end
|
||
end
|
||
|
||
// -------------------------- 监控状态转换 --------------------------
|
||
reg [2:0] prev_state;
|
||
always @(posedge sys_clk) begin
|
||
prev_state <= u_data_cache.curr_state;
|
||
if (prev_state != u_data_cache.curr_state) begin
|
||
case (u_data_cache.curr_state)
|
||
3'b000: $display("[%0t] Data Cache State: IDLE", $time);
|
||
3'b001: $display("[%0t] Data Cache State: WAIT_VS", $time);
|
||
3'b010: $display("[%0t] Data Cache State: RECEIVE_DATA", $time);
|
||
3'b011: $display("[%0t] Data Cache State: WRITE_FIFO", $time);
|
||
3'b100: $display("[%0t] Data Cache State: WAIT_AXI", $time);
|
||
3'b101: $display("[%0t] Data Cache State: FRAME_DONE", $time);
|
||
endcase
|
||
end
|
||
end
|
||
|
||
endmodule
|