157 lines
3.4 KiB
Verilog
157 lines
3.4 KiB
Verilog
`timescale 1ns/1ps
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module tb_sync_fifo();
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// 参数定义，与被测试模块保持一致
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parameter DATA_WIDTH = 256;
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parameter FIFO_DEPTH = 8;
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// 信号定义
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reg clk;
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reg rst_n;
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reg wr_en;
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reg [DATA_WIDTH-1:0] wr_data;
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wire full;
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reg rd_en;
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wire [DATA_WIDTH-1:0] rd_data;
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wire empty;
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// 生成时钟，周期为10ns（100MHz）
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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// 实例化被测试的FIFO模块
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sync_fifo #(
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.DATA_WIDTH(DATA_WIDTH),
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.FIFO_DEPTH(FIFO_DEPTH)
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) u_sync_fifo (
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.clk(clk),
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.rst_n(rst_n),
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.wr_en(wr_en),
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.wr_data(wr_data),
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.full(full),
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.rd_en(rd_en),
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.rd_data(rd_data),
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.empty(empty)
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);
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// 生成FSDB波形文件
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initial begin
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$fsdbDumpfile("tb.fsdb"); // 指定波形文件名称
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$fsdbDumpvars(0, tb_sync_fifo); // 记录所有层次的信号
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end
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// 测试过程
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initial begin
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// 初始化所有输入信号
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rst_n = 1'b0;
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wr_en = 1'b0;
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wr_data = {DATA_WIDTH{1'b0}};
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rd_en = 1'b0;
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// 复位操作
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#20;
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rst_n = 1'b1;
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#20;
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// 测试1: 连续写入数据直到FIFO满
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$display("Test 1: Writing until FIFO is full");
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rd_en = 1'b0;
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repeat (FIFO_DEPTH + 2) begin // 多写2个验证满状态保护
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wr_data = $urandom_range(1, 255); // 生成1-255的随机数
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wr_en = 1'b1;
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@(posedge clk);
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end
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wr_en = 1'b0;
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#20;
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// 测试2: 连续读出数据直到FIFO空
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$display("Test 2: Reading until FIFO is empty");
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wr_en = 1'b0;
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@(negedge clk);
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rd_en = 1'b1;
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repeat (FIFO_DEPTH + 2) begin // 多读2个验证空状态保护
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@(posedge clk);
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end
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rd_en = 1'b0;
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#20;
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// 测试3: 同时读写操作
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$display("Test 3: Simultaneous read and write");
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repeat (30) begin // 同时进行30次读写
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wr_en = 1'b1;
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rd_en = 1'b1;
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wr_data = $urandom_range(1, 255);
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@(posedge clk);
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end
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wr_en = 1'b0;
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rd_en = 1'b0;
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#20;
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// 测试4: 交替读写（写入一个，读出一个）
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$display("Test 4: Alternate read and write");
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repeat (10) begin
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// 写入一个数据
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wr_en = 1'b1;
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rd_en = 1'b0;
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wr_data = $urandom_range(1, 255);
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@(posedge clk);
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// 读出一个数据
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wr_en = 1'b0;
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rd_en = 1'b1;
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@(posedge clk);
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end
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wr_en = 1'b0;
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rd_en = 1'b0;
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#20;
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// 测试5: 部分填充后连续读写
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$display("Test 5: Partial fill then continuous read/write");
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// 先填充一半
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wr_en = 1'b1;
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rd_en = 1'b0;
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repeat (FIFO_DEPTH/2) begin
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wr_data = $urandom_range(1, 255);
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@(posedge clk);
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end
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// 然后同时读写
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wr_en = 1'b1;
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rd_en = 1'b1;
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repeat (20) begin
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wr_data = $urandom_range(1, 255);
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@(posedge clk);
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end
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// 最后清空FIFO
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wr_en = 1'b0;
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rd_en = 1'b1;
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repeat (FIFO_DEPTH/2) begin
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@(posedge clk);
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end
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rd_en = 1'b0;
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#50;
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$display("All tests completed!");
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$finish;
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end
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// 监控异常操作并打印信息
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always @(posedge clk) begin
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if (wr_en && full) begin
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$display("%t: Error: Trying to write to a full FIFO!", $time);
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end
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if (rd_en && empty) begin
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$display("%t: Error: Trying to read from an empty FIFO!", $time);
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end
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end
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endmodule
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