109 lines
3.7 KiB
Verilog
109 lines
3.7 KiB
Verilog
module data_assemble #(
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parameter PIXEL_WIDTH = 8, // 单通道像素位宽
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parameter GRAY_PIXEL_CNT = 32, // Gray模式：32个8bit→256bit
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parameter RGB_PIXEL_CNT = 8 // RGB模式：8个32bit（24bit数据+8bit补零）→256bit
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) (
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input wire clk,
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input wire rst_n,
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input wire en, // 拼接使能
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input wire input_pixel_type, // 0=Gray，1=RGB
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input wire [PIXEL_WIDTH-1:0] ir_ch0, // CH0数据
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input wire [PIXEL_WIDTH-1:0] ir_ch1, // CH1数据
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input wire [PIXEL_WIDTH-1:0] ir_ch2, // CH2数据
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input wire pixel_valid, // 像素有效
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output reg done, // 拼接完成（256bit就绪）
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output reg [255:0] assembled_data // 拼接后256bit数据
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);
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// 内部信号
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reg [4:0] gray_cnt; // Gray模式计数器（0~31）
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reg [2:0] rgb_cnt; // RGB模式计数器（0~7）
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reg [255:0] data_reg; // 拼接数据寄存器
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reg sync_out,sync_out_r;
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// 拼接计数器复位逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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gray_cnt <= 5'd0;
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rgb_cnt <= 3'd0;
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end else if (!en) begin
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gray_cnt <= 5'd0;
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rgb_cnt <= 3'd0;
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end else if (pixel_valid) begin
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case (input_pixel_type)
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1'b0: begin // Gray模式
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gray_cnt <= (gray_cnt == GRAY_PIXEL_CNT ) ? 5'd0 : gray_cnt + 5'd1;
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end
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1'b1: begin // RGB模式
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rgb_cnt <= (rgb_cnt == RGB_PIXEL_CNT ) ? 3'd0 : rgb_cnt + 3'd1;
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end
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endcase
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end
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end
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// 数据拼接逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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data_reg <= 256'd0;
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assembled_data <= 256'd0;
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sync_out <= 'd0;
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sync_out_r <= 'd0;
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end else if (!en) begin
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sync_out <= 'd0;
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data_reg <= 256'd0;
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assembled_data <= 256'd0;
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done <= 'd0;
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end else if (pixel_valid) begin
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case (input_pixel_type)
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1'b0: begin // Gray模式：32x8bit→256bit（高位到低位拼接）
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data_reg[(GRAY_PIXEL_CNT -1- gray_cnt) * PIXEL_WIDTH +: PIXEL_WIDTH] <= ir_ch0;
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// 计数器满：拼接完成，锁存数据
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if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin
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sync_out = 1'd1;
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//data_reg <= 256'd0; // 复位寄存器，准备下一轮
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end
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end
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1'b1: begin // RGB模式：8x32bit→256bit（32bit=8bit补零+CH2+CH1+CH0）
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reg [31:0] rgb_pixel;
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rgb_pixel = {8'd0, ir_ch2, ir_ch1, ir_ch0}; // 补零+三通道数据
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data_reg[(RGB_PIXEL_CNT - 1 - rgb_cnt) * 32 +: 32] <= rgb_pixel;
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// 计数器满：拼接完成，锁存数据
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if (gray_cnt == GRAY_PIXEL_CNT -1 ) begin
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sync_out = 1'd1;
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//data_reg <= 256'd0; // 复位寄存器，准备下一轮
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end
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end
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endcase
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sync_out_r <= 'd0;
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end else begin
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sync_out_r <= sync_out;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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assembled_data <= 'd0;
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done <= 'd0;
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end else if (sync_out_r) begin
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assembled_data <= data_reg;
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done <= 1'b1;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (done == 1'b1) begin
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done <= 'd0;
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end
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end
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endmodule |