231 lines
9.6 KiB
Verilog
231 lines
9.6 KiB
Verilog
module histogram_ctrl #(
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parameter HIST_RAM_DEPTH = 256,
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parameter HIST_RAM_DATA_W = 1
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) (
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input wire clk,
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input wire rst_n,
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input wire hist_rst, // 直方图复位
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input wire input_pixel_type, // 0=Gray，1=RGB
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input wire hist_wr_en_ch0, // CH0写使能
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input wire [7:0] hist_wr_addr_ch0, // CH0写地址（像素值0~255）
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input wire hist_wr_en_ch1, // CH1写使能
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input wire [7:0] hist_wr_addr_ch1, // CH1写地址
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input wire hist_wr_en_ch2, // CH2写使能
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input wire [7:0] hist_wr_addr_ch2, // CH2写地址
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input wire [15:0] histogram_low_num, // 低位数（计算min）
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input wire [15:0] histogram_high_num,// 高位数（计算max）
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input wire calc_en, // 计算使能
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output reg calc_done, // 计算完成
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output reg [7:0] dwidth_conv_min_ch0,
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output reg [7:0] dwidth_conv_max_ch0,
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output reg [7:0] dwidth_conv_min_ch1,
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output reg [7:0] dwidth_conv_max_ch1,
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output reg [7:0] dwidth_conv_min_ch2,
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output reg [7:0] dwidth_conv_max_ch2
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);
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// 内部信号
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reg [HIST_RAM_DATA_W-1:0] hist_ram_ch0 [HIST_RAM_DEPTH-1:0]; // CH0直方图RAM
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reg [HIST_RAM_DATA_W-1:0] hist_ram_ch1 [HIST_RAM_DEPTH-1:0]; // CH1直方图RAM
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reg [HIST_RAM_DATA_W-1:0] hist_ram_ch2 [HIST_RAM_DEPTH-1:0]; // CH2直方图RAM
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reg [7:0] calc_addr; // 遍历地址（0~255）
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reg [15:0] low_cnt_ch0; // CH0低位数计数器
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reg [15:0] high_cnt_ch0; // CH0高位数计数器
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reg [15:0] low_cnt_ch1; // CH1低位数计数器
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reg [15:0] high_cnt_ch1; // CH1高位数计数器
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reg [15:0] low_cnt_ch2; // CH2低位数计数器
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reg [15:0] high_cnt_ch2; // CH2高位数计数器
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reg calc_active; // 计算活跃标记
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// 状态定义
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localparam [1:0] S_HIST_IDLE = 2'b00;
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localparam [1:0] S_HIST_CLEAR = 2'b01;
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localparam [1:0] S_HIST_WRITE = 2'b10;
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localparam [1:0] S_HIST_CALC = 2'b11;
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reg [1:0] curr_hist_state;
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reg [1:0] next_hist_state;
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// 1. 状态机时序逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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curr_hist_state <= S_HIST_IDLE;
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end else begin
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curr_hist_state <= next_hist_state;
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end
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end
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// 2. 状态机组合逻辑
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always @(*) begin
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next_hist_state = curr_hist_state;
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case (curr_hist_state)
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S_HIST_IDLE: begin
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if (hist_rst) begin
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next_hist_state = S_HIST_CLEAR;
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end else if (hist_wr_en_ch0 || hist_wr_en_ch1 || hist_wr_en_ch2) begin
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next_hist_state = S_HIST_WRITE;
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end else if (calc_en) begin
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next_hist_state = S_HIST_CALC;
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end
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end
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S_HIST_CLEAR: begin
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if (calc_addr == HIST_RAM_DEPTH - 1) begin
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next_hist_state = S_HIST_IDLE;
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end
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end
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S_HIST_WRITE: begin
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if (hist_rst) begin
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next_hist_state = S_HIST_CLEAR;
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end else if (calc_en) begin
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next_hist_state = S_HIST_CALC;
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end
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end
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S_HIST_CALC: begin
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if (calc_addr == HIST_RAM_DEPTH - 1) begin
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next_hist_state = S_HIST_IDLE;
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end
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end
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endcase
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end
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// 3. 直方图RAM复位/写逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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// 复位所有RAM
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integer i;
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for (i = 0; i < HIST_RAM_DEPTH; i = i+1) begin
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hist_ram_ch0[i] <= 1'b0;
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hist_ram_ch1[i] <= 1'b0;
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hist_ram_ch2[i] <= 1'b0;
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end
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calc_addr <= 8'd0;
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end else begin
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case (curr_hist_state)
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S_HIST_CLEAR: begin
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// 清空RAM（地址递增）
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hist_ram_ch0[calc_addr] <= 1'b0;
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hist_ram_ch1[calc_addr] <= 1'b0;
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hist_ram_ch2[calc_addr] <= 1'b0;
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calc_addr <= calc_addr + 8'd1;
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end
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S_HIST_WRITE: begin
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// CH0写（始终有效）
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if (hist_wr_en_ch0) begin
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hist_ram_ch0[hist_wr_addr_ch0] <= 1'b1; // 标记像素值存在
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end
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// CH1/CH2写（仅RGB模式有效）
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if (hist_wr_en_ch1 && (input_pixel_type == 1'b1)) begin
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hist_ram_ch1[hist_wr_addr_ch1] <= 1'b1;
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end
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if (hist_wr_en_ch2 && (input_pixel_type == 1'b1)) begin
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hist_ram_ch2[hist_wr_addr_ch2] <= 1'b1;
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end
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calc_addr <= 8'd0;
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end
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S_HIST_CALC: begin
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// 遍历地址递增
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calc_addr <= calc_addr + 8'd1;
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end
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default: begin
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calc_addr <= 8'd0;
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end
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endcase
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end
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end
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// 4. 修复后的直方图min/max计算逻辑（关键修复点）
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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low_cnt_ch0 <= 16'd0;
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high_cnt_ch0 <= 16'd0;
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low_cnt_ch1 <= 16'd0;
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high_cnt_ch1 <= 16'd0;
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low_cnt_ch2 <= 16'd0;
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high_cnt_ch2 <= 16'd0;
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dwidth_conv_min_ch0 <= 8'd0;
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dwidth_conv_max_ch0 <= 8'd255;
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dwidth_conv_min_ch1 <= 8'd0;
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dwidth_conv_max_ch1 <= 8'd255;
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dwidth_conv_min_ch2 <= 8'd0;
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dwidth_conv_max_ch2 <= 8'd255;
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calc_done <= 1'b0;
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calc_active <= 1'b0;
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end else begin
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calc_done <= 1'b0;
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case (curr_hist_state)
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S_HIST_CALC: begin
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calc_active <= 1'b1;
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// -------------------------- 关键修复1：计算开始时强制清零计数器 --------------------------
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if (calc_addr == 8'd0) begin // 遍历地址为0时（计算起始），清零所有计数器
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low_cnt_ch0 <= 16'd0;
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high_cnt_ch0 <= 16'd0;
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low_cnt_ch1 <= 16'd0;
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high_cnt_ch1 <= 16'd0;
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low_cnt_ch2 <= 16'd0;
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high_cnt_ch2 <= 16'd0;
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end
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// -------------------------- CH0计算 --------------------------
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// min：0→255遍历，找第histogram_low_num个1
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if (low_cnt_ch0 < histogram_low_num && hist_ram_ch0[calc_addr] == 1'b1) begin
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low_cnt_ch0 <= low_cnt_ch0 + 16'd1;
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if (low_cnt_ch0 == histogram_low_num - 16'd1) begin
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dwidth_conv_min_ch0 <= calc_addr;
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end
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end
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// max：255→0遍历，找第histogram_high_num个1
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if (high_cnt_ch0 < histogram_high_num && hist_ram_ch0[255 - calc_addr] == 1'b1) begin
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high_cnt_ch0 <= high_cnt_ch0 + 16'd1;
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if (high_cnt_ch0 == histogram_high_num - 16'd1) begin
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dwidth_conv_max_ch0 <= 255 - calc_addr;
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end
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end
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// -------------------------- CH1计算（仅RGB模式） --------------------------
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if (input_pixel_type == 1'b1) begin
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if (low_cnt_ch1 < histogram_low_num && hist_ram_ch1[calc_addr] == 1'b1) begin
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low_cnt_ch1 <= low_cnt_ch1 + 16'd1;
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if (low_cnt_ch1 == histogram_low_num - 16'd1) begin
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dwidth_conv_min_ch1 <= calc_addr;
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end
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end
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if (high_cnt_ch1 < histogram_high_num && hist_ram_ch1[255 - calc_addr] == 1'b1) begin
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high_cnt_ch1 <= high_cnt_ch1 + 16'd1;
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if (high_cnt_ch1 == histogram_high_num - 16'd1) begin
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dwidth_conv_max_ch1 <= 255 - calc_addr;
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end
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end
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end
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// -------------------------- CH2计算（仅RGB模式） --------------------------
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if (input_pixel_type == 1'b1) begin
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if (low_cnt_ch2 < histogram_low_num && hist_ram_ch2[calc_addr] == 1'b1) begin
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low_cnt_ch2 <= low_cnt_ch2 + 16'd1;
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if (low_cnt_ch2 == histogram_low_num - 16'd1) begin
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dwidth_conv_min_ch2 <= calc_addr;
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end
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end
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if (high_cnt_ch2 < histogram_high_num && hist_ram_ch2[255 - calc_addr] == 1'b1) begin
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high_cnt_ch2 <= high_cnt_ch2 + 16'd1;
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if (high_cnt_ch2 == histogram_high_num - 16'd1) begin
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dwidth_conv_max_ch2 <= 255 - calc_addr;
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end
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end
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end
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// -------------------------- 遍历结束：置位完成信号 --------------------------
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if (calc_addr == HIST_RAM_DEPTH - 1) begin
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calc_done <= 1'b1;
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calc_active <= 1'b0;
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end
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end
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default: begin
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calc_active <= 1'b0;
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calc_done <= 1'b0;
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end
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endcase
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end
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end
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endmodule |