27 lines
599 B
Verilog
27 lines
599 B
Verilog
module rst_sync #(
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parameter SYNC_STAGE = 2 // 同步级数（推荐2级）
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) (
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input wire clk,
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input wire rst_n_in,
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output reg rst_n_out
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);
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reg [SYNC_STAGE-1:0] rst_sync_reg;
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always @(posedge clk or negedge rst_n_in) begin
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if (!rst_n_in) begin
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rst_sync_reg <= {SYNC_STAGE{1'b0}};
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end else begin
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rst_sync_reg <= {rst_sync_reg[SYNC_STAGE-2:0], 1'b1};
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end
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end
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always @(posedge clk or negedge rst_n_in) begin
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if (!rst_n_in) begin
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rst_n_out <= 1'b0;
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end else begin
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rst_n_out <= rst_sync_reg[SYNC_STAGE-1];
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end
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end
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endmodule |