315 lines
9.7 KiB
Verilog
315 lines
9.7 KiB
Verilog
`timescale 1ns/1ps
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module tb_axi_write_ctrl();
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// -------------------------- 1. 参数定义 --------------------------
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parameter AXI_ID_W = 8;
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parameter AXI_ADDR_W = 32;
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parameter AXI_DATA_W = 256;
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parameter AXI_STRB_W = AXI_DATA_W / 8;
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parameter CLK_PERIOD = 10;
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parameter FIFO_DEPTH = 4;
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// -------------------------- 2. 信号定义 --------------------------
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// 系统时钟/复位
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reg clk;
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reg rst_n;
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// 控制与数据输入
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reg start_en;
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reg [AXI_ADDR_W-1:0] sram_base_addr;
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wire [AXI_DATA_W-1:0] fifo_rd_data;
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wire fifo_empty;
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wire fifo_rd_en_dut; // DUT输出的读使能（仅由DUT驱动）
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// Testbench控制的FIFO读使能（用于清空FIFO）
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reg tb_fifo_rd_en;
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// 合并后的FIFO读使能（仅驱动FIFO，避免直接驱动DUT输出）
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wire fifo_rd_en = tb_fifo_rd_en | fifo_rd_en_dut;
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// AXI AW通道
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wire [AXI_ID_W-1:0] axi_m_awid;
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wire [AXI_ADDR_W-1:0] axi_m_awaddr;
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wire [3:0] axi_m_awlen;
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wire [2:0] axi_m_awsize;
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wire [1:0] axi_m_awburst;
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wire axi_m_awlock;
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wire [4:0] axi_m_awcache;
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wire [2:0] axi_m_awprot;
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wire [4:0] axi_m_awqos;
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wire axi_m_awvalid;
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reg axi_m_awready;
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// AXI W通道
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wire [AXI_ID_W-1:0] axi_m_wid;
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wire [AXI_DATA_W-1:0] axi_m_wdata;
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wire [AXI_STRB_W-1:0] axi_m_wstrb;
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wire axi_m_wlast;
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wire axi_m_wvalid;
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reg axi_m_wready;
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// AXI B通道
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reg [AXI_ID_W-1:0] axi_m_bid;
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reg [1:0] axi_m_bresp;
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reg axi_m_bvalid;
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wire axi_m_bready;
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// DUT状态输出
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wire axi_busy;
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wire axi_done;
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// FIFO相关控制信号
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reg fifo_wr_en;
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reg [AXI_DATA_W-1:0] fifo_wr_data;
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wire fifo_full;
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reg [$clog2(FIFO_DEPTH)-1:0] fifo_wr_ptr;
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// -------------------------- 3. 生成系统时钟 --------------------------
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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// -------------------------- 4. 实例化DUT（AXI写控制器） --------------------------
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axi_write_ctrl #(
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.AXI_ID_W (AXI_ID_W),
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.AXI_ADDR_W (AXI_ADDR_W),
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.AXI_DATA_W (AXI_DATA_W),
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.AXI_STRB_W (AXI_STRB_W)
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) u_axi_write_ctrl (
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.clk (clk),
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.rst_n (rst_n),
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.start_en (start_en),
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.sram_base_addr (sram_base_addr),
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.fifo_rd_data (fifo_rd_data),
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.fifo_empty (fifo_empty),
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.fifo_rd_en (fifo_rd_en_dut), // DUT输出单独命名，避免冲突
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.axi_m_awid (axi_m_awid),
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.axi_m_awaddr (axi_m_awaddr),
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.axi_m_awlen (axi_m_awlen),
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.axi_m_awsize (axi_m_awsize),
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.axi_m_awburst (axi_m_awburst),
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.axi_m_awlock (axi_m_awlock),
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.axi_m_awcache (axi_m_awcache),
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.axi_m_awprot (axi_m_awprot),
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.axi_m_awqos (axi_m_awqos),
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.axi_m_awvalid (axi_m_awvalid),
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.axi_m_awready (axi_m_awready),
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.axi_m_wid (axi_m_wid),
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.axi_m_wdata (axi_m_wdata),
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.axi_m_wstrb (axi_m_wstrb),
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.axi_m_wlast (axi_m_wlast),
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.axi_m_wvalid (axi_m_wvalid),
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.axi_m_wready (axi_m_wready),
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.axi_m_bid (axi_m_bid),
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.axi_m_bresp (axi_m_bresp),
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.axi_m_bvalid (axi_m_bvalid),
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.axi_m_bready (axi_m_bready),
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.axi_busy (axi_busy),
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.axi_done (axi_done)
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);
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// -------------------------- 5. 实例化sync_fifo模块 --------------------------
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sync_fifo #(
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.DATA_WIDTH (AXI_DATA_W),
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.FIFO_DEPTH (FIFO_DEPTH)
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) u_sync_fifo (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (fifo_wr_en),
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.wr_data (fifo_wr_data),
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.full (fifo_full),
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.rd_en (fifo_rd_en), // 使用合并后的读使能
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.rd_data (fifo_rd_data),
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.empty (fifo_empty)
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);
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// -------------------------- 6. 生成FSDB波形文件 --------------------------
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initial begin
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$fsdbDumpfile("tb.fsdb");
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$fsdbDumpvars(0, tb_axi_write_ctrl);
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$fsdbDumpMDA(0, tb_axi_write_ctrl);
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end
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// -------------------------- 7. FIFO初始化与数据写入 --------------------------
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reg [AXI_DATA_W-1:0] fifo_init_data[FIFO_DEPTH-1:0];
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initial begin
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fifo_init_data[0] = 256'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f;
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fifo_init_data[1] = 256'h20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f;
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fifo_init_data[2] = 256'h40414243_44454647_48494a4b_4c4d4e4f_50515253_54555657_58595a5b_5c5d5e5f;
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fifo_init_data[3] = 256'h60616263_64656667_68696a6b_6c6d6e6f_70717273_74757677_78797a7b_7c7d7e7f;
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end
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task fill_fifo;
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input integer count;
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begin
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fifo_wr_en = 1'b1;
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repeat(count) begin
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@(posedge clk);
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if (!fifo_full) begin
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fifo_wr_data = fifo_init_data[fifo_wr_ptr];
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fifo_wr_ptr = fifo_wr_ptr + 1'b1;
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if (fifo_wr_ptr >= FIFO_DEPTH) fifo_wr_ptr = 0;
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end
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end
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fifo_wr_en = 1'b0;
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@(posedge clk);
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end
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endtask
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// -------------------------- 8. 模拟AXI从机 --------------------------
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_awready <= 1'b0;
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end else if (axi_m_awvalid) begin
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axi_m_awready <= ($random % 2) ? 1'b1 : 1'b0;
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if (!axi_m_awready && axi_m_awvalid) begin
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axi_m_awready <= #(CLK_PERIOD) 1'b1;
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end
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end else begin
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axi_m_awready <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_wready <= 1'b0;
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end else if (axi_m_wvalid) begin
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axi_m_wready <= ($random % 2) ? 1'b1 : 1'b0;
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if (!axi_m_wready && axi_m_wvalid) begin
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axi_m_wready <= #(CLK_PERIOD) 1'b1;
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end
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end else begin
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axi_m_wready <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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axi_m_bvalid <= 1'b0;
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axi_m_bid <= 8'd0;
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axi_m_bresp <= 2'd0;
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end else if (axi_m_wvalid && axi_m_wready) begin
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axi_m_bvalid <= #(CLK_PERIOD) 1'b1;
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axi_m_bid <= axi_m_wid;
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end else if (axi_m_bvalid && axi_m_bready) begin
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axi_m_bvalid <= 1'b0;
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end
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end
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// -------------------------- 9. 核心测试场景 --------------------------
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initial begin
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rst_n = 1'b0;
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start_en = 1'b0;
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sram_base_addr = 32'h1000_0000;
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fifo_wr_en = 1'b0;
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fifo_wr_data = {AXI_DATA_W{1'b0}};
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fifo_wr_ptr = 0;
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tb_fifo_rd_en = 1'b0;
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axi_m_bid = 8'd0;
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axi_m_bresp = 2'd0;
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axi_m_bvalid = 1'b0;
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#(CLK_PERIOD * 5);
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rst_n = 1'b1;
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#(CLK_PERIOD * 2);
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// 测试1：单事务写
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$display("[%0t] Test 1: Single AXI Write Transaction", $time);
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fill_fifo(FIFO_DEPTH);
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start_en = 1'b1;
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#(CLK_PERIOD);
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start_en = 1'b0;
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wait(axi_done == 1'b1);
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#(CLK_PERIOD);
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$display("[%0t] Test 1 Result: AWAddr=0x%08h (Expected:0x10000000), WData Match=%b",
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$time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[0]));
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#(CLK_PERIOD * 2);
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// 测试2：连续事务写
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$display("[%0t] Test 2: Continuous AXI Write Transactions", $time);
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fill_fifo(FIFO_DEPTH);
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#(CLK_PERIOD);
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start_en = 1'b1;
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#(CLK_PERIOD);
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start_en = 1'b0;
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wait(axi_done == 1'b1);
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#(CLK_PERIOD);
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$display("[%0t] Test 2 Trans1: AWAddr=0x%08h (Expected:0x10000020), WData Match=%b",
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$time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[1]));
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fill_fifo(FIFO_DEPTH);
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#(CLK_PERIOD);
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start_en = 1'b1;
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#(CLK_PERIOD);
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start_en = 1'b0;
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wait(axi_done == 1'b1);
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#(CLK_PERIOD);
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$display("[%0t] Test 2 Trans2: AWAddr=0x%08h (Expected:0x10000040), WData Match=%b",
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$time, axi_m_awaddr, (axi_m_wdata == fifo_init_data[2]));
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#(CLK_PERIOD * 2);
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// 测试3：FIFO空阻塞
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$display("[%0t] Test 3: FIFO Empty Block Test", $time);
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tb_fifo_rd_en = 1'b1; // 使用Testbench读使能清空FIFO
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while (!fifo_empty) begin
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@(posedge clk);
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end
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tb_fifo_rd_en = 1'b0;
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#(CLK_PERIOD);
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start_en = 1'b1;
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#(CLK_PERIOD * 3);
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start_en = 1'b0;
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$display("[%0t] Test 3 Result: AXI Busy=%b (Expected:0), AWValid=%b (Expected:0)",
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$time, axi_busy, axi_m_awvalid);
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#(CLK_PERIOD * 2);
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// 测试4：AXI握手延迟
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$display("[%0t] Test 4: AXI Handshake Delay Test", $time);
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fill_fifo(FIFO_DEPTH);
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#(CLK_PERIOD);
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axi_m_awready <= 1'b0;
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axi_m_wready <= 1'b0;
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start_en = 1'b1;
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#(CLK_PERIOD);
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start_en = 1'b0;
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#(CLK_PERIOD * 2);
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axi_m_awready <= 1'b1;
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#(CLK_PERIOD);
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axi_m_wready <= 1'b1;
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wait(axi_done == 1'b1);
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#(CLK_PERIOD);
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$display("[%0t] Test 4 Result: WData Match=%b (Expected:1), Done=%b (Expected:1)",
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$time, (axi_m_wdata == fifo_init_data[3]), axi_done);
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#(CLK_PERIOD * 2);
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$display("[%0t] All Tests Completed!", $time);
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$finish;
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end
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// -------------------------- 10. 状态监控 --------------------------
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reg [1:0] axi_state;
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always @(posedge clk) begin
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axi_state = u_axi_write_ctrl.axi_state;
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end
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always @(posedge clk) begin
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case (axi_state)
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2'd0: $display("[%0t] AXI State: IDLE", $time);
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2'd1: $display("[%0t] AXI State: AW (Address Channel)", $time);
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2'd2: $display("[%0t] AXI State: W (Data Channel)", $time);
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2'd3: $display("[%0t] AXI State: B (Response Channel)", $time);
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endcase
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end
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endmodule
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